JPS60154647A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60154647A JPS60154647A JP59010181A JP1018184A JPS60154647A JP S60154647 A JPS60154647 A JP S60154647A JP 59010181 A JP59010181 A JP 59010181A JP 1018184 A JP1018184 A JP 1018184A JP S60154647 A JPS60154647 A JP S60154647A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- silicon carbide
- layer
- alumina
- sealing glass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔・〜技術分野〕
一本発明は半導体装置、特に、少量のベリリウムを含む
炭化ケイ素を主成分とする材料を用いてなる半導体装置
に適用して効果のある技術に関する。[Detailed Description of the Invention] [Technical Field] The present invention relates to a technique that is effective when applied to a semiconductor device, particularly a semiconductor device using a material whose main component is silicon carbide containing a small amount of beryllium. .
０．５〜３．５重量％のベリリウムを含む炭化ケイ素を
ホットプレスして得た電気絶縁性の炭化ケイ素（以下、
単に電気絶縁性炭化ケイ素と称する）は、（１１電気絶
縁性が大きい、（２）゛熱伝導率が大きい、Ｉ＊）＃、
ＬｉＪＬａｉ、１ｌｆＺシ１１コンシ祈ｒ？＞ （Ａ１
ｍＷｍ６度が大きい等の利点があるので、アルミナセラ
ミックに代る電気絶縁用基板として注目を集めている（
たとえば特開昭５６−６６０８６号および特開昭５７−
２５９１号公報診照）。Electrically insulating silicon carbide (hereinafter referred to as
(simply referred to as electrically insulating silicon carbide) has (11 high electrical insulation, (2) high thermal conductivity, I*)#,
LiJLai, 1lfZ shi 11 consi prayer? > (A1
Because it has advantages such as a large mWm6 degree, it is attracting attention as an electrically insulating substrate as an alternative to alumina ceramic (
For example, JP-A-56-66086 and JP-A-57-
Publication No. 2591).
ところで、電気絶縁性炭化ケイ素を利用したパッケージ
基板においては、封止用ガラス（低融点ガラス）との密
着性が比較的弱く、ガラス封止の信頼性が低下するおそ
れのあることが本発明者により明らかとされた。By the way, the present inventor has discovered that in a package substrate using electrically insulating silicon carbide, the adhesion with the sealing glass (low melting point glass) is relatively weak, which may reduce the reliability of the glass seal. It was made clear by
また、電気路、縁性炭化ケイ素を利用したパッケージ基
板上に導体配線を形成する場合には、基板の誘電率が高
いために問題が生じることが本発者により解明された。In addition, the present inventor has discovered that when forming electrical paths and conductor wiring on a package substrate using edged silicon carbide, problems arise due to the high dielectric constant of the substrate.
本発明の目的は、電気絶縁性炭化ケイ素を主成分とする
基板のガラス接着性、配線特性を向上させることを目的
とするものである。An object of the present invention is to improve the glass adhesion and wiring characteristics of a substrate containing electrically insulating silicon carbide as a main component.
本発明の前記ならびにその他の目的と新規な心像け、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel aspects of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、電気絶縁性炭化ケイ素からなる基板上にアル
ミナ層を介して封止ガラスまたは配線を施こすことてよ
り前記目的を達成するものである。That is, the above object is achieved by providing sealing glass or wiring on a substrate made of electrically insulating silicon carbide with an alumina layer interposed therebetween.
〔実施例１〕
第１図は本発明の一実施例である半導体装置の断面図、
第２図はその封止ガラス接着部の拡大部分断面図である
、
この半導体装置如おいては、パンケージ基板１け乗気絶
縁性炭化ケイ素からなる材料を用いて形成されている。[Example 1] FIG. 1 is a cross-sectional view of a semiconductor device which is an example of the present invention.
FIG. 2 is an enlarged partial sectional view of the sealing glass adhesive portion. In this semiconductor device, the pan cage substrate 1 is formed using a material made of insulating silicon carbide.
この基板１の中央部表面上には、シリコン（Ｓｔ）等の
ベレット２が接着層３等で取り付けられている。A pellet 2 made of silicon (St) or the like is attached to the central surface of the substrate 1 with an adhesive layer 3 or the like.
一方、基板１の周囲表面上には、封止用ガラス４および
リード５を介Ｉ−て、電気絶縁性炭化ケイ素からなるキ
ナ／プロが接着される。On the other hand, on the peripheral surface of the substrate 1, Kina/Pro made of electrically insulating silicon carbide is adhered via a sealing glass 4 and a lead 5.
前記ベレット２のポンディングパッドとリード５のイン
ナーリード部とはワイヤ７で電気的に接続されている。The bonding pad of the pellet 2 and the inner lead portion of the lead 5 are electrically connected by a wire 7.
本実施例では、前記封止ガラス４を基板１上に接着する
に際して、第２図に示すように、基板１上にアルミナ（
α−ＡｊＬＯｓ）層８が設けら才１ている。このアルミ
ナ層４は基板１上にアルミナ材料をスクリーン印刷等で
被着した後に約１０００℃で焼成することにより形成さ
れろ。In this embodiment, when bonding the sealing glass 4 onto the substrate 1, as shown in FIG.
An α-AjLOs layer 8 is provided. This alumina layer 4 is formed by depositing an alumina material on the substrate 1 by screen printing or the like and then firing it at about 1000°C.
本実施例によれば、封止ガラス４がアルミナ層８を介し
て基板上に接着されている。ｊ≦Ｊ止カシカラス４ルミ
ナ層８との密着性は良く、かつアルミナ層８け基板１上
に焼成されることによって強く密着している。従って、
基板１と封止ガラス４とは強力に接着され、封止カラス
接着部の信頼性が著しく向上する。According to this embodiment, the sealing glass 4 is bonded onto the substrate via the alumina layer 8. j≦J The adhesion between the alumina layer 8 and the alumina layer 8 is good, and the alumina layer 8 is strongly adhered to the substrate 1 by being fired. Therefore,
The substrate 1 and the sealing glass 4 are strongly bonded to each other, and the reliability of the sealing glass bonding portion is significantly improved.
第１図において、上記アルミナ層、８＆よ図示を省略し
ている。In FIG. 1, illustration of the alumina layer 8& is omitted.
上記アルミナ層８け封止ガラス４の下部のみに設けても
、基板１上全面に設けてもよい。The alumina layer 8 may be provided only on the lower part of the sealing glass 4, or may be provided on the entire surface of the substrate 1.
また、キャップの材料６として’ｒｌｆ、気絶縁性炭化
ケイ素を用いているので、キヤ、７ブ６の封止ガラス４
が被着される部分に、上記アルミナ層８を設けてもよい
。In addition, since 'rlf, gas insulating silicon carbide, is used as the material 6 of the cap, the sealing glass 4 of the cap 6 is
The alumina layer 8 may be provided on the portion where the alumina is deposited.
なお、チップ２の下部にアルミナ層８を設ける場合は、
熱膨張係数の差を考慮して、接着層３として応力吸収で
きるシリコンゴム等の弾性材料を用いてもよい。In addition, when providing the alumina layer 8 at the bottom of the chip 2,
In consideration of the difference in thermal expansion coefficient, an elastic material such as silicone rubber that can absorb stress may be used as the adhesive layer 3.
〔実施例２〕
第３図は本発明の実施例２である半導体装置の基板の拡
大部分断面図である。[Embodiment 2] FIG. 3 is an enlarged partial sectional view of a substrate of a semiconductor device according to Embodiment 2 of the present invention.
この実施例では、市、気絶練性炭化ケイ素からなる基板
１の上にアルミナ層８を介して銅又りアルミニウムから
なる導体配線層９が形成され、その上にベレット２が半
田バンブ１０で面実装（フェイスダウンボンティング）
されている。In this embodiment, a conductive wiring layer 9 made of copper or aluminum is formed on a substrate 1 made of swollen silicon carbide with an alumina layer 8 interposed therebetween, and a pellet 2 is placed on the surface with solder bumps 10. Implementation (face down bonding)
has been done.
この場合には、アルミナの誘電率（９，４）が誘電率（
４２）よりも非常に小さいので、配線層９をＳｊＣの基
板１上に直接形成する場合に比べて配線層９のノイズや
配線容量が減少し、極めて良好な布線特性が得られる。In this case, the dielectric constant (9,4) of alumina is
42), the noise and wiring capacitance of the wiring layer 9 are reduced compared to the case where the wiring layer 9 is directly formed on the SJC substrate 1, and extremely good wiring characteristics can be obtained.
この例においても、アルミナ層８上に、第１図に示すよ
うに、封止カラスを設はキャップを被着してもよい。実
施例１と全く同一の効果が得られる。In this example as well, a sealing glass may be provided on the alumina layer 8 as shown in FIG. 1, or a cap may be attached thereto. Exactly the same effect as in Example 1 can be obtained.
なお、実施例１においても、リード５と基板１との間の
容量を減少させろことができることはもちろんである。It goes without saying that in the first embodiment as well, the capacitance between the lead 5 and the substrate 1 can be reduced.
（１）炭化ケイ素を主成分とする基板上にアルミブ一層
を介して封止ガラスを施こすことにより、封止ガラスと
アルミナの密着性が良いので制止ガラスの接着力が大き
くなり、イ８頼性を向上できる。(1) By applying sealing glass to a substrate whose main component is silicon carbide through a single layer of aluminum, the adhesion between the sealing glass and alumina is good, increasing the adhesion force of the sealing glass. You can improve your sexuality.
（２）炭化ケイ素を主成分とする基板上てアルミツ一層
を介して配線を施こすことにより、アルミナσ）誘電率
が炭化ケイ素のそれよりも低いσ）で、配線のノイズや
容量゛が減少し、布線特性を向上できる。(2) By wiring through a single layer of aluminum on a substrate whose main component is silicon carbide, alumina σ) has a dielectric constant lower than that of silicon carbide, reducing wiring noise and capacitance. and can improve wiring characteristics.
（３） アルミナ層を基板上に焼成することにより、良
好な密着性が得られる。(3) Good adhesion can be obtained by firing the alumina layer onto the substrate.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.
たとえば、アルミナ層の形成方法等は前記実施例に限定
されるものではない。For example, the method of forming the alumina layer is not limited to the above embodiment.
〔利用分野］
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるフラットパッケージ
およびフリップチップ型の半導体装置に適用した場合に
ついて説明したが、それに限定されるものではなく、た
とえば、それ以外のパッケージ構造の半導体装置にも広
く適用でき、またマルチチップモジュール等にも適用で
きる。[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to flat package and flip-chip type semiconductor devices, which are the background application fields, but the present invention is not limited thereto. For example, it can be widely applied to semiconductor devices with other package structures, and can also be applied to multi-chip modules.
第１図は本発明の一実施例である半導体装置の断面図、
第２図はその封止ガラス接着部の拡大部分断面図、
第３図は本発明の他の実施例の拡大部分断面図である。
１・・・パッケージ基板、２・・・ベレット、３・・・
接着層、４・・・封止ガラス、５・・・リード、６・・
・ワイヤ、８・・・アルミナ層、９・・・導体配線層、
１ｏ・・・半田バンプ。FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is an enlarged partial cross-sectional view of the sealing glass adhesive part, and FIG. 3 is an enlarged partial cross-sectional view of another embodiment of the present invention. It is. 1...Package board, 2...Bellet, 3...
Adhesive layer, 4... Sealing glass, 5... Lead, 6...
・Wire, 8... Alumina layer, 9... Conductor wiring layer,
1o...Solder bump.
Claims (1)
して封止ガラスまたは配線を施こしてなることを特徴と
する半導体装置。 ２、アルミナ層は基板上に焼成されていることを特徴と
する特許請求の範囲第１項記載の半導体装置、[Scope of Claims] 1. A semiconductor device characterized by forming a sealing glass or wiring on a substrate mainly composed of silicon carbide with an alumina layer interposed therebetween. 2. The semiconductor device according to claim 1, wherein the alumina layer is fired on the substrate;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59010181A JPS60154647A (en) | 1984-01-25 | 1984-01-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59010181A JPS60154647A (en) | 1984-01-25 | 1984-01-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60154647A true JPS60154647A (en) | 1985-08-14 |
Family
ID=11743116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59010181A Pending JPS60154647A (en) | 1984-01-25 | 1984-01-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60154647A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6247153A (en) * | 1985-08-27 | 1987-02-28 | Ibiden Co Ltd | Semiconductor device |
| JPS62144347A (en) * | 1985-12-19 | 1987-06-27 | Sutatsukusu Kogyo Kk | Semiconductor device for high-fidelity audio apparatus |
| US5087964A (en) * | 1989-10-31 | 1992-02-11 | Mitsubishi Denki Kabushiki Kaisha | Package for a light-responsive semiconductor chip |
-
1984
- 1984-01-25 JP JP59010181A patent/JPS60154647A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6247153A (en) * | 1985-08-27 | 1987-02-28 | Ibiden Co Ltd | Semiconductor device |
| JPS62144347A (en) * | 1985-12-19 | 1987-06-27 | Sutatsukusu Kogyo Kk | Semiconductor device for high-fidelity audio apparatus |
| US5087964A (en) * | 1989-10-31 | 1992-02-11 | Mitsubishi Denki Kabushiki Kaisha | Package for a light-responsive semiconductor chip |
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