JPH0936119A - Semiconductor device, its manufacture and semiconductor unit using the semiconductor device - Google Patents

Semiconductor device, its manufacture and semiconductor unit using the semiconductor device

Info

Publication number
JPH0936119A
JPH0936119A JP7180268A JP18026895A JPH0936119A JP H0936119 A JPH0936119 A JP H0936119A JP 7180268 A JP7180268 A JP 7180268A JP 18026895 A JP18026895 A JP 18026895A JP H0936119 A JPH0936119 A JP H0936119A
Authority
JP
Japan
Prior art keywords
semiconductor device
circuit board
sealing resin
semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7180268A
Other languages
Japanese (ja)
Inventor
Masahiro Ono
正浩 小野
Yoshihiro Bessho
芳宏 別所
Yoshihiro Tomura
善広 戸村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7180268A priority Critical patent/JPH0936119A/en
Publication of JPH0936119A publication Critical patent/JPH0936119A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Abstract

PROBLEM TO BE SOLVED: To prevent the exfoliation of a semiconductor device and sealing resin caused by the stress generated by the difference in thermal expansion coefficient of a semiconductor device, a circuit board and sealing resin and the cracks of the sealing resin itself. SOLUTION: An electrode pad 3 is formed on a semiconductor device (IC board) 6. A protruding electrode (bump) 7 is formed on the electrode pad 3. A conductive bonding agent 5 is applied to the tip part of the bump 7 of the IC board 6 as a binding layer using a transfer method or a printing method. Then, the manufactured IC chips are aligned in a face-down state in such a manner that the bumps 7 are opposing to the input-output terminal electrode 8 of a circuit board 9, and the IC chips are mounted on the circuit board 9. The conductive bonding agent 5 is hardened in the above-mentioned state, and the IC board 6 and the circuit board 9 are electrically connected. Then, sealing resin 4 is filled in such a manner that the binding layer (conductive bonding agent 5) is surrounded, and the sealing resin 4 is hardened.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、実装において封止
樹脂との密着力を高めることのできる半導体装置及びそ
の製造方法並びにその半導体装置を用いた半導体ユニッ
トに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of enhancing adhesion with a sealing resin during mounting, a method of manufacturing the same, and a semiconductor unit using the semiconductor device.

【0002】[0002]

【従来の技術】従来、回路基板の入出力端子電極に半導
体装置を実装するに際しては、半田付けを用いたワイヤ
ーボンディング法がよく利用されていた。しかし、近
年、半導体装置のパッケージの小型化と接続端子数の増
加とにより、接続端子の間隔が狭くなり、従来の半田付
け技術で対処することは次第に困難となってきた。
2. Description of the Related Art Heretofore, a wire bonding method using soldering has been often used in mounting a semiconductor device on an input / output terminal electrode of a circuit board. However, in recent years, due to the miniaturization of the package of the semiconductor device and the increase in the number of connection terminals, the space between the connection terminals has become narrower, and it has become increasingly difficult to cope with this with conventional soldering techniques.

【0003】そこで、最近では、集積回路チップ等の半
導体装置を回路基板の入出力端子電極上に直接実装する
ことにより、実装面積を小さくして効率化を図ろうとす
る方法が提案されている。なかでも、半導体装置を回路
基板にフェイスダウン状態でフリップチップ実装する方
法は、半導体装置と回路基板との電気的接続が一括して
行えること、及び接続後の機械的強度が強いことから、
有用な方法であるとされている。
Therefore, recently, a method has been proposed in which a semiconductor device such as an integrated circuit chip is directly mounted on the input / output terminal electrodes of a circuit board to reduce the mounting area and improve efficiency. Among them, the method of flip-chip mounting the semiconductor device on the circuit board in a face-down state is that the electrical connection between the semiconductor device and the circuit board can be performed at once, and the mechanical strength after connection is strong,
It is said to be a useful method.

【0004】例えば、工業調査会、1980年1月15
日発行、日本マイクロエレクトロニクス協会編、「IC
化実装技術」には、半田メッキ法を用いた実装方法が記
載されている。以下、この実装方法について説明する。
For example, Industrial Research Committee, January 15, 1980
Published by Japan Microelectronics Association, "IC
The "mounting technology" describes a mounting method using a solder plating method. Hereinafter, this mounting method will be described.

【0005】図8(a)は従来の半導体装置における半
田バンプを示す断面図、図8(b)は従来の半導体ユニ
ットを示す断面図である。図8に示すように、半導体装
置(以下「IC基板」という。)116の電極パッド1
13を回路基板119の入出力端子電極118に接続す
る場合には、まず、IC基板116の電極パッド113
の上に密着金属膜112及び拡散防止金属膜111を蒸
着法によって順次形成する。次いで、拡散防止金属膜1
11の上に半田からなる電気的接続接点(以下「半田バ
ンプ」という。)110をメッキ法によって形成し(以
上、図8(a))、ICチップを作製する。次いで、こ
のようにして作製したICチップを、フェイスダウン状
態で、半田バンプ110が入出力端子電極118の上に
当接するように位置合わせを行い、ICチップを回路基
板119の上に載置する(図8(b))。次いで、この
半導体装置の実装体(半導体ユニット)を高温に加熱
し、半田バンプ110を回路基板119の入出力端子電
極118に融着する。
FIG. 8A is a sectional view showing a solder bump in a conventional semiconductor device, and FIG. 8B is a sectional view showing a conventional semiconductor unit. As shown in FIG. 8, the electrode pad 1 of the semiconductor device (hereinafter referred to as “IC substrate”) 116.
When connecting 13 to the input / output terminal electrode 118 of the circuit board 119, first, the electrode pad 113 of the IC board 116 is
An adhesion metal film 112 and a diffusion prevention metal film 111 are sequentially formed on the upper surface by an evaporation method. Then, the diffusion prevention metal film 1
An electrical connection contact (hereinafter referred to as "solder bump") 110 made of solder is formed on 11 by a plating method (above, FIG. 8A), and an IC chip is manufactured. Next, the IC chip thus manufactured is positioned face down so that the solder bumps 110 contact the input / output terminal electrodes 118, and the IC chip is mounted on the circuit board 119. (FIG.8 (b)). Next, the mounting body (semiconductor unit) of this semiconductor device is heated to a high temperature to fuse the solder bumps 110 to the input / output terminal electrodes 118 of the circuit board 119.

【0006】また、最近では、導電性接着剤を用いた半
導体装置の実装方法も提案されている。図9は従来の導
電性接着剤を用いた半導体ユニットを示す断面図であ
る。図9に示すように、まず、半導体装置(以下「IC
基板」という。)126の電極パッド123の上にワイ
ヤーボンディング法又はメッキ法によって電気的接続接
点(Auバンプ)120を形成する。次いで、このAu
バンプ120を導電性接着剤(接合層)125を介して
回路基板129の入出力端子電極128に接続する。こ
のような半導体ユニットにおいては、半導体装置126
のAuバンプ120に導電性接着剤125を転写した後
に、回路基板129の入出力端子電極128に導電性接
着剤125が当接するように位置合わせを行い、導電性
接着剤125を硬化させることにより、半導体装置12
6と回路基板129との電気的接続が実現されている。
Recently, a method of mounting a semiconductor device using a conductive adhesive has been proposed. FIG. 9 is a sectional view showing a semiconductor unit using a conventional conductive adhesive. As shown in FIG. 9, first, a semiconductor device (hereinafter referred to as “IC
Substrate. ) 126, the electrical connection contact (Au bump) 120 is formed on the electrode pad 123 of 126 by a wire bonding method or a plating method. Then this Au
The bump 120 is connected to the input / output terminal electrode 128 of the circuit board 129 via the conductive adhesive (bonding layer) 125. In such a semiconductor unit, the semiconductor device 126
After the conductive adhesive 125 is transferred to the Au bumps 120, the alignment is performed so that the conductive adhesive 125 contacts the input / output terminal electrodes 128 of the circuit board 129, and the conductive adhesive 125 is cured. , Semiconductor device 12
6 and the circuit board 129 are electrically connected.

【0007】さらに、接続を補強するために、封止樹脂
によって封止した半導体ユニットも提案されている。こ
の場合には、さらに封止樹脂を封入する工程と、封止樹
脂を硬化させる工程とが必要になる。
Further, a semiconductor unit sealed with a sealing resin has been proposed to reinforce the connection. In this case, a step of further encapsulating the sealing resin and a step of curing the sealing resin are required.

【0008】[0008]

【発明が解決しようとする課題】しかし、上記のような
従来の半導体装置及びその実装体(半導体ユニット)に
は、次のような問題点がある。
However, the above-described conventional semiconductor device and its mounted body (semiconductor unit) have the following problems.

【0009】すなわち、半導体ユニット製作工程中にお
ける温度差あるいは信頼性試験などにおいて、半導体装
置、回路基板、封止樹脂の熱膨張係数に差があるため
に、熱衝撃時の熱膨張による応力や吸湿によって接着力
が低下し、バルク部に亀裂、剥離が発生する。そして、
このようにバルク部に亀裂、剥離が発生すると、接合界
面が不安定となり、電気的接続点(Auバンプ)120
の抵抗値が増大する虞れがある。また、半導体装置と封
止樹脂との境界における剥離や封止樹脂そのものにおけ
る亀裂が発生すると、劣化が早まり、信頼性の寿命が著
しく損なわれるといった問題点がある。
That is, in the temperature difference during the semiconductor unit manufacturing process or the reliability test, there is a difference in the thermal expansion coefficient of the semiconductor device, the circuit board, and the sealing resin. As a result, the adhesive strength is reduced and cracks and peeling occur in the bulk part. And
When a crack or peeling occurs in the bulk portion in this manner, the bonding interface becomes unstable, and the electrical connection point (Au bump) 120
There is a possibility that the resistance value of will increase. In addition, if peeling occurs at the boundary between the semiconductor device and the sealing resin or cracks occur in the sealing resin itself, there is a problem that deterioration is accelerated and the reliability life is significantly impaired.

【0010】本発明は、従来技術における前記課題を解
決するため、半導体装置と封止樹脂との密着力を高め、
劣化を抑えることが可能な半導体装置及びその製造方法
並びにその半導体装置を用いた半導体ユニットを提供す
ることを目的とする。
In order to solve the above problems in the prior art, the present invention enhances the adhesive force between the semiconductor device and the sealing resin,
An object of the present invention is to provide a semiconductor device capable of suppressing deterioration, a manufacturing method thereof, and a semiconductor unit using the semiconductor device.

【0011】[0011]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体装置の構成は、フェイスダウン
状態で回路基板に実装される半導体装置であって、前記
半導体装置の回路を除いた面の少なくとも一部が、凹面
及び凸面から選ばれる少なくとも一つの面を有すること
を特徴とする。
In order to achieve the above object, a semiconductor device according to the present invention has a structure in which a semiconductor device is mounted on a circuit board in a face-down state, and the circuit of the semiconductor device is excluded. At least a part of the surfaces has at least one surface selected from a concave surface and a convex surface.

【0012】また、本発明に係る半導体装置の製造方法
の構成は、フェイスダウン状態で回路基板に実装される
半導体装置の製造方法であって、前記半導体装置の回路
を除いた面の少なくとも一部に、前記半導体装置と同じ
材料又は無機物の砥粒を加熱吹き付けすることを特徴と
する。
A semiconductor device manufacturing method according to the present invention is a method for manufacturing a semiconductor device mounted on a circuit board in a face-down state, wherein at least a part of a surface of the semiconductor device excluding a circuit is In addition, abrasive grains of the same material or inorganic material as the semiconductor device are heated and sprayed.

【0013】また、本発明に係る半導体ユニットの構成
は、端子電極を有する回路基板と、突起電極を有し、フ
ェイスダウン状態で前記回路基板に実装された半導体装
置とを備えた半導体ユニットであって、前記半導体装置
は、回路を除いた面の少なくとも一部に凹面及び凸面か
ら選ばれる少なくとも一つの面を有し、前記半導体装置
の前記突起電極は前記回路基板の前記端子電極に接合層
を介して電気的に接続され、かつ、前記半導体装置と前
記回路基板との間隙と前記半導体装置の側面とが封止樹
脂によって機械的に補強されていることを特徴とする。
The structure of the semiconductor unit according to the present invention is a semiconductor unit including a circuit board having terminal electrodes and a semiconductor device having protruding electrodes and mounted on the circuit board in a face-down state. The semiconductor device has at least one surface selected from a concave surface and a convex surface on at least a part of the surface excluding the circuit, and the protruding electrode of the semiconductor device has a bonding layer on the terminal electrode of the circuit board. And a side surface of the semiconductor device and a side surface of the semiconductor device are mechanically reinforced by a sealing resin.

【0014】また、前記本発明の半導体ユニットの構成
においては、突起電極が、Au、Cu、Al、半田又は
これらの合金からなるのが好ましい。また、前記本発明
の半導体ユニットの構成においては、接合層が、導電性
接着剤からなるのが好ましい。
Further, in the structure of the semiconductor unit of the present invention, it is preferable that the protruding electrode is made of Au, Cu, Al, solder or an alloy thereof. Further, in the configuration of the semiconductor unit of the present invention, it is preferable that the bonding layer is made of a conductive adhesive.

【0015】また、前記本発明の半導体ユニットの構成
においては、接合層が、異方性導電材からなるのが好ま
しい。
In the structure of the semiconductor unit of the present invention, it is preferable that the bonding layer is made of an anisotropic conductive material.

【0016】[0016]

【発明の実施の形態】前記本発明の半導体装置の構成に
よれば、フェイスダウン状態で回路基板に実装される半
導体装置であって、前記半導体装置の回路を除いた面の
少なくとも一部が、凹面及び凸面から選ばれる少なくと
も一つの面を有することを特徴とするため、半導体装置
を回路基板に実装した場合に、半導体装置と封止樹脂と
の接触面積が増加し、半導体装置と封止樹脂との密着強
度が高まる。
According to the configuration of the semiconductor device of the present invention, a semiconductor device mounted on a circuit board in a face-down state, wherein at least a part of a surface of the semiconductor device excluding a circuit is Since the semiconductor device has at least one surface selected from a concave surface and a convex surface, when the semiconductor device is mounted on a circuit board, the contact area between the semiconductor device and the sealing resin increases, and the semiconductor device and the sealing resin increase. The adhesion strength with

【0017】また、前記本発明の半導体装置の製造方法
の構成によれば、フェイスダウン状態で回路基板に実装
される半導体装置の製造方法であって、前記半導体装置
の回路を除いた面の少なくとも一部に、前記半導体装置
と同じ材料又は無機物の砥粒を加熱吹き付けすることを
特徴とするため、半導体装置の回路を除いた面の少なく
とも一部に容易に凹凸面が形成される。
Further, according to the structure of the method for manufacturing a semiconductor device of the present invention, there is provided a method for manufacturing a semiconductor device mounted on a circuit board in a face-down state, wherein at least a surface of the semiconductor device excluding a circuit is included. Since the abrasive grain of the same material or inorganic material as that of the semiconductor device is heated and sprayed on a part of the semiconductor device, an uneven surface is easily formed on at least a part of the surface of the semiconductor device excluding the circuit.

【0018】また、前記本発明の半導体ユニットの構成
によれば、端子電極を有する回路基板と、突起電極を有
し、フェイスダウン状態で前記回路基板に実装された半
導体装置とを備えた半導体ユニットであって、前記半導
体装置は、回路を除いた面の少なくとも一部に凹面及び
凸面から選ばれる少なくとも一つの面を有し、前記半導
体装置の前記突起電極は前記回路基板の前記端子電極に
接合層を介して電気的に接続され、かつ、前記半導体装
置と前記回路基板との間隙と前記半導体装置の側面とが
封止樹脂によって機械的に補強されていることを特徴と
するため、半導体装置を回路基板に実装した場合に、半
導体装置と封止樹脂との接触面積が増加し、半導体装置
と封止樹脂との密着強度が高まる。その結果、半導体装
置、回路基板、封止樹脂の熱膨脹係数の差によって発生
する応力による半導体装置と封止樹脂との剥離や封止樹
脂そのものの亀裂が防止される。
Further, according to the structure of the semiconductor unit of the present invention, the semiconductor unit is provided with the circuit board having the terminal electrodes, and the semiconductor device having the protruding electrodes and mounted on the circuit board in a face-down state. The semiconductor device has at least one surface selected from a concave surface and a convex surface on at least a part of the surface excluding the circuit, and the protruding electrode of the semiconductor device is bonded to the terminal electrode of the circuit board. The semiconductor device is electrically connected via a layer, and the gap between the semiconductor device and the circuit board and the side surface of the semiconductor device are mechanically reinforced by a sealing resin. When is mounted on a circuit board, the contact area between the semiconductor device and the sealing resin increases, and the adhesion strength between the semiconductor device and the sealing resin increases. As a result, the peeling between the semiconductor device and the sealing resin and the cracking of the sealing resin itself due to the stress generated by the difference in the thermal expansion coefficients of the semiconductor device, the circuit board, and the sealing resin are prevented.

【0019】また、前記本発明の半導体ユニットの構成
において、接合層が、導電性接着剤又は異方性導電材か
らなるという好ましい例によれば、信頼性の寿命が延び
る。なぜなら、温度の変化によって半導体ユニットや基
板が伸びたり縮んだりするが、導電性接着剤又は異方性
導電材はフレキシブルな性質を有しているために熱応力
を緩和することができるからである。
Further, in the above-mentioned structure of the semiconductor unit of the present invention, according to a preferable example in which the bonding layer is made of a conductive adhesive or an anisotropic conductive material, the life of reliability is extended. This is because the semiconductor unit or the substrate expands or contracts due to the change in temperature, but the conductive adhesive or the anisotropic conductive material has a flexible property, so that the thermal stress can be relaxed. .

【0020】[0020]

【実施例】以下、実施例を用いて本発明をさらに具体的
に説明する。 <第1の実施例>図1は本発明に係る半導体装置の第1
の実施例における突起電極を示す断面図である。図1
は、半導体装置の一部分における複数の電気的接続点の
うちの1つを示している。図1に示すように、半導体装
置(以下「IC基板」という。)6の上には電極パッド
3が形成されている。また、電極パッド3の上には突起
電極(以下「バンプ」という。)7が形成されている。
バンプ7は、第1のバンプ7′と、第1のバンプ7′の
上に形成され、かつ、第1のバンプ7′よりも小さい第
2のバンプ7″とからなる2段構造を有している(以下
単に「バンプ7」という。)。また、IC基板6には、
その端面1、及び電極パッド3側の端面から電極パッド
3までの部分2に凹凸面が形成されている(図2参
照)。すなわち、IC基板6の回路を除いた面に凹凸面
が形成されている。
EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples. <First Embodiment> FIG. 1 shows a first semiconductor device according to the present invention.
6 is a cross-sectional view showing a protruding electrode in the example of FIG. FIG.
Shows one of a plurality of electrical connection points in a part of the semiconductor device. As shown in FIG. 1, an electrode pad 3 is formed on a semiconductor device (hereinafter referred to as “IC substrate”) 6. A bump electrode (hereinafter referred to as “bump”) 7 is formed on the electrode pad 3.
The bump 7 has a two-step structure including a first bump 7 ′ and a second bump 7 ″ which is formed on the first bump 7 ′ and is smaller than the first bump 7 ′. (Hereinafter simply referred to as “bump 7”). Further, the IC substrate 6 has
An uneven surface is formed on the end surface 1 and a portion 2 from the end surface on the electrode pad 3 side to the electrode pad 3 (see FIG. 2). That is, an uneven surface is formed on the surface of the IC substrate 6 excluding the circuits.

【0021】凹凸面は、例えば以下のようにして形成さ
れる。すなわち、図7に示すように、IC基板6の端面
1に、IC基板6と同じ材料又は無機物の砥粒10、例
えばSiO2 を300℃以上の温度で吹き付けて化合さ
せることにより、凹凸面が容易に形成される。
The uneven surface is formed as follows, for example. That is, as shown in FIG. 7, by polishing the end surface 1 of the IC substrate 6 with abrasive grains 10 of the same material as that of the IC substrate 6 or an inorganic material, for example, SiO 2 at a temperature of 300 ° C. or higher and combining them, the uneven surface is Easily formed.

【0022】図2は本発明に係る半導体ユニットの第1
の実施例を示す断面図である。ここで、半導体装置とし
ては上記したもの(図1)が用いられている。この半導
体ユニットの作製方法は以下のとおりである。まず、I
C基板6のバンプ7の先端部に、接合層としての導電性
接着剤5を転写法や印刷法によって塗布する。上記のよ
うな2段構造のバンプ7を用いれば、必要量以上の導電
性接着剤5が、バンプ7の先端部に付着するのを防止す
ることができるので、適量の導電性接着剤5を塗布する
ことができる。次いで、上記のようにして作製されたI
Cチップを、フェイスダウン状態で、バンプ7が回路基
板9の入出力端子電極8に対向するように位置合わせを
行い、ICチップを回路基板9の上に載置する。この状
態で導電性接着剤5を硬化させれば、IC基板6と回路
基板9との電気的接続が実現される。次いで、接合層
(導電性接着剤5)を囲むようにして封止樹脂4を封入
し、封止樹脂4を硬化させる。これにより、IC基板6
と回路基板9との間隙とIC基板6の側面1とが封止樹
脂4によって機械的に補強された半導体ユニットが得ら
れる。
FIG. 2 shows a first semiconductor unit according to the present invention.
It is sectional drawing which shows Example of (a). Here, the semiconductor device described above (FIG. 1) is used as the semiconductor device. The method of manufacturing this semiconductor unit is as follows. First, I
The conductive adhesive 5 as a bonding layer is applied to the tip of the bump 7 of the C substrate 6 by a transfer method or a printing method. If the bumps 7 having the two-stage structure as described above are used, it is possible to prevent more than the necessary amount of the conductive adhesive 5 from adhering to the tip portions of the bumps 7. It can be applied. Then, I prepared as described above
The C chip is positioned face down so that the bumps 7 face the input / output terminal electrodes 8 of the circuit board 9 and the IC chip is placed on the circuit board 9. When the conductive adhesive 5 is cured in this state, the IC substrate 6 and the circuit substrate 9 are electrically connected. Next, the sealing resin 4 is enclosed so as to surround the bonding layer (conductive adhesive 5) and the sealing resin 4 is cured. As a result, the IC substrate 6
A semiconductor unit is obtained in which the gap between the circuit board 9 and the side surface 1 of the IC board 6 is mechanically reinforced by the sealing resin 4.

【0023】この場合、上記したようにIC基板6の回
路を除いた面に凹凸面が形成されていることから、IC
基板6と封止樹脂4との接触面積が増加し、IC基板6
と封止樹脂4との密着強度が高まる。その結果、IC基
板6、回路基板9、封止樹脂4の熱膨脹係数の差によっ
て発生する応力によるIC基板6と封止樹脂4との剥離
や封止樹脂4そのものの亀裂が防止される。また、導電
性接着剤5を介して接合されているため、信頼性の寿命
が延びる。なぜなら、温度の変化によって半導体ユニッ
トや基板が伸びたり縮んだりするが、導電性接着剤5は
フレキシブルな性質を有しているために熱応力を緩和す
ることができるからである。
In this case, since the uneven surface is formed on the surface of the IC substrate 6 excluding the circuit as described above, the IC
The contact area between the substrate 6 and the sealing resin 4 increases, and the IC substrate 6
The adhesion strength between the resin and the sealing resin 4 is increased. As a result, peeling between the IC substrate 6 and the sealing resin 4 and cracks in the sealing resin 4 themselves due to stress generated by the difference in thermal expansion coefficient between the IC substrate 6, the circuit board 9 and the sealing resin 4 are prevented. In addition, since they are bonded via the conductive adhesive 5, the reliability life is extended. This is because the semiconductor adhesive and the substrate may expand or contract due to changes in temperature, but the conductive adhesive 5 has a flexible property, so that thermal stress can be relaxed.

【0024】尚、本実施例においては、バンプ7を2段
構造の突起形状に成形しているが、必ずしもこの形状に
限定されるものではない。また、本実施例においては、
IC基板6の回路を除いた面に凹凸面を形成している
が、必ずしもこの構成に限定されるものではない。IC
基板6の回路を除いた面が、凹面及び凸面から選ばれる
少なくとも一つの面を有していれば、IC基板6と封止
樹脂4との接触面積が増加するため、IC基板6と封止
樹脂4との密着強度を高めることができる。このこと
は、以下の第2〜第5の実施例についても同様である。
In the present embodiment, the bump 7 is formed in the shape of a protrusion having a two-step structure, but the shape is not necessarily limited to this shape. In addition, in this embodiment,
Although the uneven surface is formed on the surface of the IC substrate 6 excluding the circuit, it is not necessarily limited to this structure. IC
If the surface of the substrate 6 excluding the circuit has at least one surface selected from a concave surface and a convex surface, the contact area between the IC substrate 6 and the sealing resin 4 increases, so that the IC substrate 6 and the sealing resin 4 are sealed. The adhesion strength with the resin 4 can be increased. This also applies to the following second to fifth embodiments.

【0025】また、本実施例においては、IC基板6の
回路を除いた全面に凹凸面を形成しているが、必ずしも
この構成に限定されるものではなく、IC基板6の回路
を除いた面の少なくとも一部に凹凸面を形成すれば足り
る。
In this embodiment, the uneven surface is formed on the entire surface of the IC substrate 6 excluding the circuit, but the present invention is not limited to this structure, and the surface of the IC substrate 6 excluding the circuit is not limited thereto. It is sufficient to form the uneven surface on at least a part of.

【0026】また、突起電極(バンプ)7は、Au、C
u、Al、半田又はこれらの合金から形成されているの
が好ましい。 <第2の実施例>図3(a)は本発明に係る半導体装置
の第2の実施例における電気的接続接点を示す断面図で
ある。図3(a)は、半導体装置の一部分における複数
の電気的接続点のうちの1つを示している。図3(a)
に示すように、半導体装置(以下「IC基板」とい
う。)36の上には電極パッド33が形成されている。
また、IC基板36の上には、電極パッド33の周縁部
を覆うようにして密着金属膜37が形成されている。ま
た、電極パッド33及び密着金属膜37の上には、拡散
防止金属膜40が蒸着法によって形成されている。ま
た、拡散防止金属膜40の上には半田からなる電気的接
続接点(以下「半田バンプ」)30がメッキ法によって
形成されている。また、IC基板36には、その端面3
1、及び電極パッド33側の端面から電極パッド33ま
での部分32に凹凸面が形成されている(図3(b)参
照)。
The protruding electrodes (bumps) 7 are made of Au, C
It is preferably made of u, Al, solder or an alloy thereof. <Second Embodiment> FIG. 3A is a sectional view showing an electrical connection contact in a second embodiment of the semiconductor device according to the present invention. FIG. 3A shows one of a plurality of electrical connection points in a part of the semiconductor device. FIG. 3 (a)
As shown in FIG. 3, the electrode pad 33 is formed on the semiconductor device (hereinafter referred to as “IC substrate”) 36.
Further, an adhesion metal film 37 is formed on the IC substrate 36 so as to cover the peripheral portion of the electrode pad 33. A diffusion prevention metal film 40 is formed on the electrode pad 33 and the adhesion metal film 37 by a vapor deposition method. Further, on the diffusion preventing metal film 40, an electrical connection contact (hereinafter referred to as “solder bump”) 30 made of solder is formed by a plating method. Further, the IC substrate 36 has an end surface 3
1 and the uneven surface is formed in the portion 32 from the end surface on the electrode pad 33 side to the electrode pad 33 (see FIG. 3B).

【0027】図3(b)は本発明に係る半導体ユニット
の第2の実施例を示す断面図である。ここで、半導体装
置としては上記したもの(図3(a))が用いられてい
る。半導体ユニットの作製方法は以下のとおりである。
まず、IC基板36の半田バンプ30の先端部に、接合
層としての導電性接着剤35を転写法や印刷法によって
塗布する。次いで、このようにして作製されたICチッ
プを、フェイスダウン状態で、半田バンプ30が回路基
板39の入出力端子電極38に対向するように位置合わ
せを行い、ICチップを回路基板39の上に載置する。
この状態で導電性接着剤35を硬化させれば、IC基板
36と回路基板39との電気的接続が実現される。次い
で、接合層(導電性接着剤35)を囲むようにして封止
樹脂34を封入し、封止樹脂34を硬化させる。これに
より、IC基板36と回路基板39との間隙とIC基板
36の側面1とが封止樹脂34によって機械的に補強さ
れた半導体ユニットが得られる。
FIG. 3B is a sectional view showing a second embodiment of the semiconductor unit according to the present invention. Here, the semiconductor device described above (FIG. 3A) is used as the semiconductor device. The method of manufacturing the semiconductor unit is as follows.
First, the conductive adhesive 35 as a bonding layer is applied to the tip of the solder bump 30 of the IC substrate 36 by a transfer method or a printing method. Next, the IC chip thus manufactured is positioned face down so that the solder bumps 30 face the input / output terminal electrodes 38 of the circuit board 39, and the IC chip is placed on the circuit board 39. Place it.
When the conductive adhesive 35 is cured in this state, the IC substrate 36 and the circuit substrate 39 are electrically connected. Next, the sealing resin 34 is encapsulated so as to surround the bonding layer (conductive adhesive 35), and the sealing resin 34 is cured. As a result, a semiconductor unit in which the gap between the IC board 36 and the circuit board 39 and the side surface 1 of the IC board 36 are mechanically reinforced by the sealing resin 34 is obtained.

【0028】<第3の実施例>図4(a)は本発明に係
る半導体装置の第3の実施例における突起電極を示す断
面図である。図4(a)は、半導体装置の一部分におけ
る複数の電気的接続点のうちの1つを示している。図4
(a)に示すように、半導体装置(以下「IC基板」と
いう。)46の上には電極パッド43が形成されてい
る。また、電極パッド43の上には突起電極(以下「バ
ンプ」という。)47が形成されている。また、IC基
板46には、その端面41、及び電極パッド43側の端
面から電極パッド43までの部分42に凹凸面が形成さ
れている(図4(b)参照)。
<Third Embodiment> FIG. 4A is a sectional view showing a protruding electrode in a third embodiment of the semiconductor device according to the present invention. FIG. 4A shows one of a plurality of electrical connection points in a part of the semiconductor device. FIG.
As shown in (a), an electrode pad 43 is formed on a semiconductor device (hereinafter referred to as “IC substrate”) 46. A protruding electrode (hereinafter referred to as “bump”) 47 is formed on the electrode pad 43. Further, the IC substrate 46 has an uneven surface formed on the end surface 41 and a portion 42 from the end surface on the electrode pad 43 side to the electrode pad 43 (see FIG. 4B).

【0029】図4(b)は本発明に係る半導体ユニット
の第3の実施例を示す断面図である。ここで、半導体装
置としては上記したもの(図4(a))が用いられてい
る。半導体ユニットの作製方法は以下のとおりである。
まず、IC基板46のバンプ47の先端部に、接合層と
しての導電性接着剤45を転写法や印刷法によって塗布
する。次いで、このようにして作製されたICチップ
を、フェイスダウン状態で、バンプ47が回路基板49
の入出力端子電極48に対向するように位置合わせを行
い、ICチップを回路基板49の上に載置する。この状
態で導電性接着剤45を硬化させれば、IC基板46と
回路基板49との電気的接続が実現される。次いで、接
合層(導電性接着剤45)を囲むようにして封止樹脂4
4を封入し、封止樹脂44を硬化させる。これにより、
IC基板46と回路基板49との間隙とIC基板46の
側面1とが封止樹脂44によって機械的に補強された半
導体ユニットが得られる。
FIG. 4B is a sectional view showing a third embodiment of the semiconductor unit according to the present invention. Here, as the semiconductor device, the one described above (FIG. 4A) is used. The method of manufacturing the semiconductor unit is as follows.
First, the conductive adhesive 45 as a bonding layer is applied to the tip of the bump 47 of the IC substrate 46 by a transfer method or a printing method. Next, the IC chip thus manufactured is placed face down in the bump 47 on the circuit board 49.
The IC chip is placed on the circuit board 49 by performing alignment so as to face the input / output terminal electrode 48 of. When the conductive adhesive 45 is cured in this state, the electric connection between the IC board 46 and the circuit board 49 is realized. Next, the sealing resin 4 is formed so as to surround the bonding layer (conductive adhesive 45).
4 is encapsulated and the sealing resin 44 is cured. This allows
A semiconductor unit is obtained in which the gap between the IC board 46 and the circuit board 49 and the side surface 1 of the IC board 46 are mechanically reinforced by the sealing resin 44.

【0030】<第4の実施例>図5は本発明に係る半導
体ユニットの第4の実施例を示す断面図である。図5に
示すように、半導体装置(以下「IC基板」という。)
56の上には電極パッド53が形成されている。また、
電極パッド53の上には突起電極(以下「バンプ」とい
う。)57が形成されている。また、IC基板56に
は、その端面51、及び電極パッド53側の端面から電
極パッド53までの部分52に凹凸面が形成されてい
る。
<Fourth Embodiment> FIG. 5 is a sectional view showing a fourth embodiment of the semiconductor unit according to the present invention. As shown in FIG. 5, a semiconductor device (hereinafter referred to as “IC substrate”).
An electrode pad 53 is formed on 56. Also,
A protruding electrode (hereinafter referred to as “bump”) 57 is formed on the electrode pad 53. Further, the IC substrate 56 has an uneven surface formed on the end surface 51 and a portion 52 from the end surface on the electrode pad 53 side to the electrode pad 53.

【0031】半導体ユニットの作製方法は以下のとおり
である。まず、上記のようにして作製されたICチップ
を、フェイスダウン状態で、バンプ57が回路基板59
の入出力端子電極58に対向するように位置合わせを行
い、接合層としての異方性導電材55を介してICチッ
プを回路基板49の上に載置する。この状態で異方性接
着剤55を硬化させれば、IC基板56と回路基板59
との電気的接続が実現される。次いで、接合層(異方性
導電材55)を囲むようにして封止樹脂54を封入し、
封止樹脂54を硬化させる。これにより、IC基板56
と回路基板59との間隙とIC基板56の側面51とが
封止樹脂54によって機械的に補強された半導体ユニッ
トが得られる。
The method of manufacturing the semiconductor unit is as follows. First, in the IC chip manufactured as described above, the bumps 57 are placed on the circuit board 59 in a face-down state.
The IC chip is placed on the circuit board 49 via the anisotropic conductive material 55 as a bonding layer, so that the IC chip faces the input / output terminal electrode 58. If the anisotropic adhesive 55 is cured in this state, the IC substrate 56 and the circuit substrate 59
An electrical connection with is realized. Then, the sealing resin 54 is enclosed so as to surround the bonding layer (anisotropic conductive material 55),
The sealing resin 54 is cured. As a result, the IC substrate 56
A semiconductor unit in which the gap between the circuit board 59 and the side surface 51 of the IC board 56 is mechanically reinforced by the sealing resin 54 is obtained.

【0032】本実施例においては、異方性導電材55を
介して接合されているため、信頼性の寿命が延びる。な
ぜなら、温度の変化によって半導体ユニットや基板が伸
びたり縮んだりするが、異方性導電材55はフレキシブ
ルな性質を有しているために熱応力を緩和することがで
きるからである。
In the present embodiment, since they are bonded via the anisotropic conductive material 55, the reliability life is extended. This is because the semiconductor unit or the substrate expands or contracts due to the change in temperature, but the anisotropic conductive material 55 has a flexible property, so that the thermal stress can be relaxed.

【0033】<第5の実施例>図6は本発明に係る半導
体ユニットの第5の実施例を示す断面図である。図6に
示すように、半導体装置(以下「IC基板」という。)
66の上には電極パッド63が形成されている。また、
電極パッド63の上には突起電極(以下「バンプ」とい
う。)67が形成されている。また、IC基板66に
は、その端面61、及び電極パッド63側の端面から電
極パッド63までの部分62に凹凸面が形成されてい
る。
<Fifth Embodiment> FIG. 6 is a sectional view showing a fifth embodiment of a semiconductor unit according to the present invention. As shown in FIG. 6, a semiconductor device (hereinafter referred to as “IC substrate”).
Electrode pads 63 are formed on 66. Also,
A protruding electrode (hereinafter referred to as “bump”) 67 is formed on the electrode pad 63. Further, the IC substrate 66 has an uneven surface formed on the end surface 61 and a portion 62 from the end surface on the electrode pad 63 side to the electrode pad 63.

【0034】半導体ユニットの作製方法は以下のとおり
である。まず、上記のようにして作製されたICチップ
を、フェイスダウン状態で、バンプ67が回路基板69
の入出力端子電極68に対向するように位置合わせを行
い、接合層としての異方性導電材65を介してICチッ
プを回路基板69の上に載置する。この状態で異方性導
電材65を硬化させれば、IC基板66と回路基板69
との電気的接続が実現される。ここで、ICチップを回
路基板69の上に載置する前において、異方性導電材6
5は、IC基板66と回路基板69との間隙以上の厚み
を有している。このため、異方性導電材65がIC基板
66と回路基板69と間に充填された状態となるので、
上記第4の実施例と比較して安定した接続状態が実現さ
れる。次いで、接合層(異方性導電材65)を囲むよう
にして封止樹脂64を封入し、封止樹脂64を硬化させ
る。これにより、IC基板66と回路基板69との間隙
とIC基板66の側面61とが封止樹脂64によって機
械的に補強された半導体ユニットが得られる。
The method of manufacturing the semiconductor unit is as follows. First, in the IC chip manufactured as described above, the bump 67 is placed on the circuit board 69 in a face-down state.
The IC chip is placed on the circuit board 69 through the anisotropic conductive material 65 as a bonding layer, so that the IC chip faces the input / output terminal electrode 68. If the anisotropic conductive material 65 is cured in this state, the IC board 66 and the circuit board 69 are formed.
An electrical connection with is realized. Here, before the IC chip is placed on the circuit board 69, the anisotropic conductive material 6
5 has a thickness equal to or larger than the gap between the IC substrate 66 and the circuit substrate 69. Therefore, the anisotropic conductive material 65 is filled between the IC board 66 and the circuit board 69.
A stable connection state is realized as compared with the fourth embodiment. Next, the sealing resin 64 is enclosed so as to surround the bonding layer (anisotropic conductive material 65) and the sealing resin 64 is cured. As a result, a semiconductor unit is obtained in which the gap between the IC substrate 66 and the circuit substrate 69 and the side surface 61 of the IC substrate 66 are mechanically reinforced by the sealing resin 64.

【0035】[0035]

【発明の効果】以上説明したように、本発明によれば、
半導体装置をフェースダウン状態で回路基板に実装した
場合に、半導体装置と封止樹脂との接触面積が増加し、
半導体装置と封止樹脂との密着強度が高まる。その結
果、半導体装置、回路基板、封止樹脂の熱膨脹係数の差
によって発生する応力による半導体装置と封止樹脂との
剥離や封止樹脂そのものの亀裂が防止される。
As described above, according to the present invention,
When the semiconductor device is mounted face down on the circuit board, the contact area between the semiconductor device and the sealing resin increases,
The adhesion strength between the semiconductor device and the sealing resin is increased. As a result, the peeling between the semiconductor device and the sealing resin and the cracking of the sealing resin itself due to the stress generated by the difference in the thermal expansion coefficients of the semiconductor device, the circuit board, and the sealing resin are prevented.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る半導体装置の第1の実施例におけ
る突起電極を示す断面図である。
FIG. 1 is a sectional view showing a protruding electrode in a first embodiment of a semiconductor device according to the present invention.

【図2】本発明に係る半導体ユニットの第1の実施例を
示す断面図である。
FIG. 2 is a sectional view showing a first embodiment of the semiconductor unit according to the present invention.

【図3】(a)は本発明に係る半導体装置の第2の実施
例における電気的接続接点を示す断面図、(b)は本発
明に係る半導体ユニットの第2の実施例を示す断面図で
ある。
3A is a sectional view showing an electrical connection contact in a second embodiment of a semiconductor device according to the present invention, and FIG. 3B is a sectional view showing a second embodiment of a semiconductor unit according to the present invention. Is.

【図4】(a)は本発明に係る半導体装置の第3の実施
例における突起電極を示す断面図、(b)は本発明に係
る半導体ユニットの第3の実施例を示す断面図である。
4A is a sectional view showing a protruding electrode in a third embodiment of a semiconductor device according to the present invention, and FIG. 4B is a sectional view showing a third embodiment of a semiconductor unit according to the present invention. .

【図5】本発明に係る半導体ユニットの第4の実施例を
示す断面図である。
FIG. 5 is a sectional view showing a fourth embodiment of the semiconductor unit according to the present invention.

【図6】本発明に係る半導体ユニットの第5の実施例を
示す断面図である。
FIG. 6 is a sectional view showing a fifth embodiment of the semiconductor unit according to the present invention.

【図7】本発明に係る半導体装置の製造方法の一例を示
す概略図である。
FIG. 7 is a schematic view showing an example of a method for manufacturing a semiconductor device according to the present invention.

【図8】(a)は従来の半導体装置における半田バンプ
を示す断面図、(b)は従来の半導体ユニットを示す断
面図である。
FIG. 8A is a sectional view showing a solder bump in a conventional semiconductor device, and FIG. 8B is a sectional view showing a conventional semiconductor unit.

【図9】従来の導電性接着剤を用いた半導体ユニットを
示す断面図である
FIG. 9 is a cross-sectional view showing a semiconductor unit using a conventional conductive adhesive.

【符号の説明】[Explanation of symbols]

1、31、41、51、61…半導体装置(IC基板)
の端面 2、32、42、52、62…電極パッド側の端面から
電極パッドまでの部分 3、33、43、53、63…電極パッド 4、34、44、54、64…封止樹脂 5、35、45…導電性接着剤 6、36、46、56、66…半導体装置(IC基板) 7、67…突起電極(バンプ) 7′…第1の突起電極(バンプ) 7″…第2の突起電極(バンプ) 8、38、48、58、68…入出力端子電極 9、39、49、59、69…回路基板 10…砥粒 30…電気的接続接点(半田バンプ) 37…密着金属膜 40…拡散防止金属膜 47…突起電極(バンプ) 55…異方性導電材 57…突起電極(バンプ) 65…異方性導電材
1, 31, 41, 51, 61 ... Semiconductor device (IC substrate)
End face 2, 32, 42, 52, 62 ... Portion from the end face on the electrode pad side to the electrode pad 3, 33, 43, 53, 63 ... Electrode pad 4, 34, 44, 54, 64 ... Sealing resin 5, 35, 45 ... Conductive adhesive 6, 36, 46, 56, 66 ... Semiconductor device (IC substrate) 7, 67 ... Projection electrode (bump) 7 '... First projection electrode (bump) 7 "... Second Projection electrodes (bumps) 8, 38, 48, 58, 68 ... Input / output terminal electrodes 9, 39, 49, 59, 69 ... Circuit board 10 ... Abrasive grains 30 ... Electrical connection contacts (solder bumps) 37 ... Adhesive metal film 40 ... Diffusion prevention metal film 47 ... Projection electrode (bump) 55 ... Anisotropic conductive material 57 ... Projection electrode (bump) 65 ... Anisotropic conductive material

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 フェイスダウン状態で回路基板に実装さ
れる半導体装置であって、前記半導体装置の回路を除い
た面の少なくとも一部が、凹面及び凸面から選ばれる少
なくとも一つの面を有することを特徴とする半導体装
置。
1. A semiconductor device mounted on a circuit board in a face-down state, wherein at least a part of the surface of the semiconductor device excluding the circuit has at least one surface selected from a concave surface and a convex surface. Characteristic semiconductor device.
【請求項2】 フェイスダウン状態で回路基板に実装さ
れる半導体装置の製造方法であって、前記半導体装置の
回路を除いた面の少なくとも一部に、前記半導体装置と
同じ材料又は無機物の砥粒を加熱吹き付けすることを特
徴とする半導体装置の製造方法。
2. A method of manufacturing a semiconductor device mounted on a circuit board in a face-down state, wherein at least a part of a surface of the semiconductor device excluding a circuit is made of the same material as the semiconductor device or an inorganic abrasive grain. A method for manufacturing a semiconductor device, comprising:
【請求項3】 端子電極を有する回路基板と、突起電極
を有し、フェイスダウン状態で前記回路基板に実装され
た半導体装置とを備えた半導体ユニットであって、前記
半導体装置は、回路を除いた面の少なくとも一部に凹面
及び凸面から選ばれる少なくとも一つの面を有し、前記
半導体装置の前記突起電極は前記回路基板の前記端子電
極に接合層を介して電気的に接続され、かつ、前記半導
体装置と前記回路基板との間隙と前記半導体装置の側面
とが封止樹脂4によって機械的に補強されていることを
特徴とする半導体ユニット。
3. A semiconductor unit comprising a circuit board having a terminal electrode and a semiconductor device having a protruding electrode and mounted on the circuit board in a face-down state, wherein the semiconductor device does not include a circuit. Has at least one surface selected from a concave surface and a convex surface in at least a portion of the surface, the protruding electrode of the semiconductor device is electrically connected to the terminal electrode of the circuit board via a bonding layer, and A semiconductor unit, wherein a gap between the semiconductor device and the circuit board and a side surface of the semiconductor device are mechanically reinforced by a sealing resin 4.
【請求項4】 突起電極が、Au、Cu、Al、半田又
はこれらの合金からなる請求項3に記載の半導体ユニッ
ト。
4. The semiconductor unit according to claim 3, wherein the protruding electrode is made of Au, Cu, Al, solder or an alloy thereof.
【請求項5】 接合層が、導電性接着剤からなる請求項
3に記載の半導体ユニット。
5. The semiconductor unit according to claim 3, wherein the bonding layer is made of a conductive adhesive.
【請求項6】 接合層が、異方性導電材からなる請求項
3に記載の半導体ユニット。
6. The semiconductor unit according to claim 3, wherein the bonding layer is made of an anisotropic conductive material.
JP7180268A 1995-07-17 1995-07-17 Semiconductor device, its manufacture and semiconductor unit using the semiconductor device Pending JPH0936119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7180268A JPH0936119A (en) 1995-07-17 1995-07-17 Semiconductor device, its manufacture and semiconductor unit using the semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7180268A JPH0936119A (en) 1995-07-17 1995-07-17 Semiconductor device, its manufacture and semiconductor unit using the semiconductor device

Publications (1)

Publication Number Publication Date
JPH0936119A true JPH0936119A (en) 1997-02-07

Family

ID=16080270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7180268A Pending JPH0936119A (en) 1995-07-17 1995-07-17 Semiconductor device, its manufacture and semiconductor unit using the semiconductor device

Country Status (1)

Country Link
JP (1) JPH0936119A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09260431A (en) * 1996-03-22 1997-10-03 Nec Corp Connection structure of flip chip mounting
US6268739B1 (en) 1998-03-30 2001-07-31 International Business Machines Corporation Method and device for semiconductor testing using electrically conductive adhesives
JP2002168715A (en) * 2000-12-04 2002-06-14 Toyoda Mach Works Ltd Semiconductor pressure detector and assembling method thereof
KR100808613B1 (en) * 2006-02-06 2008-02-28 후지쯔 가부시끼가이샤 Semiconductor device and manufacturing method for the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09260431A (en) * 1996-03-22 1997-10-03 Nec Corp Connection structure of flip chip mounting
US6268739B1 (en) 1998-03-30 2001-07-31 International Business Machines Corporation Method and device for semiconductor testing using electrically conductive adhesives
US6288559B1 (en) 1998-03-30 2001-09-11 International Business Machines Corporation Semiconductor testing using electrically conductive adhesives
US6559666B2 (en) 1998-03-30 2003-05-06 International Business Machines Corporation Method and device for semiconductor testing using electrically conductive adhesives
JP2002168715A (en) * 2000-12-04 2002-06-14 Toyoda Mach Works Ltd Semiconductor pressure detector and assembling method thereof
KR100808613B1 (en) * 2006-02-06 2008-02-28 후지쯔 가부시끼가이샤 Semiconductor device and manufacturing method for the same

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