JPH09260431A - Connection structure of flip chip mounting - Google Patents
Connection structure of flip chip mountingInfo
- Publication number
- JPH09260431A JPH09260431A JP6587296A JP6587296A JPH09260431A JP H09260431 A JPH09260431 A JP H09260431A JP 6587296 A JP6587296 A JP 6587296A JP 6587296 A JP6587296 A JP 6587296A JP H09260431 A JPH09260431 A JP H09260431A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor chip
- substrate
- board
- epoxy resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明はフリップチップ実装
の接続構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip mounted connection structure.
【0002】[0002]
【従来の技術】従来、例えば特開昭53−21771号
公報に示されているように、フリップチップを基板に実
装した構造において、チップ・基板間にエポキシ系樹
脂,シリコン系樹脂,光硬化性等の樹脂材を充填するこ
とにより、チップ・基板間の熱膨張差による耐熱疲労性
を改善できることが知られている。チップ・基板間の狭
いギャップに樹脂を充填するためには、樹脂の粘度を十
分下げる必要があり、その結果、他の材質特性、例えば
熱膨張係数,弾性率に制約が生じてしまう。また、チッ
プに形成されるパンプの高さのバラツキの影響を受け
て、チップ・基板間の樹脂厚がバラツイたり、チップ周
辺においても樹脂厚のバラツキが生じてしまい、延いて
は樹脂と基板の熱膨張差により樹脂が割れたり、基板か
ら剥離していまうという問題があった。この問題を解決
する技術としては、例えば、図2(a)〜(e)に示す
方法がある。2. Description of the Related Art Conventionally, as shown in, for example, Japanese Patent Laid-Open No. 53-21771, in a structure in which a flip chip is mounted on a substrate, an epoxy resin, a silicon resin, a photo-curable resin is provided between the chip and the substrate. It is known that the thermal fatigue resistance due to the difference in thermal expansion between the chip and the substrate can be improved by filling with a resin material such as. In order to fill the narrow gap between the chip and the substrate with the resin, it is necessary to sufficiently reduce the viscosity of the resin, and as a result, other material characteristics such as thermal expansion coefficient and elastic modulus are restricted. In addition, the resin thickness between the chip and the substrate may vary due to the influence of the height variation of the bumps formed on the chip, and the resin thickness also varies around the chip. There was a problem that the resin was broken or peeled off from the substrate due to the difference in thermal expansion. As a technique for solving this problem, for example, there is a method shown in FIGS.
【0003】図2(a)〜(e)に示す従来のフリップ
チップ接続方法は、フリップチップ25と、フリップチ
ップ25が搭載される基板21との間に固体で且つ板状
の熱硬化樹脂24を介するとともに、フリップチップ2
5のバンプ26と基板21のランド(バッド)上の迎え
半田23とが対向するように設置する工程と、半田の融
点以上の温度で、短時間の熱処理を行い熱硬化樹脂24
が固い状態で半田をリフローする工程と、熱硬化樹脂2
4の硬化可能温度以上で且つ半田の融点より低い温度に
て熱処理を行い、熱硬化樹脂24を軟化した後、引続き
硬化させる工程と、を含んで構成される。(例えば、特
開平2−96343公報参照) 図3は第2の従来例を示す断面図である。図3に示す半
導体チップの実装方法は、半導体チップ33の接続電極
35にバンプ36を形成し、バンプ36上に硬化状態で
弾性を有する導電樹脂層39を設けて硬化させ、半導体
チップ33の接続電極35の面と基板31の電極パター
ン32側の面を対向させ、その対向する二面間に接着樹
脂37を充満させることによって半導体チップ33を基
板31上に接合する。(例えば、特開平2−10394
4号公報参照)In the conventional flip chip connection method shown in FIGS. 2A to 2E, a solid and plate-shaped thermosetting resin 24 is provided between the flip chip 25 and the substrate 21 on which the flip chip 25 is mounted. And flip chip 2
5, the bump 26 of No. 5 and the solder 23 on the land (bad) of the substrate 21 face each other, and a heat treatment for a short time is performed at a temperature equal to or higher than the melting point of the solder.
Process of reflowing solder in a rigid state, and thermosetting resin 2
4, the heat treatment is carried out at a temperature not lower than the curable temperature and lower than the melting point of the solder to soften the thermosetting resin 24, and subsequently to cure the thermosetting resin 24. (For example, see Japanese Patent Laid-Open No. 2-96343) FIG. 3 is a sectional view showing a second conventional example. In the semiconductor chip mounting method shown in FIG. 3, bumps 36 are formed on the connection electrodes 35 of the semiconductor chip 33, a conductive resin layer 39 having elasticity in a cured state is provided on the bumps 36, and the bumps 36 are cured. The semiconductor chip 33 is bonded onto the substrate 31 by making the surface of the electrode 35 and the surface of the substrate 31 on the electrode pattern 32 side face each other and filling the adhesive resin 37 between the two opposing faces. (For example, JP-A-2-10394
No. 4)
【発明が解決しようとする課題】上述した従来のフリッ
プチップ実装の接続構造は、基板と半導体チップとの熱
膨張係数差により、接続部に応力が加わるとクラックが
生じるという欠点があった。The conventional flip-chip mounting connection structure described above has a drawback that cracks are generated when stress is applied to the connection portion due to the difference in thermal expansion coefficient between the substrate and the semiconductor chip.
【0004】[0004]
【課題を解決するための手段】本発明のフリップチップ
実装の接続構造は、半導体チップの電極パッドに形成し
たバンプと基板の搭載パッドとを弾性を有する導電性樹
脂で接続した後、前記半導体チップと前記基板との間に
残った隙間に液状エポキシ樹脂を毛細管現象を利用して
流し込み、前記液状エポキシ樹脂を加熱硬化させて封止
ものである。According to the flip-chip mounting connection structure of the present invention, the bumps formed on the electrode pads of the semiconductor chip and the mounting pads of the substrate are connected by a conductive resin having elasticity, and then the semiconductor chip is mounted. The liquid epoxy resin is poured into the gap left between the substrate and the substrate by utilizing the capillary phenomenon, and the liquid epoxy resin is heated and cured to seal the liquid epoxy resin.
【0005】[0005]
【発明の実施の形態】次に、本発明について図面を参照
して詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings.
【0006】図1は本発明の一実施形態を示す断面図で
ある。半導体チップ2にアルミの電極パッド6があり、
電極パッド6にはボールパンプ3が形成されている。ボ
ールパンプ3と搭載パッド5との間にはAgシリコン樹
脂4があり、両者を電気的に接続している。FIG. 1 is a sectional view showing an embodiment of the present invention. The semiconductor chip 2 has an aluminum electrode pad 6,
The ball pump 3 is formed on the electrode pad 6. There is an Ag silicon resin 4 between the ball pump 3 and the mounting pad 5, and both are electrically connected.
【0007】この構造の形成は次のように行なう。半導
体チップ2の電極パッド6に、ボール部高さ25μm,
突起高さ20μmのAuボールパンプ3を形成した後、
Auボールパンプ3上面に転写法により、Agシリコン
ペースト4を付着させる。次に、搭載パッド5と半導体
チップ2の電極パッド6に形成したボールパンプ3とを
目合せして搭載した後、Agシリコンペースト4を加熱
硬化させて接合する。次に、半導体チップ2と基板1と
の間隙に、液状エポキシ樹脂7を毛細管現象を利用して
流し込んだ後、液状エポキシ樹脂7を加熱硬化させて封
止する。The formation of this structure is performed as follows. The height of the ball portion is 25 μm on the electrode pad 6 of the semiconductor chip 2,
After forming the Au ball pump 3 having a protrusion height of 20 μm,
The Ag silicon paste 4 is attached to the upper surface of the Au ball pump 3 by a transfer method. Next, the mounting pad 5 and the ball pump 3 formed on the electrode pad 6 of the semiconductor chip 2 are aligned and mounted, and then the Ag silicon paste 4 is heat-cured and bonded. Next, the liquid epoxy resin 7 is poured into the gap between the semiconductor chip 2 and the substrate 1 by utilizing a capillary phenomenon, and then the liquid epoxy resin 7 is heat-cured and sealed.
【0008】[0008]
【発明の効果】本発明のフリップチップ実装の接続構造
は、ボールバンプと基板の搭載パッドとを、弾性を有す
る樹脂で接合しているので、半導体チップと基板との熱
膨張係数の差に基づき接続部に生じる応力を緩和できる
ため、接続不良を防止できるという効果がある。According to the flip-chip mounting connection structure of the present invention, since the ball bump and the mounting pad of the substrate are bonded with a resin having elasticity, it is based on the difference in the coefficient of thermal expansion between the semiconductor chip and the substrate. Since the stress generated in the connection portion can be relaxed, there is an effect that connection failure can be prevented.
【図1】本発明の一実施形態を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図2】(a)〜(e)は第1の従来例を示す断面図で
ある。2A to 2E are cross-sectional views showing a first conventional example.
【図3】第2の従来例を示す断面図である。FIG. 3 is a sectional view showing a second conventional example.
1 基板 2 半導体チップ 3 ボールバンプ 4 Agシリコン樹脂 5 搭載パッド 6 電極パッド 7 エポキシ樹脂 1 substrate 2 semiconductor chip 3 ball bump 4 Ag silicon resin 5 mounting pad 6 electrode pad 7 epoxy resin
Claims (3)
ンプと基板の搭載パッドとを弾性を有する導電性樹脂で
接続することを特徴とするフリップチップ実装の接続構
造。1. A flip-chip mounting connection structure characterized in that a bump formed on an electrode pad of a semiconductor chip and a mounting pad on a substrate are connected by a conductive resin having elasticity.
ンプと基板の搭載パッドとを弾性を有する導電性樹脂で
接続した後、前記半導体チップと前記基板との間に残っ
た隙間に液状エポキシ樹脂を毛細管現象を利用して流し
込み、前記液状エポキシ樹脂を加熱硬化させて封止した
ものであることを特徴とするフリップチップ実装の接続
構造。2. A bump formed on an electrode pad of a semiconductor chip and a mounting pad on a substrate are connected by a conductive resin having elasticity, and then a liquid epoxy resin is filled in a gap left between the semiconductor chip and the substrate. A connection structure for flip-chip mounting, characterized in that the liquid epoxy resin is poured in by utilizing a capillary phenomenon, and the liquid epoxy resin is heat-cured and sealed.
である請求項2記載のフリップチップ実装の接続構造。3. The flip-chip mounted connection structure according to claim 2, wherein the conductive resin is Ag silicon paste.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6587296A JPH09260431A (en) | 1996-03-22 | 1996-03-22 | Connection structure of flip chip mounting |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6587296A JPH09260431A (en) | 1996-03-22 | 1996-03-22 | Connection structure of flip chip mounting |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH09260431A true JPH09260431A (en) | 1997-10-03 |
Family
ID=13299515
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6587296A Pending JPH09260431A (en) | 1996-03-22 | 1996-03-22 | Connection structure of flip chip mounting |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH09260431A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002021197A1 (en) * | 2000-09-04 | 2002-03-14 | Cambridge Consultants Limited | Connection method |
CN111106087A (en) * | 2018-10-28 | 2020-05-05 | 立积电子股份有限公司 | Connection structure and forming method thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02103944A (en) * | 1988-10-13 | 1990-04-17 | Matsushita Electric Ind Co Ltd | Mounting method of semiconductor chip |
JPH03261154A (en) * | 1990-03-09 | 1991-11-21 | Sharp Corp | Mounting structure for semiconductor chip |
JPH0936119A (en) * | 1995-07-17 | 1997-02-07 | Matsushita Electric Ind Co Ltd | Semiconductor device, its manufacture and semiconductor unit using the semiconductor device |
-
1996
- 1996-03-22 JP JP6587296A patent/JPH09260431A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02103944A (en) * | 1988-10-13 | 1990-04-17 | Matsushita Electric Ind Co Ltd | Mounting method of semiconductor chip |
JPH03261154A (en) * | 1990-03-09 | 1991-11-21 | Sharp Corp | Mounting structure for semiconductor chip |
JPH0936119A (en) * | 1995-07-17 | 1997-02-07 | Matsushita Electric Ind Co Ltd | Semiconductor device, its manufacture and semiconductor unit using the semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002021197A1 (en) * | 2000-09-04 | 2002-03-14 | Cambridge Consultants Limited | Connection method |
CN111106087A (en) * | 2018-10-28 | 2020-05-05 | 立积电子股份有限公司 | Connection structure and forming method thereof |
CN111106087B (en) * | 2018-10-28 | 2022-03-18 | 立积电子股份有限公司 | Connection structure and forming method thereof |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980623 |