JP2000022300A - Wiring board and electronic unit - Google Patents

Wiring board and electronic unit

Info

Publication number
JP2000022300A
JP2000022300A JP18770198A JP18770198A JP2000022300A JP 2000022300 A JP2000022300 A JP 2000022300A JP 18770198 A JP18770198 A JP 18770198A JP 18770198 A JP18770198 A JP 18770198A JP 2000022300 A JP2000022300 A JP 2000022300A
Authority
JP
Japan
Prior art keywords
wiring board
chip
bare
bonding material
anisotropic conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18770198A
Other languages
Japanese (ja)
Inventor
Minoru Takizawa
稔 滝澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP18770198A priority Critical patent/JP2000022300A/en
Publication of JP2000022300A publication Critical patent/JP2000022300A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain the stable electric connectivity between a wiring board and electronic components, and at the same time to secure the sufficient junction strength between the wiring board and the electronic components without increasing costs or the like. SOLUTION: In a wiring board 10, a recessed part 12r is formed on the surface of an electrode 12, where the recessed part 12r can capture a conductive particle 32 of an anisotropy conductive junction material. Also, in an electronic unit 1, a bare IC chip 20 is mounted onto the wiring board 10 where the recessed part 12r is provided on the surface of the electrode 12 via the anisotropy conductive junction material. Also, in an electronic unit 1', a bare IC chip 20' is mounted onto the wiring board 10' where a recessed part 12'r is provided on the surface of an electrode 12' via an anisotropy conductive junction material 30', and at the same time the wiring board 10' is jointed to the bare IC chip 20' by insulation resin 40' for sealing the anisotropy conductive junction material 30'.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、異方性導電接合材
料を介して電子部品の実装される配線基板と、この配線
基板に異方性導電接合材料を介して電子部品を実装して
成る電子ユニットに関するものである。
The present invention relates to a wiring board on which electronic components are mounted via an anisotropic conductive bonding material and an electronic component mounted on the wiring board via an anisotropic conductive bonding material. It relates to an electronic unit.

【0002】[0002]

【従来の技術】電子部品である半導体装置を、配線基板
(プリント配線板)に実装する方法の1つとして、異方性
導電接合材料を用いたフリップチップ実装方法(フリッ
プチップボンディング法)がある。
2. Description of the Related Art A semiconductor device as an electronic component is mounted on a wiring board.
As one of the methods for mounting on a (printed wiring board), there is a flip chip mounting method (flip chip bonding method) using an anisotropic conductive bonding material.

【0003】図14に示す如く、半導体装置としてのベ
アICチップAは、その実装面(図中底面)に導電材料
から成る電極Aa,Aa…を備え、これら電極Aa,A
a…の表面には、それぞれAu(金)等の金属材料からバ
ンプAb,Ab…が形成されている。
As shown in FIG. 14, a bare IC chip A as a semiconductor device has electrodes Aa, Aa... Made of a conductive material on its mounting surface (bottom in the figure).
The bumps Ab, Ab... are formed from a metal material such as Au (gold) on the surfaces of a.

【0004】また、ベアICチップAの実装される配線
基板Bは、その実装面(図中上面)に導電材料から成る配
線パターンBa,Ba…が形成され、各配線パターンB
a,Ba…の先端表面には、それぞれ金メッキによって
電極Bb,Bb…が形成されている。
The wiring substrate B on which the bare IC chip A is mounted has wiring patterns Ba, Ba... Made of a conductive material on its mounting surface (upper surface in the figure).
Electrodes Bb, Bb,... are formed on the tip surfaces of a, Ba,.

【0005】さらに、配線基板BにベアICチップBを
接合させるための異方性導電接合材料Cは、フィルム状
を呈する絶縁性樹脂Caに、多数の導電粒子Cb,Cb
…を混在させることにより形成されている。
Further, an anisotropic conductive bonding material C for bonding the bare IC chip B to the wiring board B is composed of a film-shaped insulating resin Ca and a large number of conductive particles Cb, Cb.
. Are mixed.

【0006】上述した配線基板BにベアICチップAを
実装するには、先ず、配線基板Bに対して異方性導電接
合材料Cを加熱(80℃,約2秒)および加圧し、配線基
板BにおけるベアICチップAの実装位置に異方性導電
接合材料Cを仮接着する。
To mount the bare IC chip A on the wiring board B, first, the anisotropic conductive bonding material C is heated (80 ° C., about 2 seconds) and pressed on the wiring board B, The anisotropic conductive bonding material C is temporarily bonded to the mounting position of the bare IC chip A in B.

【0007】次いで、異方性導電接合材料C上にベアI
CチップAを載置し、ベアICチップACを加圧すると
ともに、異方性導電接合材料Dを加熱(180℃,約2
0秒)して、ベアICチップAを配線基板Bに本接着す
ることにより、図15に示す如き電子ユニットUが製造
される。
Next, the bare I is placed on the anisotropic conductive bonding material C.
The C chip A is placed, the bare IC chip AC is pressurized, and the anisotropic conductive bonding material D is heated (180 ° C., about 2 ° C.).
(0 second), and the bare IC chip A is permanently bonded to the wiring board B, whereby the electronic unit U as shown in FIG. 15 is manufactured.

【0008】ここで、ベアICチップAを配線基板Bに
本接着する際、ベアICチップAにおける各バンプAb
と、配線基板Bにおける各電極Baとの間に、異方性導
電接合材料Cにおける導電粒子Cb,Cb…が挟み込ま
れることで、アICチップAと配線基板Bとが電気的に
接続されるとともに、異方性導電接合材料Cの絶縁性樹
脂Caが熱硬化することで、ベアICチップAが配線基
板Bに対して機械的に接合されることとなる。
Here, when the bare IC chip A is fully bonded to the wiring board B, each bump Ab on the bare IC chip A is used.
Are sandwiched between the conductive particles Cb, Cb,... Of the anisotropic conductive bonding material C between the IC chip A and the wiring board B. At the same time, when the insulating resin Ca of the anisotropic conductive bonding material C is thermally cured, the bare IC chip A is mechanically bonded to the wiring board B.

【0009】[0009]

【発明が解決しようとする課題】ところで、上述した構
成では、ベアICチップAにおける各バンプAbの底面
と、配線基板Bにおける電極Bb,Bb…の上面とが、
共に凹凸のない平坦な形状を呈しているため、ベアIC
チップAを配線基板Bに本接着するべく、異方性導電接
合材料Cを介して配線基板BにベアICチップAを押圧
した際、異方性導電接合材料Cにおける絶縁性樹脂Ca
の流動性により、ベアICチップAにおけるバンプAb
の底面と、配線基板Bにおける電極Bbの上面との間か
ら、異方性導電接合材料Cの導電粒子Cb,Cb…が流
れ出してしまう。
In the configuration described above, the bottom surface of each bump Ab in the bare IC chip A and the upper surface of the electrodes Bb, Bb.
Since both have a flat shape without unevenness, bare IC
When the bare IC chip A is pressed against the wiring board B via the anisotropic conductive bonding material C in order to fully bond the chip A to the wiring board B, the insulating resin Ca in the anisotropic conductive bonding material C
Due to the fluidity of the bumps Ab on the bare IC chip A
.. Of the anisotropic conductive bonding material C flow out from between the bottom surface of the substrate and the upper surface of the electrode Bb of the wiring board B.

【0010】この結果、ベアICチップAにおけるバン
プAbと、配線基板Bにおける電極Bbとの間に、適量
の導電粒子Cb,Cb…を確保することが困難となり、
これによってバンプAbと電極Bbとの電気的な接続性
が著しく低下してしまう不都合があった。
As a result, it becomes difficult to secure an appropriate amount of conductive particles Cb between the bump Ab on the bare IC chip A and the electrode Bb on the wiring board B.
As a result, there is a disadvantage that the electrical connectivity between the bump Ab and the electrode Bb is significantly reduced.

【0011】これに対し、バンプAbと電極Bbとの間
に十分な個数の導電粒子Cb,Cb…を確保させるべ
く、多量の導電粒子Cbを含んだ異方性導電接合材料C
を用いた場合、隣接する電極あるいはバンプ間における
絶縁性の低下や、配線基板BとベアICチップAとの接
続強度の低下、さらには高価な異方性導電接合材料Cを
用いることによるコストの増大を招いてしまう。
On the other hand, in order to secure a sufficient number of conductive particles Cb between the bump Ab and the electrode Bb, an anisotropic conductive bonding material C containing a large amount of conductive particles Cb is used.
Is used, the insulation between adjacent electrodes or bumps is reduced, the connection strength between the wiring board B and the bare IC chip A is reduced, and the cost due to the use of the expensive anisotropic conductive bonding material C is reduced. It leads to an increase.

【0012】本発明は上記実状に鑑みて、絶縁性および
接続強度の低下や、不用意なコストの増大を招くことな
く、異方性導電接合材料を介して配線基板に電子部品を
実装した状態において、配線基板と電子部品との安定し
た電気的接続性を得ることの可能な、配線基板および電
子ユニットの提供を目的とするものである。
In view of the above situation, the present invention provides a state in which an electronic component is mounted on a wiring board via an anisotropic conductive bonding material without lowering insulation properties and connection strength and without inadvertently increasing costs. In the above, an object of the present invention is to provide a wiring board and an electronic unit capable of obtaining stable electrical connectivity between the wiring board and the electronic component.

【0013】また、上述した電子ユニットUは、異方性
導電接合材料Cを介して配線基板BとベアICチップA
とを接合しているために、適正な接合強度を確保するこ
とが困難である。
The electronic unit U described above is connected to the wiring board B and the bare IC chip A via the anisotropic conductive bonding material C.
Therefore, it is difficult to secure an appropriate bonding strength.

【0014】これに対し、接合強度を増大させるべく、
膜厚の厚い異方性導電接合材料や、絶縁性樹脂量の多い
異方性導電接合材料を用いた場合、高価な異方性導電接
合材料Cを用いることでコストの増大を招いてしまう。
On the other hand, in order to increase the bonding strength,
When an anisotropic conductive bonding material having a large film thickness or an anisotropic conductive bonding material having a large amount of insulating resin is used, the use of the expensive anisotropic conductive bonding material C causes an increase in cost.

【0015】本発明は上記実状に鑑みて、不用意なコス
トの増大を招くことなく、配線基板と電子部品との十分
な接合強度を確保し得る電子ユニットの提供を目的とす
るものである。
An object of the present invention is to provide an electronic unit capable of securing a sufficient bonding strength between a wiring board and an electronic component without inadvertently increasing the cost in view of the above situation.

【0016】[0016]

【課題を解決するための手段】請求項1の本発明に関わ
る配線基板は、電極の表面に異方性導電接合材料の導電
粒子を捕捉し得る凹部を形成している。
According to a first aspect of the present invention, there is provided a wiring board having a concave portion formed on a surface of an electrode for capturing conductive particles of an anisotropic conductive bonding material.

【0017】また、請求項2の本発明に関わる電子ユニ
ットは、電極の表面に異方性導電接合材料の導電粒子を
捕捉し得る凹部を設けて成る配線基板に、異方性導電接
合材料を介して電子部品を実装している。
According to a second aspect of the present invention, there is provided the electronic unit, wherein the anisotropic conductive bonding material is provided on a wiring substrate having a concave portion capable of capturing conductive particles of the anisotropic conductive bonding material on the surface of the electrode. Electronic components are mounted via.

【0018】また、請求項3の本発明に関わる電子ユニ
ットは、電極の表面に異方性導電接合材料の導電粒子を
捕捉し得る凹部を設けて成る配線基板に、異方性導電接
合材料を介して電子部品を実装するとともに、異方性導
電接合材料を封止する絶縁性樹脂によって配線基板と電
子部品とを接合している。
According to a third aspect of the present invention, there is provided the electronic unit, wherein the anisotropic conductive bonding material is provided on a wiring substrate having a concave portion capable of capturing conductive particles of the anisotropic conductive bonding material on the surface of the electrode. The electronic component is mounted on the wiring board and the wiring board and the electronic component are joined by an insulating resin for sealing the anisotropic conductive bonding material.

【0019】[0019]

【発明の実施の形態】以下、実施例を示す図面に基づい
て、本発明を詳細に説明する。図1は、フリップチップ
実装方法によって製造された、本発明に関わる電子ユニ
ット1を示している。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing embodiments. FIG. 1 shows an electronic unit 1 according to the present invention manufactured by a flip chip mounting method.

【0020】この電子ユニット1は、図1および図2に
示す如く、本発明に関わる配線基板10と、電子部品と
してのベアICチップ20とを具備し、異方性導電接合
材料30を用いて配線基板10にベアICチップ20を
実装することにより構成されている。
As shown in FIGS. 1 and 2, the electronic unit 1 includes a wiring board 10 according to the present invention and a bare IC chip 20 as an electronic component. It is configured by mounting the bare IC chip 20 on the wiring board 10.

【0021】また、前記電子ユニット1は、図3に示す
如く配線基板10に異方性導電接合材料30を仮接着す
る工程Saと、ベアICチップ20にバンプを形成する
工程Sbと、異方性導電接合材料30を介して配線基板
10にベアICチップ20を本接着する工程Scとを経
て製造される。
As shown in FIG. 3, the electronic unit 1 includes a step Sa of temporarily bonding the anisotropic conductive bonding material 30 to the wiring board 10 and a step Sb of forming a bump on the bare IC chip 20. And a step Sc of permanently bonding the bare IC chip 20 to the wiring board 10 via the conductive conductive bonding material 30.

【0022】図4に示す如く、配線基板10は、ガラス
エポキシ樹脂等によって構成されており、ベアICチッ
プ20の実装される実装面(図中の上面)には、導電材料
から複数の配線パターン11が形成され、各配線パター
ン11の先端表面には、それぞれ金メッキによって電極
12が形成されている。なお、各配線パターン11は、
電極12の部分を除いてソルダーレジスト13により覆
われている。
As shown in FIG. 4, the wiring board 10 is made of a glass epoxy resin or the like, and a mounting surface (upper surface in the drawing) on which the bare IC chip 20 is mounted has a plurality of wiring patterns made of conductive material. An electrode 12 is formed on the front end surface of each wiring pattern 11 by gold plating. In addition, each wiring pattern 11
Except for the part of the electrode 12, it is covered with the solder resist 13.

【0023】図5(a),(b)に示す如く、配線パターン
11における電極12の表面には、後述する異方性導電
接合材料の導電粒子を捕捉し得る複数の凹部12rが形
成されており、この凹部12rは配線パターン11の延
在方向に対して略直交する方向に延びるV字状の溝であ
って、その深さは約1〜5μmに設定されている。
As shown in FIGS. 5A and 5B, the surface of the electrode 12 in the wiring pattern 11 is formed with a plurality of concave portions 12r capable of capturing conductive particles of an anisotropic conductive bonding material described later. The recess 12r is a V-shaped groove extending in a direction substantially perpendicular to the extending direction of the wiring pattern 11, and has a depth of about 1 to 5 μm.

【0024】また、上記凹部12rはメッキ法、すなわ
ち配線パターン11に電極12を構成する際のメッキ工
程において形成する方法、あるいは削り出し法、すなわ
ち配線パターン11に電極12を構成しているメッキ層
をツールによって削り出す方法を用いて形成されてい
る。
The recess 12r is formed by a plating method, that is, a method of forming the electrode 12 in the wiring pattern 11 in a plating step, or a shaving method, that is, a plating layer forming the electrode 12 in the wiring pattern 11. Is formed by using a method of shaving off with a tool.

【0025】なお、図6(a),(b)に示す如く、電極1
2の表面を配線パターン11の延在方向に延びるV溝に
よって、凹部12rを構成することも可能である。ま
た、図7(a),(b)に示す如く、電極12の表面を配線
パターン11の延在方向に対して斜めに交差するV溝に
よって、凹部12rを構成することも可能である。
As shown in FIGS. 6A and 6B, the electrode 1
The recess 12r may be formed by a V-groove extending in the direction in which the wiring pattern 11 extends in the surface of the second pattern 2. Also, as shown in FIGS. 7A and 7B, the concave portion 12r can be formed by a V-groove obliquely intersecting the surface of the electrode 12 with the extending direction of the wiring pattern 11.

【0026】一方、電子部品としてのベアICチップ2
0は、図2に示す如く配線基板10と対向する実装面
(図中底面)に、Al(アルミニウム)等の導電材料から成
る電極21,21…が形成されている。
On the other hand, bare IC chip 2 as an electronic component
0 is the mounting surface facing the wiring board 10 as shown in FIG.
Electrodes 21, 21... Made of a conductive material such as Al (aluminum) are formed on the bottom surface (in the figure).

【0027】これら電極21,21…は、配線基板10
における各電極11A,11A…と対応して配置されて
おり、ベアICチップ20の電極21,21…の表面に
は、配線基板10へ実装する前の段階(図3の工程Sb)
で、Au(金)あるいはSn−Pb(錫−鉛)合金等から成
るバンプ22,22…が形成される。
The electrodes 21, 21,...
Are arranged corresponding to the electrodes 11A, 11A,... On the surfaces of the electrodes 21, 21,... Of the bare IC chip 20 before the mounting on the wiring board 10 (step Sb in FIG. 3).
Are formed from Au (gold) or Sn-Pb (tin-lead) alloy.

【0028】配線基板10にベアICチップ20を実装
するための異方性導電接合材料30は、絶縁性樹脂31
に、粒子径が約3〜10μmの導電粒子32,32…を
混在させ、フィルム状に形成したものである。なお、こ
の異方性導電接合材料30は、上述したベアICチップ
20の実装面よりも一回り大きい形状(面積比で1.0
5倍程度)を呈している。
The anisotropic conductive bonding material 30 for mounting the bare IC chip 20 on the wiring board 10 is made of an insulating resin 31.
Are mixed with conductive particles 32 having a particle diameter of about 3 to 10 μm to form a film. The anisotropic conductive bonding material 30 has a shape that is slightly larger than the mounting surface of the bare IC chip 20 described above (in terms of area ratio of 1.0).
5 times).

【0029】以下では、上述した構成の電子ユニット1
を製造する方法、言い換えれば配線基板10に対するベ
アICチップ20の実装工程を説明する。
Hereinafter, the electronic unit 1 having the above configuration will be described.
, That is, a process of mounting the bare IC chip 20 on the wiring board 10 will be described.

【0030】先ず、図8に示す如く、配線基板10の実
装面に異方性導電接合材料30を載置し、こののちヒー
トツール(図示せず)によって異方性導電接合材料30を
加熱(80℃、約5秒)かつ上方から加圧し、配線基板1
0に異方性導電接合材料30を仮接着する(図3中の工
程Sa)。
First, as shown in FIG. 8, the anisotropic conductive bonding material 30 is placed on the mounting surface of the wiring board 10, and then the anisotropic conductive bonding material 30 is heated by a heat tool (not shown). 80 ° C, about 5 seconds)
The temporary bonding of the anisotropic conductive bonding material 30 is carried out to 0 (step Sa in FIG. 3).

【0031】次いで、図9に示す如く、仮接着された異
方性導電接合材料30に、ベアICチップ20を載置し
たのち、ヒートツールHを用いてベアICチップ20を
加圧するとともに、異方性導電接合材料30を加熱(1
80℃、約20秒)して、ベアICチップ20を配線基
板10に本接着する(図3中の工程Sc)。
Next, as shown in FIG. 9, after the bare IC chip 20 is placed on the anisotropic conductive bonding material 30 temporarily bonded, the bare IC chip 20 is pressed using The isotropic conductive bonding material 30 is heated (1
At 80 ° C. for about 20 seconds), the bare IC chip 20 is fully bonded to the wiring board 10 (step Sc in FIG. 3).

【0032】かくして、配線基板10とベアICチップ
20とが、溶融したのち硬化した異方性導電接合材料3
0の絶縁性樹脂31によって接合されるとともに、配線
基板10の各電極11AとベアICチップ20の各電極
21(バンプ22)との間に、異方性導電接合材料30の
導電粒子32,32…が挟み込まれることで、互いに電
気的に接続される。
Thus, the anisotropic conductive bonding material 3 in which the wiring substrate 10 and the bare IC chip 20 are melted and then hardened.
And the conductive particles 32 of the anisotropic conductive bonding material 30 between each electrode 11A of the wiring board 10 and each electrode 21 (bump 22) of the bare IC chip 20. Are electrically connected to each other.

【0033】ここで、ヒートツールHによってベアIC
チップ20を加圧する工程では、異方性導電接合材料3
0における導電粒子32,32…が、ベアICチップ2
0の下降に伴って、各電極12の凹部12rに捕捉され
ることにより、配線基板10における電極12と、ベア
ICチップ20の電極21(バンプ22)との間に、適量
(100平方μm当たり約5〜20個)の導電粒子32が
確保される。
Here, the bare IC is heated by the heat tool H.
In the step of pressing the chip 20, the anisotropic conductive bonding material 3
., The bare IC chip 2
As a result, the electrode 12 is caught by the concave portion 12r of each electrode 12 along with the drop of 0, so that an appropriate amount of space is formed between the electrode 12 on the wiring board 10 and the electrode 21 (bump 22) of the bare IC chip 20.
(Approximately 5 to 20 conductive particles 32 per 100 square μm) are secured.

【0034】このようにして、配線基板10における電
極12とベアICチップ20の電極21(バンプ22)と
の間に、十分な個数の導電週子が介在することにより、
配線基板10とベアICチップ20との安定した電気的
接続性が得られる。
In this manner, a sufficient number of conductive probes are interposed between the electrodes 12 on the wiring board 10 and the electrodes 21 (bumps 22) of the bare IC chip 20.
Stable electrical connectivity between the wiring substrate 10 and the bare IC chip 20 is obtained.

【0035】また、ヒートツールHによってベアICチ
ップ20を加圧する工程において、ベアICチップ20
の電極21に形成されたバンプ22が、図9に示す如
く、配線基板10における電極12の凹部12rに食い
込むように変形して密着することで、上述した導電粒子
32の介在と併せ、配線基板10の電極12とベアIC
チップ20のバンプ22との電気的接続性が大幅に向上
することとなる。
In the step of pressing the bare IC chip 20 with the heat tool H, the bare IC chip 20
As shown in FIG. 9, the bumps 22 formed on the electrodes 21 are deformed so as to bite into the recesses 12r of the electrodes 12 on the wiring board 10 and are brought into close contact with each other. 10 electrodes 12 and bare IC
The electrical connectivity with the bumps 22 of the chip 20 is greatly improved.

【0036】さらに、上述の如く、ベアICチップ20
のバンプ22が配線基板10における電極12の凹部1
2rに食い込んで密着することにより、異方性導電接合
材料30における絶縁性樹脂31と併せて、配線基板1
0とベアICチップ20との機械的な接続性が大幅に向
上することとなる。
Further, as described above, the bare IC chip 20
Bumps 22 are recessed portions 1 of electrodes 12 in wiring board 10.
2r so that the wiring board 1 and the insulating resin 31 in the anisotropic conductive bonding material 30
0 and the bare IC chip 20 are greatly improved in mechanical connectivity.

【0037】図10に示す電子ユニット1′は、配線基
板10′とベアICチップ20′とを具備し、異方性導
電接合材料30′を用いて配線基板10′にベアICチ
ップ20′を実装し、絶縁性樹脂40′によって異方性
導電接合材料30′を封止することにより構成されてい
る。
The electronic unit 1 'shown in FIG. 10 includes a wiring board 10' and a bare IC chip 20 '. The bare IC chip 20' is mounted on the wiring board 10 'using an anisotropic conductive bonding material 30'. It is configured by mounting and sealing the anisotropic conductive bonding material 30 ′ with the insulating resin 40 ′.

【0038】また、この電子ユニット1′は、図11に
示す如く、配線基板10′に異方性導電接合材料30′
を仮接着する工程Saと、ベアICチップ20′にバン
プを形成する工程Sbと、異方性導電接合材料30′を
介して配線基板10′にベアICチップ20′を本接着
する工程Scと、配線基板10′にダムを形成する工程
Sdと、絶縁性樹脂40′を供給する工程Seを経て製
造される。
Further, as shown in FIG. 11, the electronic unit 1 'includes an anisotropic conductive bonding material 30'
Sa, a step Sb of forming bumps on the bare IC chip 20 ', and a step Sc of permanently bonding the bare IC chip 20' to the wiring board 10 'via the anisotropic conductive bonding material 30'. It is manufactured through a step Sd of forming a dam on the wiring board 10 'and a step Se of supplying an insulating resin 40'.

【0039】なお、電子ユニット1′における絶縁性樹
脂40′による封止以外の構成は、先に説明した電子ユ
ニット1と同一なので、図10以降の図中において、電
子ユニット1と同一の作用を成す要素に、図1から図9
と同一の番号に′(ダッシュ)を附して詳細な説明は省略
する。
Since the structure of the electronic unit 1 'other than the sealing with the insulating resin 40' is the same as that of the electronic unit 1 described above, the same operation as that of the electronic unit 1 is shown in FIGS. The elements to be formed are shown in FIGS.
The same reference numerals as those described above are denoted by '(dash), and detailed description is omitted.

【0040】また、電子ユニット1′の製造工程におい
ても、配線基板10′にベアICチップ20′を本接着
する工程(図11中の工程Sc)までは、上述した電子ユ
ニット1の製造工程と何ら変わるところはない。
In the manufacturing process of the electronic unit 1 ', the process of manufacturing the electronic unit 1 described above is the same as the process of completely bonding the bare IC chip 20' to the wiring board 10 '(process Sc in FIG. 11). Nothing changes.

【0041】上述した電子ユニット1′を製造する場合
には、配線基板10′にベアICチップ20′を本接着
したのち、図12に示す如く、配線基板10′の上面に
ダム14′を形成する(図11中の工程Sd)。ここで前
記ダム14′は、図10に示す如く、配線基板10′の
ソルダーレジスト13′上に、ベアICチップ20′の
周囲を囲むようにして形成される。
In the case of manufacturing the above-described electronic unit 1 ', after a bare IC chip 20' is permanently bonded to the wiring board 10 ', a dam 14' is formed on the upper surface of the wiring board 10 'as shown in FIG. (Step Sd in FIG. 11). Here, as shown in FIG. 10, the dam 14 'is formed on the solder resist 13' of the wiring board 10 'so as to surround the bare IC chip 20'.

【0042】次いで、ダム14′の内側に、例えばペー
スト状の絶縁性樹脂40′を供給する(図11中の工程
Se)。このとき、絶縁性樹脂40′は、ベアICチッ
プ20′の外周面とダム14′の内周面とに囲まれた領
域を満たし、異方性導電接合材料30′の表面を覆うよ
うに供給される。
Next, for example, a paste-like insulating resin 40 'is supplied to the inside of the dam 14' (step Se in FIG. 11). At this time, the insulating resin 40 'is supplied so as to fill the area surrounded by the outer peripheral surface of the bare IC chip 20' and the inner peripheral surface of the dam 14 'and cover the surface of the anisotropic conductive bonding material 30'. Is done.

【0043】こののち、絶縁性樹脂40′を硬化させる
ことにより、この絶縁性樹脂40′によって異方性導電
接合材料30′が封止され、かつ配線基板10とベアI
Cチップ20とが互いに接合されることとなる。
Thereafter, by curing the insulating resin 40 ', the anisotropic conductive bonding material 30' is sealed by the insulating resin 40 ', and the wiring board 10 and the bare I
The C chip 20 is joined to each other.

【0044】上述した如き構成の電子ユニット1′で
は、先に詳述した電子ユニット1と同様、配線基板1
0′にベアICチップ20′を本接着する工程におい
て、異方性導電接合材料30′の導電粒子32′,3
2′…が、電極12′の凹部12r′に捕捉されること
で、配線基板10′の電極12′とベアICチップ2
0′の電極21′(バンプ22′)との間に、適量(10
0平方μm当たり約5〜20個)の導電粒子32′が確保
され、配線基板10′とベアICチップ20′との安定
した電気的接続性が得られる。
In the electronic unit 1 'having the above-described structure, the wiring board 1 is provided similarly to the electronic unit 1 described in detail above.
In the step of permanently bonding the bare IC chip 20 'to the conductive particles 32', 3 'of the anisotropic conductive bonding material 30'.
Are captured by the concave portion 12r 'of the electrode 12', so that the electrode 12 'of the wiring board 10' and the bare IC chip 2
0 ′ electrode 21 ′ (bump 22 ′).
The conductive particles 32 '(about 5 to 20 particles per square micrometer) are secured, and stable electrical connection between the wiring board 10' and the bare IC chip 20 'can be obtained.

【0045】また、配線基板10′にベアICチップ2
0′を本接着する工程で、ベアICチップ20′のバン
プ22′が、配線基板10′の電極12′の凹部12
r′に食い込むように変形して密着するため、配線基板
10′の電極12′とベアICチップ20′のバンプ2
2′との電気的接続性が大幅に向上する。
The bare IC chip 2 is mounted on the wiring board 10 '.
In the step of fully bonding the first IC chip 0 ', the bumps 22' of the bare IC chip 20 'become
r 'so as to bite into the electrode r', the electrode 12 'of the wiring board 10' and the bump 2 of the bare IC chip 20 '.
The electrical connectivity with 2 'is greatly improved.

【0046】さらに、上述の如く、ベアICチップ2
0′のバンプ22′が配線基板10′の電極12′の凹
部12r′に食い込んで密着することにより、配線基板
10′とベアICチップ20′との機械的な接続性が大
幅に向上する。
Further, as described above, the bare IC chip 2
Since the 0 'bumps 22' bite into the recesses 12r 'of the electrodes 12' of the wiring board 10 'and come into close contact therewith, the mechanical connectivity between the wiring board 10' and the bare IC chip 20 'is greatly improved.

【0047】さらに、上記構成の電子ユニット1′で
は、異方性導電接合材料30′における絶縁性樹脂3
1′によって、配線基板10′とベアICチップ20′
とを機械的に接合していることと併せ、異方性導電接合
材料30を覆う絶縁性樹脂40′によっても、配線基板
10′とベアICチップ20′とを機械的に接合してい
るので、配線基板10′とベアICチップ20′との十
分な接合強度を確保することが可能となる。
Further, in the electronic unit 1 'having the above structure, the insulating resin 3' in the anisotropic conductive bonding material 30 'is used.
1 ', the wiring board 10' and the bare IC chip 20 '
The wiring board 10 'and the bare IC chip 20' are also mechanically joined by the insulating resin 40 'covering the anisotropic conductive joining material 30 in addition to the mechanical joining of Thus, it is possible to secure sufficient bonding strength between the wiring board 10 'and the bare IC chip 20'.

【0048】なお、上述した各実施例においては、配線
基板にベアICチップをフリップチップ実装するための
異方性導電接合材料として、フィルム状を呈する異方性
導電接合材料(異方性導電フィルム)を採用しているが、
ペースト状の異方性導電接合材料(異方性導電ペースト)
を採用することも可能である。
In each of the embodiments described above, a film-like anisotropic conductive bonding material (anisotropic conductive film) is used as an anisotropic conductive bonding material for flip-chip mounting a bare IC chip on a wiring board. ), But
Paste-like anisotropic conductive bonding material (anisotropic conductive paste)
It is also possible to employ.

【0049】また、上述した各実施例においては、配線
基板に実装される電子部品としてベアICチップを例示
しているが、配線基板に対してフリップチップ実装され
る電子部品であれば、ベアICチップ以外の様々な電子
部品を搭載する配線基板や電子ユニットにおいても、本
発明を有効に適用し得ることは言うまでもない。
In each of the above-described embodiments, a bare IC chip is exemplified as an electronic component mounted on a wiring board. Needless to say, the present invention can be effectively applied to a wiring board or an electronic unit on which various electronic components other than the chip are mounted.

【0050】[0050]

【発明の効果】以上、詳述した如く、請求項1の本発明
に関わる配線基板は、電極の表面に異方性導電接合材料
の導電粒子を捕捉し得る凹部を形成している。上記構成
では、配線基板に電子部品を本接着する際、異方性導電
接合材料の導電粒子が電極の凹部に捕捉されるため、多
量の導電粒子を含んだ異方性導電接合材料を用いること
なく、電子部品と配線基板との間に十分な個数の導電粒
子を確保することが可能となり、もって本発明に関わる
配線基板によれば、絶縁性および接続強度の低下や不用
意なコストの増大を招くことなく、配線基板と電子部品
との安定した電気的接続性を得ることができる。
As described above in detail, the wiring board according to the first aspect of the present invention has a concave portion on the surface of the electrode which can capture the conductive particles of the anisotropic conductive bonding material. In the above configuration, when the electronic component is permanently bonded to the wiring board, since the conductive particles of the anisotropic conductive bonding material are trapped in the concave portions of the electrodes, the anisotropic conductive bonding material containing a large amount of conductive particles should be used. In addition, it is possible to secure a sufficient number of conductive particles between the electronic component and the wiring board, and according to the wiring board of the present invention, the insulation and the connection strength are reduced and the cost is increased carelessly. , Stable electrical connection between the wiring board and the electronic component can be obtained.

【0051】また、請求項2の本発明に関わる電子ユニ
ットは、電極の表面に異方性導電接合材料の導電粒子を
捕捉し得る凹部を設けて成る配線基板に、異方性導電接
合材料を介して電子部品を実装している。上記構成で
は、配線基板に電子部品を本接着する際、異方性導電接
合材料の導電粒子が電極の凹部に捕捉されるため、多量
の導電粒子を含んだ異方性導電接合材料を用いることな
く、電子部品と配線基板との間に十分な個数の導電粒子
を確保することが可能となり、もって本発明に関わる電
子ユニットによれば、絶縁性および接続強度の低下や不
用意なコストの増大を招くことなく、配線基板と電子部
品との安定した電気的接続性を得ることができる。
According to a second aspect of the present invention, in the electronic unit according to the present invention, the anisotropic conductive bonding material is provided on a wiring board having a concave portion capable of capturing conductive particles of the anisotropic conductive bonding material on the surface of the electrode. Electronic components are mounted via. In the above configuration, when the electronic component is permanently bonded to the wiring board, since the conductive particles of the anisotropic conductive bonding material are trapped in the concave portions of the electrodes, the anisotropic conductive bonding material containing a large amount of conductive particles should be used. Therefore, it is possible to secure a sufficient number of conductive particles between the electronic component and the wiring board, and thus, according to the electronic unit according to the present invention, the insulation and the connection strength are reduced and the cost is increased unintentionally. , Stable electrical connection between the wiring board and the electronic component can be obtained.

【0052】また、請求項3の本発明に関わる電子ユニ
ットは、電極の表面に異方性導電接合材料の導電粒子を
捕捉し得る凹部を設けて成る配線基板に、異方性導電接
合材料を介して電子部品を実装するとともに、異方性導
電接合材料を封止する絶縁性樹脂によって配線基板と電
子部品とを接合している。上記構成では、異方性導電接
合材料によって配線基板と電子部品とを接合するととも
に、異方性導電接合材料を封止する絶縁性樹脂によっ
て、配線基板と電子部品とを接合しているので、膜厚の
厚い異方性導電接合材料や絶縁性樹脂量の多い異方性導
電接合材料を用いることなく、配線基板と電子部品とを
強固に接合させることが可能となり、もって本発明に関
わる電子ユニットによれば、不用意なコストの増大を招
くことなく、配線基板と電子部品との十分な接合強度を
確保することができる。
According to a third aspect of the present invention, there is provided the electronic unit, wherein the anisotropic conductive bonding material is provided on a wiring board having a concave portion capable of capturing conductive particles of the anisotropic conductive bonding material on the surface of the electrode. The electronic component is mounted on the wiring board and the wiring board and the electronic component are joined by an insulating resin for sealing the anisotropic conductive bonding material. In the above configuration, the wiring board and the electronic component are joined by the anisotropic conductive bonding material, and the wiring board and the electronic component are joined by the insulating resin that seals the anisotropic conductive bonding material. Without using a thick anisotropic conductive bonding material having a large thickness or an anisotropic conductive bonding material having a large amount of insulating resin, the wiring board and the electronic component can be firmly bonded to each other. According to the unit, it is possible to secure sufficient bonding strength between the wiring board and the electronic component without inadvertently increasing the cost.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に関わる電子ユニットを示す概念的な断
面側面図。
FIG. 1 is a conceptual cross-sectional side view showing an electronic unit according to the present invention.

【図2】本発明に関わる電子ユニットの構成要素を示す
概念図。
FIG. 2 is a conceptual diagram showing components of an electronic unit according to the present invention.

【図3】本発明に関わ配線基板を示す概念的な断面側面
図。
FIG. 3 is a conceptual cross-sectional side view showing a wiring board according to the present invention.

【図4】(a)および(b)は、本発明に関わる配線基板の
電極を示す要部平面図および要部断面図。
FIGS. 4A and 4B are a main part plan view and a main part sectional view showing electrodes of a wiring board according to the present invention.

【図5】(a)および(b)は、本発明に関わる配線基板の
電極における他の実施例を示す要部平面図および要部断
面図。
FIGS. 5A and 5B are a main part plan view and a main part sectional view showing another embodiment of an electrode of a wiring board according to the present invention.

【図6】(a)および(b)は、本発明に関わる配線基板の
電極における他の実施例を示す要部平面図および要部断
面図。
FIGS. 6A and 6B are a plan view and a cross-sectional view of a main part showing another embodiment of an electrode of a wiring board according to the present invention.

【図7】本発明に関わる電子ユニットの製造工程を示す
フローチャート。
FIG. 7 is a flowchart showing a manufacturing process of the electronic unit according to the present invention.

【図8】本発明に関わる電子ユニットの製造工程を示す
概念図。
FIG. 8 is a conceptual diagram showing a manufacturing process of an electronic unit according to the present invention.

【図9】本発明に関わる電子ユニットの製造工程を示す
概念図。
FIG. 9 is a conceptual diagram showing a manufacturing process of an electronic unit according to the present invention.

【図10】(a)および(b)は、本発明に関わる電子ユニ
ットの他の実施例を示す概念的な断面側面図および要部
平面図。
FIGS. 10A and 10B are conceptual cross-sectional side views and a main part plan view showing another embodiment of the electronic unit according to the present invention.

【図11】図10に示した電子ユニットの製造工程を示
すフローチャート。
11 is a flowchart showing a manufacturing process of the electronic unit shown in FIG.

【図12】図10に示した電子ユニットの製造工程を示
す概念図。
FIG. 12 is a conceptual diagram showing a manufacturing process of the electronic unit shown in FIG.

【図13】図10に示した電子ユニットの製造工程を示
す概念図。
FIG. 13 is a conceptual diagram showing a manufacturing process of the electronic unit shown in FIG.

【図14】従来の電子ユニットの製造工程を示すフロー
チャート。
FIG. 14 is a flowchart showing a conventional electronic unit manufacturing process.

【図15】従来の電子ユニットの構成要素を示す概念
図。
FIG. 15 is a conceptual diagram showing components of a conventional electronic unit.

【符号の説明】[Explanation of symbols]

1,1′…電子ユニット、 10,10′…配線基板、 11,11′…配線パターン 12,12′…電極、 12r,12r′…凹部、 20,20′…ベアICチップ(電子部品)、 30,30′…異方性導電性接合材料、 31,31′…絶縁性樹脂、 32,32′…導電粒子、 40′…絶縁性樹脂。 1, 1 ': electronic unit, 10, 10': wiring board, 11, 11 ': wiring pattern 12, 12': electrode, 12r, 12r ': concave portion, 20, 20': bare IC chip (electronic component), 30, 30 ': anisotropic conductive bonding material; 31, 31': insulating resin; 32, 32 ': conductive particles; 40': insulating resin.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 異方性導電接合材料を介して電子部品
の実装される配線基板であって、 前記異方性導電接合材料における導電粒子を捕捉し得る
凹部を、電極の表面に設けて成ることを特徴とする配線
基板。
1. A wiring board on which an electronic component is mounted via an anisotropic conductive bonding material, wherein a recess capable of capturing conductive particles in the anisotropic conductive bonding material is provided on a surface of an electrode. A wiring board characterized by the above-mentioned.
【請求項2】 電極の表面に異方性導電接合材料の導
電粒子を捕捉し得る凹部を設けて成る配線基板に、前記
異方性導電接合材料を介して電子部品を実装して成るこ
とを特徴とする電子ユニット。
2. An electronic component mounted on a wiring board having a concave portion capable of capturing conductive particles of an anisotropic conductive bonding material provided on a surface of an electrode, via an anisotropic conductive bonding material. Electronic unit featuring.
【請求項3】 電極の表面に異方性導電接合材料の導
電粒子を捕捉し得る凹部を設けて成る配線基板に、前記
異方性導電接合材料を介して電子部品を実装するととも
に、前記異方性導電接合材料を封止する絶縁性樹脂によ
って、前記配線基板と前記電子部品とを接合して成るこ
とを特徴とする電子ユニット。
3. An electronic component is mounted on a wiring board having a concave portion capable of capturing conductive particles of an anisotropic conductive bonding material on a surface of an electrode, via the anisotropic conductive bonding material, and an electronic component is mounted. An electronic unit, wherein the wiring board and the electronic component are joined by an insulating resin sealing an isotropic conductive joining material.
JP18770198A 1998-07-02 1998-07-02 Wiring board and electronic unit Pending JP2000022300A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18770198A JP2000022300A (en) 1998-07-02 1998-07-02 Wiring board and electronic unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18770198A JP2000022300A (en) 1998-07-02 1998-07-02 Wiring board and electronic unit

Publications (1)

Publication Number Publication Date
JP2000022300A true JP2000022300A (en) 2000-01-21

Family

ID=16210655

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18770198A Pending JP2000022300A (en) 1998-07-02 1998-07-02 Wiring board and electronic unit

Country Status (1)

Country Link
JP (1) JP2000022300A (en)

Cited By (9)

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Publication number Priority date Publication date Assignee Title
JP2002170838A (en) * 2000-11-30 2002-06-14 Shinkawa Ltd Semiconductor device and its manufacturing method
JP2006245140A (en) * 2005-03-01 2006-09-14 Nissha Printing Co Ltd Connection structure and method of connection of circuit terminal
JP2007324278A (en) * 2006-05-31 2007-12-13 Fujitsu Ltd Semiconductor device and manufacturing method therefor
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002170838A (en) * 2000-11-30 2002-06-14 Shinkawa Ltd Semiconductor device and its manufacturing method
JP2006245140A (en) * 2005-03-01 2006-09-14 Nissha Printing Co Ltd Connection structure and method of connection of circuit terminal
JP2007324278A (en) * 2006-05-31 2007-12-13 Fujitsu Ltd Semiconductor device and manufacturing method therefor
KR101292594B1 (en) * 2010-07-02 2013-08-12 엘지이노텍 주식회사 Embedded printed circuit board with metal dam and method for manufacturing the same
CN103378269B (en) * 2012-04-23 2017-03-01 日亚化学工业株式会社 Light-emitting device
CN103378269A (en) * 2012-04-23 2013-10-30 日亚化学工业株式会社 Light emitting device
JP2013246840A (en) * 2012-05-23 2013-12-09 Nhk Spring Co Ltd Wiring member of suspension for disk device and suspension for disk device
CN105576110B (en) * 2014-10-31 2018-04-13 首尔伟傲世有限公司 High-efficiency light-emitting device
CN105576110A (en) * 2014-10-31 2016-05-11 首尔伟傲世有限公司 High-efficiency light-emitting device
WO2019128118A1 (en) * 2017-12-26 2019-07-04 晶元光电股份有限公司 Light emitting device, and manufacturing method and display module thereof
US11641010B2 (en) 2017-12-26 2023-05-02 Epistar Corporation Light-emitting device, manufacturing method thereof and display module using the same
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JPWO2021200669A1 (en) * 2020-03-31 2021-10-07
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