JP2000216195A - Semiconductor device, and its manufacture, and adhesive used therein - Google Patents

Semiconductor device, and its manufacture, and adhesive used therein

Info

Publication number
JP2000216195A
JP2000216195A JP11014126A JP1412699A JP2000216195A JP 2000216195 A JP2000216195 A JP 2000216195A JP 11014126 A JP11014126 A JP 11014126A JP 1412699 A JP1412699 A JP 1412699A JP 2000216195 A JP2000216195 A JP 2000216195A
Authority
JP
Japan
Prior art keywords
semiconductor element
wiring board
electrode
semiconductor device
thermosetting resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11014126A
Other languages
Japanese (ja)
Inventor
Mitsunori Ishizaki
光範 石崎
Tsuneo Hamaguchi
恒夫 濱口
Kenji Toshida
賢二 利田
Yoichi Kitamura
洋一 北村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11014126A priority Critical patent/JP2000216195A/en
Publication of JP2000216195A publication Critical patent/JP2000216195A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H01L2224/29082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To facilitate the sealing with resin between a semiconductor element and a wiring board by materializing highly reliable flip chip connection between the semiconductor element of a fine electrode and a wiring board easily and at low cost. SOLUTION: The bump electrode 14 of a semiconductor element 12 and the electrode 16a on a wiring board 15 are pressure-welded and connected with each other, and they are fastened by the adhesive consisting of thermosetting resin 17 arranged between the wiring board 15 and the semiconductor element 12. At that time, a conductor layer 16 to serve as wiring including the electrode 16a on the wiring board 15 is so made as to be covered by the thermosetting resin 17, and the protection and the sealing by resin of the conductor layer 16 are performed by thermosetting resin 17.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】この発明は、半導体素子を高
密度に配線基板に実装した半導体装置に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which semiconductor elements are mounted on a wiring board at high density.

【０００２】[0002]

【従来の技術】配線基板上に半導体素子を搭載した半導
体装置において、電極数が多くて、電極間隔の狭い半導
体素子を配線基板に実装する従来の技術として、キャリ
アと呼ばれる配線基板の表面電極に、半導体素子上の突
起電極を直接接続するフリップチップ接続がある。この
フリップチップ接続は、半導体素子の実装に必要な面積
を最も小さくして配線基板との接続が可能である。ま
た、この様な半導体装置は他の部品と共に、さらにマザ
ーボードとなるプリント配線板に実装されて用いられる
が、配線基板の裏面に設けた電極を介してプリント配線
板に実装できるため、最も小さい面積でプリント配線板
に実装することができ、小型化、軽量化に適している。2. Description of the Related Art In a semiconductor device in which a semiconductor element is mounted on a wiring board, a conventional technique for mounting a semiconductor element having a large number of electrodes and a narrow gap between the electrodes on the wiring board is a technique of mounting a semiconductor element on a surface electrode of a wiring board called a carrier. And flip-chip connection for directly connecting protruding electrodes on a semiconductor element. This flip-chip connection can be connected to a wiring board with the smallest area required for mounting a semiconductor element. Further, such a semiconductor device is used by being mounted on a printed wiring board serving as a motherboard together with other components, and since the semiconductor device can be mounted on the printed wiring board via electrodes provided on the back surface of the wiring board, the semiconductor device has the smallest area. It can be mounted on a printed wiring board, and is suitable for miniaturization and weight reduction.

【０００３】図８は例えば、システムＬＳＩのパッケー
ジング技術，ＳＨＭ会誌，ｐｐ．３８−４３，Ｖｏｌ．
１４，Ｎｏ．２，１９９８．に記載された従来の半導体
装置の構造を示す断面図である。図において、１は半導
体素子、２は半導体素子１表面に形成された電極パッ
ド、３は電極パッド２上に形成された突起電極となるは
んだバンプ、４は絶縁性の繊維に樹脂を含浸させて構成
される配線基板、５は配線基板４表面に形成された配線
パターン、５ａは配線パターン５の一部であり、半導体
素子１のはんだバンプ３と相対する位置に配設される電
極、６は配線基板４上に配線パターン５を覆う様に形成
されたレジスト膜、７は半導体素子１と配線基板４間を
封止する封止樹脂、８は配線基板４裏面に形成された電
極、９は電極８上に形成され、マザーボードとなるプリ
ント配線板（図示せず）との接続用のはんだバンプ、１
０は配線基板４表裏の電極５ａ、８間を接続するための
バイアホール、１１は配線基板４裏面に形成されたレジ
スト膜である。FIG. 8 shows, for example, a packaging technology of a system LSI, SHM Journal, pp. 147-143. 38-43, Vol.
14, No. 2, 1998. 1 is a cross-sectional view showing a structure of a conventional semiconductor device described in FIG. In the drawing, 1 is a semiconductor element, 2 is an electrode pad formed on the surface of the semiconductor element 1, 3 is a solder bump serving as a protruding electrode formed on the electrode pad 2, and 4 is an insulating fiber impregnated with resin. The wiring board 5 is a wiring pattern formed on the surface of the wiring board 4, 5 a is a part of the wiring pattern 5, and electrodes 6 are disposed at positions opposed to the solder bumps 3 of the semiconductor element 1. A resist film formed on the wiring board 4 so as to cover the wiring pattern 5; 7, a sealing resin for sealing between the semiconductor element 1 and the wiring board 4; 8, an electrode formed on the back surface of the wiring board 4; Solder bumps formed on electrodes 8 for connection to a printed wiring board (not shown) serving as a motherboard,
Reference numeral 0 denotes a via hole for connecting the electrodes 5a and 8 on the front and back of the wiring board 4, and reference numeral 11 denotes a resist film formed on the back of the wiring board 4.

【０００４】この様に構成される半導体装置の製造方法
を以下に示す。まず、半導体素子１の電極２上にはんだ
バンプ３を蒸着等により形成する。予め表裏に電極５
ａ、８および配線パターン５が形成された配線基板４上
の全面にレジスト膜６を形成した後、このレジスト膜６
を写真製版技術を用いてパターンニングして、電極５ａ
部分を開口する。また、配線基板４裏面にも同様にレジ
スト膜１１を形成しパターニングして電極８部分を開口
する。次に、半導体素子１のはんだバンプ３と配線基板
４上の電極５ａとの位置あわせを行った後、加熱した半
導体素子１を配線基板４に押しつけて、はんだを溶融す
ることによって、半導体素子１と配線基板４との電気的
接続を行う。次に、機械的強度をあげるため、半導体素
子１と配線基板４との間に樹脂７を注入した後、硬化さ
せて樹脂封止する。この後、レジスト膜１１から突出す
るように電極８上にはんだバンプ９を形成する。[0004] A method of manufacturing a semiconductor device having such a configuration will be described below. First, the solder bumps 3 are formed on the electrodes 2 of the semiconductor element 1 by vapor deposition or the like. Before and after the electrode 5
After forming a resist film 6 on the entire surface of the wiring substrate 4 on which the wiring patterns 5 and 8 are formed, the resist film 6 is formed.
Is patterned using a photoengraving technique to form an electrode 5a.
Open the part. Similarly, a resist film 11 is formed on the rear surface of the wiring substrate 4 and patterned to open the electrode 8 portion. Next, after the solder bumps 3 of the semiconductor element 1 are aligned with the electrodes 5a on the wiring board 4, the heated semiconductor element 1 is pressed against the wiring board 4, and the solder is melted. And the wiring board 4 are electrically connected. Next, in order to increase the mechanical strength, a resin 7 is injected between the semiconductor element 1 and the wiring board 4 and then cured to seal the resin. Thereafter, solder bumps 9 are formed on the electrodes 8 so as to protrude from the resist film 11.

【０００５】[0005]

【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されており、配線基板４上には配線パタ
ーン５を覆うレジスト膜６が、電極５ａ部分のみ開口さ
れて形成される（例えば、M.Mizutani, et al:"A Study
of a New Flip Chip Packaging Process for Diversif
ied Bump and Land Combination",,Proceedings of 199
8Electronic Components and Technology Conference,p
p316-319.を参照）。このため、半導体素子１のはんだ
バンプ３と電極５ａとの接続の際、はみ出したはんだが
隣接の電極５ａに接触したり、溶融時にはんだがぬれ拡
がるのが防止でき、短絡が防止され信頼性の高い接続が
行える。また、レジスト膜６が微細な配線パターン５を
覆って外部から保護することにより、配線パターン５の
マイグレーションを防止する効果も有する。しかしなが
ら、この様なレジスト膜６を形成するには、例えば１０
０μｍ程度の微細パターンである電極５ａ部分のみ開口
するように、レジスト膜６をパターニングする必要があ
り、高精度の写真製版技術が必要であるため、製造コス
トが高くなる。また、半導体素子１と配線基板４との隙
間が、このレジスト膜６の形成により小さくなり、この
隙間に樹脂封止のための樹脂７を信頼性良く注入するの
が困難になるという問題点があった。The conventional semiconductor device is configured as described above, and a resist film 6 covering a wiring pattern 5 is formed on a wiring substrate 4 with only an electrode 5a opened. For example, M. Mizutani, et al: "A Study
of a New Flip Chip Packaging Process for Diversif
ied Bump and Land Combination ",, Proceedings of 199
8Electronic Components and Technology Conference, p
p. 316-319.). Therefore, when the solder bump 3 of the semiconductor element 1 is connected to the electrode 5a, it is possible to prevent the protruding solder from contacting the adjacent electrode 5a or to prevent the solder from spreading when it is melted. High connection can be made. Further, since the resist film 6 covers the fine wiring pattern 5 and protects it from the outside, there is also an effect of preventing migration of the wiring pattern 5. However, in order to form such a resist film 6, for example, 10
It is necessary to pattern the resist film 6 so as to open only the electrode 5a, which is a fine pattern of about 0 μm, and a high-precision photolithography technique is required, so that the manufacturing cost is increased. Further, the gap between the semiconductor element 1 and the wiring board 4 is reduced by the formation of the resist film 6, and it becomes difficult to reliably inject the resin 7 for resin sealing into the gap. there were.

【０００６】この発明は、上記のような問題点を解消す
るために成されたものであって、微細電極の半導体素子
と配線基板とが信頼性良く容易にフリップチップ接続で
き、半導体素子と配線基板との間の樹脂封止が容易で、
信頼性が高く低コストな半導体装置を得ることを目的と
する。SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is possible to easily and reliably connect a semiconductor element having fine electrodes to a wiring board with a flip chip, and to connect a semiconductor element with a wiring. Easy resin sealing between the board and
An object is to obtain a highly reliable and low-cost semiconductor device.

【０００７】[0007]

【課題を解決するための手段】この発明に係わる請求項
１記載の半導体装置は、突起電極を有する半導体素子
と、絶縁性の繊維に樹脂を含浸させて構成し、表面に上
記突起電極に相対する電極を含む導体層を配設した配線
基板とを、上記突起電極と上記電極とを圧接して接続
し、上記配線基板と上記半導体素子との間に介在した熱
硬化性樹脂から成る接着剤により固着された構成であっ
て、上記導体層の表面が上記熱硬化性樹脂により覆われ
て、露出しないものである。According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor element having a protruding electrode; and an insulating fiber impregnated with a resin. An adhesive made of a thermosetting resin interposed between the wiring substrate and the semiconductor element, by connecting the wiring substrate provided with the conductor layer including the electrode to be pressed to the protruding electrode and the electrode. The surface of the conductor layer is covered with the thermosetting resin and is not exposed.

【０００８】またこの発明に係わる請求項２記載の半導
体装置は、表面に電極を有する半導体素子と、絶縁性の
繊維に樹脂を含浸させて構成し、表面に上記電極に相対
する突起電極および該突起電極に接続する導体層を配設
した配線基板とを、上記電極と上記突起電極とを圧接し
て接続し、上記配線基板と上記半導体素子との間に介在
した熱硬化性樹脂から成る接着剤により固着された構成
であって、上記導体層の表面が上記熱硬化性樹脂により
覆われて、露出しないものである。According to a second aspect of the present invention, there is provided a semiconductor device having a semiconductor element having an electrode on a surface thereof, an insulating fiber impregnated with a resin, and a projecting electrode opposed to the electrode on the surface, and A wiring board provided with a conductor layer connected to the protruding electrode is connected by press-contacting the electrode and the protruding electrode, and is made of a thermosetting resin interposed between the wiring board and the semiconductor element. The conductor layer is covered with the thermosetting resin and is not exposed.

【０００９】またこの発明に係わる請求項３記載の半導
体装置は、請求項１または２において、導体層が形成さ
れた配線基板の周辺部領域の表面をレジスト膜で覆い、
該レジスト膜の開口部内に半導体素子を配置し、上記配
線基板と上記半導体素子との間に介在する熱硬化性樹脂
が上記レジスト膜上に渡って延在するものである。According to a third aspect of the present invention, there is provided the semiconductor device according to the first or second aspect, wherein a surface of a peripheral region of the wiring board on which the conductor layer is formed is covered with a resist film,
A semiconductor element is arranged in an opening of the resist film, and a thermosetting resin interposed between the wiring substrate and the semiconductor element extends over the resist film.

【００１０】またこの発明に係わる請求項４記載の半導
体装置は、請求項１〜３のいずれかにおいて、配線基板
の厚さが約０．０５〜０．１ｍｍ程度であるものであ
る。According to a fourth aspect of the present invention, there is provided the semiconductor device according to any one of the first to third aspects, wherein the thickness of the wiring board is about 0.05 to 0.1 mm.

【００１１】またこの発明に係わる請求項５記載の半導
体装置は、請求項１〜４のいずれかにおいて、熱硬化性
樹脂が、樹脂中に絶縁性粒子を含有したものである。According to a fifth aspect of the present invention, there is provided a semiconductor device according to any one of the first to fourth aspects, wherein the thermosetting resin contains insulating particles in the resin.

【００１２】またこの発明に係わる請求項６記載の半導
体装置の製造方法は、請求項１〜５のいずれかに記載の
半導体装置の製造方法であって、配線基板上に、熱硬化
性樹脂から成る接着剤となるフィルム状の熱硬化シート
をＢステージ状態にて配置し、上記配線基板および半導
体素子の電極と突起電極とが相対した状態で、上記半導
体素子を上記配線基板に押しつけ、上記配線基板表面に
配設された導体層表面を加熱により溶融された上記熱硬
化性樹脂で覆った後、該熱硬化性樹脂を硬化させるもの
である。According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to any one of the first to fifth aspects, wherein a thermosetting resin is formed on the wiring substrate. A film-like thermosetting sheet as an adhesive is placed in a B-stage state, and the semiconductor element is pressed against the wiring board in a state where the electrodes of the wiring board and the semiconductor element are opposed to the projecting electrodes, and the wiring is formed. After covering the surface of the conductor layer provided on the substrate surface with the thermosetting resin melted by heating, the thermosetting resin is cured.

【００１３】またこの発明に係わる請求項７記載の半導
体装置の製造方法は、請求項１記載の半導体装置の製造
方法であって、配線基板上に、絶縁性粒子を含有する層
と含有しない層との２層構成であり熱硬化性樹脂から成
る接着剤となるフィルム状の熱硬化シートを、上記絶縁
性粒子を含有しない層を下方にしてＢステージ状態にて
配置し、上記配線基板の電極と半導体素子の突起電極と
が相対した状態で、上記半導体素子を上記配線基板に押
しつけ、上記配線基板表面に配設された導体層表面を加
熱により溶融された上記熱硬化性樹脂で覆った後、該熱
硬化性樹脂を硬化させるものである。According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first aspect, wherein a layer containing insulating particles and a layer containing no insulating particles are formed on the wiring board. And a film-like thermosetting sheet serving as an adhesive made of a thermosetting resin is disposed in a B-stage state with the layer not containing the insulating particles downward, and the electrode of the wiring board is formed. After the semiconductor element is pressed against the wiring board with the protruding electrodes of the semiconductor element facing each other, and after covering the surface of the conductor layer disposed on the wiring board surface with the thermosetting resin melted by heating, And to cure the thermosetting resin.

【００１４】またこの発明に係わる請求項８記載の半導
体装置の製造方法は、請求項２記載の半導体装置の製造
方法であって、配線基板上に、絶縁性粒子を含有する層
と含有しない層との２層構成であり熱硬化性樹脂から成
る接着剤となるフィルム状の熱硬化シートを、上記絶縁
性粒子を含有する層を下方にしてＢステージ状態にて配
置し、上記配線基板の突起電極と半導体素子の電極とが
相対した状態で、上記半導体素子を上記配線基板に押し
つけ、上記配線基板表面に配設された導体層表面を加熱
により溶融された上記熱硬化性樹脂で覆った後、該熱硬
化性樹脂を硬化させるものである。According to a eighth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the second aspect, wherein the layer containing insulating particles and the layer not containing the insulating particles are formed on the wiring board. And a film-like thermosetting sheet serving as an adhesive made of a thermosetting resin is disposed in a B-stage state with the layer containing the insulating particles downward, and the protrusion of the wiring board is formed. After the semiconductor element is pressed against the wiring board in a state where the electrode and the electrode of the semiconductor element are opposed to each other, after covering the surface of the conductor layer disposed on the wiring board surface with the thermosetting resin melted by heating. And to cure the thermosetting resin.

【００１５】またこの発明に係わる請求項９記載の半導
体装置の製造方法に用いる接着剤は、熱硬化性樹脂から
成り、絶縁性粒子を含有する層と含有しない層との２層
構造のフィルム状熱硬化シートで構成されたものであ
る。The adhesive used in the method of manufacturing a semiconductor device according to the ninth aspect of the present invention is made of a thermosetting resin, and has a two-layer film structure including a layer containing insulating particles and a layer not containing the insulating particles. It is composed of a thermosetting sheet.

【００１６】[0016]

【発明の実施の形態】実施の形態１．以下、この発明の
実施の形態を図について説明する。図１は、この発明の
実施の形態１による半導体装置の構造を示す断面図であ
る。図において、１２は半導体素子、１３は半導体素子
１２表面に形成された電極、１４は電極１３上に形成さ
れた突起電極、１５は絶縁性の繊維に樹脂を含浸させて
構成される配線基板、１６は配線基板１５表面に形成さ
れた配線パターンとなる導体層、１６ａは導体層１６の
一部であり、半導体素子１２の突起電極１４と相対する
位置に配設される電極、１７は半導体素子１２と配線基
板１５との間に、配線基板１５上の導体層１６全体が覆
われるよう配された熱硬化性樹脂から成る接着剤（以
下、熱硬化性接着剤１７と称す）、１７ａは熱硬化性接
着剤１７のフィレット、１８は配線基板１５裏面に形成
された電極、１９は電極１８上に形成され、マザーボー
ドとなるプリント配線板（図示せず）との接続用のはん
だバンプ、２０は配線基板１５表裏の電極１６ａ、１８
間を接続するためのバイアホール、２１は配線基板１５
裏面に、電極１８部分のみ開口して形成されたレジスト
膜である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention. In the figure, 12 is a semiconductor element, 13 is an electrode formed on the surface of the semiconductor element 12, 14 is a protruding electrode formed on the electrode 13, 15 is a wiring board formed by impregnating an insulating fiber with a resin, Reference numeral 16 denotes a conductor layer serving as a wiring pattern formed on the surface of the wiring board 15, 16 a denotes a part of the conductor layer 16, an electrode provided at a position facing the protruding electrode 14 of the semiconductor element 12, and 17 denotes a semiconductor element An adhesive (hereinafter, referred to as a thermosetting adhesive 17) made of a thermosetting resin disposed between the wiring board 12 and the wiring board 15 so as to cover the entire conductor layer 16 on the wiring board 15; A fillet of the curable adhesive 17, an electrode 18 formed on the back surface of the wiring board 15, a solder bump 19 formed on the electrode 18 for connection with a printed wiring board (not shown) serving as a motherboard, and 20. Wiring base 15 front and back electrodes 16a, 18
Via holes for connection between the wiring boards 21
This is a resist film formed on the back surface with an opening only at the electrode 18.

【００１７】上記の様な半導体装置における半導体素子
１２と配線板３の接続方法を以下に示す。まず、半導体
素子１２上の例えばアルミから成る電極１３上に、金、
ニッケルまたは銅などの金属材料で、厚さ約３０μｍ程
度の突起電極１４を形成する。予め表裏に電極１６ａ、
１８および導体層１６が形成された配線基板１５上に、
例えば熱硬化型のエポキシ樹脂などから成る熱硬化性接
着剤１７を配置する。このとき、配線基板１５上の導体
層１６が、接続完了時にその全面が熱硬化性接着剤１７
により覆われるように、熱硬化性接着剤１７を半導体素
子１２の大きさよりも大きく配置する。次に、半導体素
子１２を例えば、２００℃程度に加熱しておき、半導体
素子１２の突起電極１４と配線基板１５の電極１６ａと
の位置合わせをしながら、半導体素子１２を配線基板１
５に押し当てる。このとき、熱硬化性接着剤１７は半導
体素子１２の端面に沿って這い上がると共に横方向にも
拡がりフィレット１７ａを形成する。この突起電極１４
と電極１６ａとが接触した状態で熱硬化性接着剤１７を
硬化させ、半導体素子１２を室温程度まで冷却する。こ
れにより、熱硬化性接着材１７と突起電極１４との線膨
張係数差に起因して突起電極１４と電極１６ａとに圧縮
力が働き、突起電極１４と電極１６ａとの電気的接続が
安定して維持できる。A method for connecting the semiconductor element 12 and the wiring board 3 in the above semiconductor device will be described below. First, gold, for example, on the electrode 13 made of aluminum on the semiconductor element 12,
The protruding electrode 14 having a thickness of about 30 μm is formed of a metal material such as nickel or copper. Before and after the electrodes 16a,
On the wiring board 15 on which the conductor layers 18 and 18 are formed,
For example, a thermosetting adhesive 17 made of a thermosetting epoxy resin or the like is provided. At this time, when the connection is completed, the entire surface of the conductor layer 16 on the wiring board 15 is covered with the thermosetting adhesive 17.
The thermosetting adhesive 17 is arranged to be larger than the size of the semiconductor element 12 so as to be covered by. Next, the semiconductor element 12 is heated to, for example, about 200 ° C., and the semiconductor element 12 is placed on the wiring board 1 while the projection electrode 14 of the semiconductor element 12 is aligned with the electrode 16 a of the wiring board 15.
Press on 5. At this time, the thermosetting adhesive 17 creeps up along the end face of the semiconductor element 12 and also spreads laterally to form a fillet 17a. This protruding electrode 14
The thermosetting adhesive 17 is cured in a state where the semiconductor device 12 and the electrode 16a are in contact with each other, and the semiconductor element 12 is cooled to about room temperature. Thereby, a compressive force acts on the protruding electrode 14 and the electrode 16a due to a difference in linear expansion coefficient between the thermosetting adhesive 17 and the protruding electrode 14, and the electrical connection between the protruding electrode 14 and the electrode 16a is stabilized. Can be maintained.

【００１８】この実施の形態では、半導体素子１２の突
起電極１４と配線基板１５の電極１６ａとは、圧接され
てそれらを覆う熱硬化性接着剤１７により固着される。
このため、従来のもののように、はんだなどの接合剤の
はみ出しやぬれ拡がり等の問題がなく、そのために従来
形成されていたレジスト膜６の形成の必要が無い。ま
た、熱硬化性接着剤１７は配線基板１５の導体層１６全
体を覆うように形成されるため、微細な配線パターンを
有する導体層１６を覆って外部から保護し、配線のマイ
グレーションを防止する効果も有する。さらに、この熱
硬化性接着剤１７により半導体素子１２と配線基板１５
との間の樹脂封止も為されている。この様に、従来高精
度の写真製版技術を用いて形成されていたレジスト膜６
が不要となり、熱硬化性接着剤１７により、半導体素子
１２の突起電極１４と配線基板１５の電極１６ａとの接
続、微細な配線パターンを有する導体層１６の保護、お
よび樹脂封止を行うことができ、低コストで容易に信頼
性の高い半導体装置が得られる。In this embodiment, the protruding electrode 14 of the semiconductor element 12 and the electrode 16a of the wiring board 15 are pressed and fixed by a thermosetting adhesive 17 covering them.
Therefore, there is no problem such as the protrusion of the bonding agent such as solder or the spread of the wetting unlike the conventional one, and therefore, it is not necessary to form the conventionally formed resist film 6. Further, since the thermosetting adhesive 17 is formed so as to cover the entire conductor layer 16 of the wiring board 15, the thermosetting adhesive 17 covers the conductor layer 16 having a fine wiring pattern, protects it from the outside, and prevents the migration of the wiring. Also have. Further, the semiconductor element 12 and the wiring board 15 are bonded by the thermosetting adhesive 17.
Is also performed between them. As described above, the resist film 6 conventionally formed using the high-precision photolithography technology is used.
The connection between the protruding electrodes 14 of the semiconductor element 12 and the electrodes 16a of the wiring board 15, the protection of the conductor layer 16 having a fine wiring pattern, and the resin sealing are performed by the thermosetting adhesive 17. Thus, a highly reliable semiconductor device can be easily obtained at low cost.

【００１９】なお、図１に示した半導体装置は、半導体
素子１２と熱硬化性接着剤１７と配線基板１５とで構成
されているが、それぞれの線膨張係数が異なることか
ら、半導体素子１２の裏面が凸状態に反る。通常、熱硬
化性接着剤１７の線膨張係数は、半導体素子１２の線膨
張係数の１０倍、配線基板１５の線膨張係数の５倍程度
である。上記の様な反りが大きいと、はんだバンプ１９
を用いてプリント配線板に実装する際に、確実に接続す
ることが困難であった。配線基板１５の厚さが０．１ｍ
ｍ以下で反りを小さくできることが、数値計算により確
認された。また、配線基板１５の厚さは０．０５ｍｍ以
上でなければ、薄すぎて使用に耐えないものである。こ
のため、配線基板１５の厚さを０．０５〜０．１ｍｍ程
度とすることにより、反りが低減できて、プリント配線
板に確実に実装できる信頼性の高い半導体装置が得られ
る。Although the semiconductor device shown in FIG. 1 is composed of the semiconductor element 12, the thermosetting adhesive 17, and the wiring board 15, their respective coefficients of linear expansion are different. The back surface warps to a convex state. Normally, the linear expansion coefficient of the thermosetting adhesive 17 is about 10 times the linear expansion coefficient of the semiconductor element 12 and about 5 times the linear expansion coefficient of the wiring board 15. If the warpage is large as described above, the solder bump 19
When mounting on a printed wiring board by using, it is difficult to make a reliable connection. The thickness of the wiring board 15 is 0.1 m
It has been confirmed by numerical calculation that the warpage can be reduced below m. If the thickness of the wiring board 15 is not more than 0.05 mm, it is too thin to withstand use. For this reason, by setting the thickness of the wiring board 15 to about 0.05 to 0.1 mm, a warp can be reduced and a highly reliable semiconductor device that can be reliably mounted on a printed wiring board can be obtained.

【００２０】実施の形態２．次に、この発明の実施の形
態２による半導体装置について説明する。図２はこの発
明の実施の形態２による半導体装置の構造を示す断面図
である。なお、この実施の形態以降、配線基板１５の裏
面側の電極１８、はんだバンプ１９、レジスト膜２１お
よびバイアホール２０の図示および説明は便宜上省略す
る。図２に示すように、導体層１６が形成された配線基
板１５の周辺部領域の表面をレジスト膜２２で覆う。こ
のレジスト膜２２の開口部内に半導体素子１２を配置
し、上記実施の形態１と同様に、熱硬化性接着剤１７に
よって半導体素子１２の突起電極１４と配線基板１５の
電極１６ａとを接続して固着する。このとき、加熱によ
り溶融した熱硬化性接着剤１７が、半導体素子１２端面
からレジスト膜２２上に渡ってフィレット１７ａを形成
するように構成する。例えば、フィレット１７ａの横方
向の寸法が、半導体素子１２端面から０．４ｍｍ程度で
あるとき、半導体素子１２の端面から０．３ｍｍ程度離
間させてレジスト膜２２パターンを形成すると効果的で
ある。Embodiment 2 Next, a semiconductor device according to a second embodiment of the present invention will be described. FIG. 2 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention. Note that, from this embodiment, illustration and description of the electrodes 18, the solder bumps 19, the resist film 21, and the via holes 20 on the back surface side of the wiring board 15 are omitted for convenience. As shown in FIG. 2, the surface of the peripheral region of the wiring board 15 on which the conductor layer 16 is formed is covered with a resist film 22. The semiconductor element 12 is arranged in the opening of the resist film 22, and the protruding electrode 14 of the semiconductor element 12 is connected to the electrode 16a of the wiring board 15 by the thermosetting adhesive 17 as in the first embodiment. Stick. At this time, the thermosetting adhesive 17 melted by heating forms a fillet 17a from the end face of the semiconductor element 12 onto the resist film 22. For example, when the lateral dimension of the fillet 17a is about 0.4 mm from the end face of the semiconductor element 12, it is effective to form the resist film 22 pattern at a distance of about 0.3 mm from the end face of the semiconductor element 12.

【００２１】この実施の形態では、レジスト膜２２を配
線基板１５の周辺部領域の表面を覆うように形成し、配
線基板１５と半導体素子１２との間に介在する熱硬化性
接着剤１７をレジスト膜２２上に渡って延在するように
形成した。これにより、導体層１６は、配線基板１５の
周辺部領域ではレジスト膜２２に、それ以外の領域では
熱硬化性接着剤１７に覆われ、実施の形態１と同様に、
微細な配線が外部から保護され、配線のマイグレーショ
ンが防止できる。また、この様なレジスト膜２２は、半
導体素子１２よりも大きな開口部を持つもので、微細な
加工を必要とせず容易に形成できる。この様に、レジス
ト膜２２を配線基板１５の周辺部領域にのみ形成するこ
とにより、配線基板１５が大きく熱硬化性接着剤１７で
配線基板１５の周辺部領域まで覆うことが困難な場合に
も、容易に導体層１６を覆う構造が実現でき、上記実施
の形態１と同様に、低コストで容易に信頼性の高い半導
体装置が得られる。In this embodiment, the resist film 22 is formed so as to cover the surface of the peripheral region of the wiring board 15, and the thermosetting adhesive 17 interposed between the wiring board 15 and the semiconductor element 12 is resist-coated. It was formed to extend over the film 22. As a result, the conductor layer 16 is covered with the resist film 22 in the peripheral region of the wiring board 15 and covered with the thermosetting adhesive 17 in the other regions, as in the first embodiment.
Fine wiring is protected from the outside, and migration of wiring can be prevented. Further, such a resist film 22 has an opening larger than that of the semiconductor element 12, and can be easily formed without requiring fine processing. By forming the resist film 22 only in the peripheral region of the wiring substrate 15 in this manner, even when the wiring substrate 15 is large and it is difficult to cover the peripheral region of the wiring substrate 15 with the thermosetting adhesive 17. Thus, a structure that easily covers the conductor layer 16 can be realized, and a highly reliable semiconductor device can be easily obtained at low cost as in the first embodiment.

【００２２】実施の形態３．次に、この発明の実施の形
態３による半導体装置について説明する。図３はこの実
施の形態３による半導体装置の構造を示す断面図であ
る。上記実施の形態１および２では、半導体素子１２側
に突起電極１４を形成したが、この実施の形態では、配
線基板１５の電極１６ａ上に突起電極２３を形成する。
また半導体素子１２と配線基板１５との接続方法は、上
記実施の形態２と同様に、配線基板１５の周辺部領域の
表面をレジスト膜２２で覆い、配線基板１５上に熱硬化
性接着剤１７を配置した後、加熱した半導体素子１２
を、半導体素子１２の電極１３と配線基板１５の突起電
極２３との位置合わせをしながら、配線基板１５に押し
当てる。このとき、熱硬化性接着剤１７は半導体素子１
２端面からレジスト膜２２上に渡ってフィレット１７ａ
を形成する。この突起電極２３と電極１３とが接触した
状態で熱硬化性接着剤１７を硬化させ、半導体素子１２
を室温程度まで冷却する。Embodiment 3 FIG. Next, a semiconductor device according to a third embodiment of the present invention will be described. FIG. 3 is a sectional view showing the structure of the semiconductor device according to the third embodiment. In the first and second embodiments, the protruding electrode 14 is formed on the semiconductor element 12 side. In this embodiment, the protruding electrode 23 is formed on the electrode 16 a of the wiring board 15.
The connection between the semiconductor element 12 and the wiring board 15 is performed by covering the surface of the peripheral area of the wiring board 15 with the resist film 22 and placing the thermosetting adhesive 17 on the wiring board 15 as in the second embodiment. Is placed and then heated semiconductor element 12
Is pressed against the wiring board 15 while aligning the electrodes 13 of the semiconductor element 12 with the protruding electrodes 23 of the wiring board 15. At this time, the thermosetting adhesive 17 is
Fillet 17a extending from two end faces onto resist film 22
To form The thermosetting adhesive 17 is cured while the protruding electrode 23 and the electrode 13 are in contact with each other, and the semiconductor element 12 is cured.
Is cooled to about room temperature.

【００２３】この実施の形態では、上記実施の形態２と
同様の効果が得られると共に、突起電極２３を半導体素
子１２よりも安価な配線基板１５側に形成することによ
り、突起電極形成不良からくるロスが低減でき、さらに
低コストの半導体装置が得られる。なお、この実施の形
態は、レジスト膜２２を形成しない上記実施の形態１に
も適用でき、同様の効果が得られる。In this embodiment, the same effect as that of the second embodiment can be obtained, and the formation of the bump electrode 23 on the wiring board 15 side, which is less expensive than the semiconductor element 12, causes a bump electrode formation defect. Loss can be reduced, and a low-cost semiconductor device can be obtained. This embodiment can be applied to the first embodiment in which the resist film 22 is not formed, and the same effect can be obtained.

【００２４】実施の形態４．次に、この発明の実施の形
態４による半導体装置について説明する。図４はこの実
施の形態４による半導体装置の構造を示す断面図であ
る。この実施の形態では、図２で示した上記実施の形態
２による半導体装置において、熱硬化性接着剤１７に、
例えばシリカなどの絶縁性の粒子２４を含有するものを
用いる。上述したように、熱硬化性接着剤１７の線膨張
係数は、半導体素子１２の線膨張係数の１０倍、配線基
板１５の線膨張係数の５倍程度であり、半導体素子１２
と熱硬化性接着剤１７との界面または熱硬化性接着剤１
７と配線基板１５との界面には大きなせん断応力が発生
するものである。熱硬化性接着剤１７に絶縁性粒子２４
を含有させることにより、熱硬化性接着剤１７の線膨張
係数を低減させ、熱硬化性接着剤１７と半導体素子１２
および配線基板１５との界面のせん断応力が低減でき、
ヒートサイクル試験などに強く、信頼性の向上した半導
体装置が得られる。なお、この様な、絶縁性粒子２４を
含有した熱硬化性接着剤１７は、上記実施の形態１およ
び３にも同様に適用でき、同様の効果が得られる。Embodiment 4 Next, a semiconductor device according to a fourth embodiment of the present invention will be described. FIG. 4 is a sectional view showing the structure of the semiconductor device according to the fourth embodiment. In this embodiment, in the semiconductor device according to the second embodiment shown in FIG.
For example, a material containing insulating particles 24 such as silica is used. As described above, the linear expansion coefficient of the thermosetting adhesive 17 is about 10 times the linear expansion coefficient of the semiconductor element 12 and about 5 times the linear expansion coefficient of the wiring board 15.
Interface between thermosetting adhesive 17 and thermosetting adhesive 1 or thermosetting adhesive 1
A large shear stress is generated at the interface between the wiring board 7 and the wiring board 15. The insulating particles 24 are applied to the thermosetting adhesive 17.
, The coefficient of linear expansion of the thermosetting adhesive 17 is reduced, and the thermosetting adhesive 17 and the semiconductor element 12
And the shear stress at the interface with the wiring board 15 can be reduced,
A semiconductor device which is strong in a heat cycle test and the like and has improved reliability can be obtained. In addition, such a thermosetting adhesive 17 containing the insulating particles 24 can be similarly applied to the first and third embodiments, and the same effect can be obtained.

【００２５】実施の形態５．次に、この発明の実施の形
態５による半導体装置の製造方法について説明する。図
５はこの実施の形態５による半導体装置の製造方法を示
す断面図である。まず、半導体素子１２の電極１３上に
突起電極１４を形成する。突起電極１４の材料は、金、
銅、ニッケルなどであり、形成方法はめっき、ボールボ
ンダを用いる。ボールボンダによる方法は、金属線の先
端を放電により球状にして、それを半導体素子１２の電
極１３上に、熱と超音波振動により接合した後、金属線
を切断することによって行う。従って、ボールボンダに
よる突起電極１４の形成方法は、市販の半導体素子１２
を購入して行うことも容易である。次に、周辺部領域に
レジスト膜２２が形成された配線基板１５上に熱硬化性
接着剤１７となるフィルム状熱硬化シートとしての接着
フィルム１７ｂをＢステージ状態にて配置する（図５
（ａ））。Embodiment 5 FIG. Next, a method for manufacturing a semiconductor device according to the fifth embodiment of the present invention will be described. FIG. 5 is a sectional view showing a method for manufacturing a semiconductor device according to the fifth embodiment. First, the protruding electrode 14 is formed on the electrode 13 of the semiconductor element 12. The material of the protruding electrode 14 is gold,
It is made of copper, nickel, or the like, and is formed by plating or a ball bonder. The method using a ball bonder is performed by forming the tip of a metal wire into a sphere by electric discharge, joining it to the electrode 13 of the semiconductor element 12 by heat and ultrasonic vibration, and then cutting the metal wire. Therefore, the method of forming the protruding electrode 14 by the ball bonder is based on the commercially available semiconductor element 12.
It is also easy to buy and do. Next, an adhesive film 17b as a film-like thermosetting sheet serving as the thermosetting adhesive 17 is arranged in a B-stage state on the wiring board 15 on which the resist film 22 is formed in the peripheral region (FIG. 5).
(A)).

【００２６】次に、突起電極１４の形成された半導体素
子１２を例えば、２００℃に加熱してレジスト膜２２の
開口部内に配置し、突起電極１４と配線基板１５の電極
１６ａとの位置合わせをしながら、接着フィルム１７ｂ
を介して、荷重を加えて半導体素子１２を配線基板１５
に押し当てる。このとき熱硬化性接着剤１７（接着フィ
ルム１７ｂ）は加熱により溶融して、半導体素子１２の
端面からレジスト膜２２上に渡って延在し、露出した導
体層１６を覆う。この後、熱硬化性接着剤１７を半導体
素子１２の熱で硬化させ、冷却して半導体素子１２と配
線基板１５とが接続された半導体装置を得る（図５
（ｂ））。Next, the semiconductor element 12 on which the protruding electrodes 14 are formed is heated, for example, to 200 ° C., and is disposed in the opening of the resist film 22 so as to align the protruding electrodes 14 with the electrodes 16 a of the wiring board 15. While the adhesive film 17b
Is applied to the semiconductor element 12 to apply a load to the wiring board 15.
Press against. At this time, the thermosetting adhesive 17 (adhesive film 17b) is melted by heating, extends from the end surface of the semiconductor element 12 over the resist film 22, and covers the exposed conductor layer 16. Thereafter, the thermosetting adhesive 17 is cured by the heat of the semiconductor element 12 and cooled to obtain a semiconductor device in which the semiconductor element 12 and the wiring board 15 are connected (FIG. 5).
(B)).

【００２７】この実施の形態では、熱硬化性接着剤１７
にＢステージ状態の接着フィルム１７ｂを用いる。配線
基板１５上に熱硬化性接着剤１７を配置する際、フィル
ム状であるため、取り扱いが容易で半導体装置の製造が
容易になる。またこの接着フィルム１７ｂは、所定の温
度に加熱されることにより、一時的に液状となる特徴を
有し、半導体素子１２と配線基板１５との間にあるボイ
ドを効率よく排出することができるとともに、熱硬化に
要する時間が１０秒程度と極めて短く、他の液状の熱硬
化性接着剤と比べ硬化時間を約１／５に短縮することが
でき、生産性が向上する。In this embodiment, the thermosetting adhesive 17
The adhesive film 17b in the B-stage state is used. When the thermosetting adhesive 17 is arranged on the wiring board 15, since it is in the form of a film, it is easy to handle and the semiconductor device is easily manufactured. The adhesive film 17b has a characteristic that it temporarily becomes liquid when heated to a predetermined temperature, and can efficiently discharge voids between the semiconductor element 12 and the wiring board 15. The time required for heat curing is as short as about 10 seconds, and the curing time can be reduced to about 1/5 as compared with other liquid thermosetting adhesives, thereby improving the productivity.

【００２８】実施の形態６．次に、この発明の実施の形
態６による半導体装置の製造方法について説明する。図
６および図７は、この実施の形態６による半導体装置の
製造方法を示す断面図である。この実施の形態では、上
記実施の形態５による半導体装置の製造において、配線
基板１５上に熱硬化性接着剤１７を配置する際に用いる
Ｂステージ状態の接着フィルム１７ｂに、絶縁性粒子２
４を含有しない第１のフィルム層１７ｃと絶縁性粒子２
４を含有する第２のフィルム層１７ｄとの２層構成の接
着フィルム１７ｂを用いたものである。図６（ａ）に示
すように、突起電極２３が配線基板１５側に形成されて
いる場合には、配線基板１５上に配置する接着フィルム
１７ｂは、絶縁性粒子２４を含有する第２のフィルム層
１７ｄを下方にして配置する。一方、図７（ａ）に示す
ように、突起電極１４が半導体素子１２側に形成されて
いる場合には、配線基板１５上に配置する接着フィルム
１７ｂは、絶縁性粒子２４を含有しない第１のフィルム
層１７ｃを下方にして配置する。Embodiment 6 FIG. Next, a method of manufacturing a semiconductor device according to Embodiment 6 of the present invention will be described. 6 and 7 are sectional views showing a method for manufacturing a semiconductor device according to the sixth embodiment. In the present embodiment, in the manufacture of the semiconductor device according to the fifth embodiment, the insulating particles 2 are provided on the adhesive film 17b in the B-stage state used when the thermosetting adhesive 17 is disposed on the wiring board 15.
Film layer 17c containing no 4 and insulating particles 2
In this example, an adhesive film 17b having a two-layer structure with a second film layer 17d containing the film 4 is used. As shown in FIG. 6A, when the protruding electrode 23 is formed on the wiring board 15, the adhesive film 17 b disposed on the wiring board 15 is a second film containing the insulating particles 24. The layer 17d is arranged with the lower side. On the other hand, as shown in FIG. 7A, when the protruding electrode 14 is formed on the semiconductor element 12 side, the adhesive film 17 b disposed on the wiring substrate 15 has the first film 17 containing no insulating particles 24. Is placed with its film layer 17c facing down.

【００２９】この後、図６（ｂ）、図７（ｂ）に示すよ
うに、加熱した半導体素子１２を、突起電極１４（２
３）と電極１６ａ（１３）との位置合わせをしながら、
接着フィルム１７ｂを介して、荷重を加えて半導体素子
１２を配線基板１５に押し当てる。このとき熱硬化性接
着剤１７（接着フィルム１７ｂ）は加熱により溶融し
て、半導体素子１２の端面からレジスト膜２２上に渡っ
て延在し、露出した導体層１６を覆う。この後、熱硬化
性接着剤１７を半導体素子１２の熱で硬化させ、冷却し
て半導体素子１２と配線基板１５とが接続された半導体
装置を得る。After that, as shown in FIGS. 6B and 7B, the heated semiconductor element 12 is
3) While aligning the electrode 16a (13) with the electrode 16a (13),
The semiconductor element 12 is pressed against the wiring board 15 by applying a load via the adhesive film 17b. At this time, the thermosetting adhesive 17 (adhesive film 17b) is melted by heating, extends from the end surface of the semiconductor element 12 over the resist film 22, and covers the exposed conductor layer 16. Thereafter, the thermosetting adhesive 17 is cured by the heat of the semiconductor element 12 and cooled to obtain a semiconductor device in which the semiconductor element 12 and the wiring board 15 are connected.

【００３０】この実施の形態では、接着フィルム１７ｂ
を、絶縁性粒子２４を含有しない第１のフィルム層１７
ｃと絶縁性粒子２４を含有する第２のフィルム層１７ｄ
との２層構成とし、配線基板１５上に配置する際、突起
電極１４（２３）の先端側に絶縁性粒子２４を含有しな
い第１のフィルム層１７ｃが、根元側に絶縁性粒子２４
を含有する第２のフィルム層１７ｄが位置するように配
置する。このため、突起電極１４（２３）の先端部分と
電極１６ａ（１３）とが接触する際に、突起電極１４
（２３）の先端部分近傍には絶縁性粒子２４が殆どな
く、突起電極１４（２３）と電極１６ａ（１３）との間
に絶縁性粒子２４を挟み込んで接触不良となることが防
止できる。この様に、半導体素子１２と配線基板１５と
の良好で安定した電気的接続が得られるとともに、絶縁
性粒子２４により熱硬化性接着剤１７の線膨張係数を低
減させて、熱硬化性接着剤１７と半導体素子１２および
配線基板１５との界面のせん断応力が低減でき、半導体
装置の信頼性を向上することができる。In this embodiment, the adhesive film 17b
To the first film layer 17 containing no insulating particles 24.
c and second film layer 17d containing insulating particles 24
When disposed on the wiring board 15, the first film layer 17 c containing no insulating particles 24 is provided on the tip side of the bump electrode 14 (23), and the insulating particles 24 are provided on the base side.
Are arranged so that the second film layer 17d containing the slag is located. Therefore, when the tip portion of the protruding electrode 14 (23) comes into contact with the electrode 16a (13), the protruding electrode 14 (23)
There is hardly any insulating particles 24 near the tip of (23), and it is possible to prevent the insulating particles 24 from being sandwiched between the protruding electrodes 14 (23) and the electrodes 16a (13), resulting in poor contact. In this way, good and stable electrical connection between the semiconductor element 12 and the wiring board 15 can be obtained, and the linear expansion coefficient of the thermosetting adhesive 17 is reduced by the insulating particles 24, so that the thermosetting adhesive 17 The shear stress at the interface between the semiconductor device 17 and the semiconductor element 12 and the wiring substrate 15 can be reduced, and the reliability of the semiconductor device can be improved.

【００３１】なお、絶縁性粒子２４は、シリカの他、ア
ルミナなど、絶縁性を有し線膨張係数が接着フィルム１
７ｂを構成する樹脂よりも小さいものであれば良い。The insulating particles 24 are made of an insulating material, such as alumina, other than silica, having a linear expansion coefficient of 1.
What is necessary is just to be smaller than the resin which comprises 7b.

【００３２】また、２層構成の接着フィルム１７ｂは、
絶縁性粒子２４を含有しない第１のフィルム層１７ｃと
絶縁性粒子２４を含有する第２のフィルム層１７ｄとで
接着フィルム１７ｂが予め２層に構成されたものでも、
また、配線基板１５上に、第１のフィルム層１７ｃと第
２のフィルム層１７ｄとを順次積層して配置することに
より構成しても良い。The two-layer adhesive film 17b is
Even if the adhesive film 17b is configured in two layers in advance by the first film layer 17c not containing the insulating particles 24 and the second film layer 17d containing the insulating particles 24,
Further, the first film layer 17c and the second film layer 17d may be sequentially laminated and arranged on the wiring board 15.

【００３３】[0033]

【発明の効果】以上のように、この発明に係わる請求項
１記載の半導体装置は、突起電極を有する半導体素子
と、絶縁性の繊維に樹脂を含浸させて構成し、表面に上
記突起電極に相対する電極を含む導体層を配設した配線
基板とを、上記突起電極と上記電極とを圧接して接続
し、上記配線基板と上記半導体素子との間に介在した熱
硬化性樹脂から成る接着剤により固着された構成であっ
て、上記導体層の表面が上記熱硬化性樹脂により覆われ
て、露出しないため、低コストで容易に信頼性の高い半
導体装置が得られる。As described above, the semiconductor device according to the first aspect of the present invention comprises a semiconductor element having a protruding electrode and an insulating fiber impregnated with a resin. A wiring board provided with a conductor layer including opposing electrodes is connected by press-contacting the protruding electrodes and the electrodes, and is made of a thermosetting resin interposed between the wiring board and the semiconductor element. Since the surface of the conductor layer is covered with the thermosetting resin and is not exposed, a highly reliable semiconductor device can be easily obtained at low cost.

【００３４】またこの発明に係わる請求項２記載の半導
体装置は、表面に電極を有する半導体素子と、絶縁性の
繊維に樹脂を含浸させて構成し、表面に上記電極に相対
する突起電極および該突起電極に接続する導体層を配設
した配線基板とを、上記電極と上記突起電極とを圧接し
て接続し、上記配線基板と上記半導体素子との間に介在
した熱硬化性樹脂から成る接着剤により固着された構成
であって、上記導体層の表面が上記熱硬化性樹脂により
覆われて、露出しないため、信頼性の高い半導体装置が
さらに低コストで容易に得られる。According to a second aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor element having an electrode on a surface; and an impregnated insulating fiber impregnated with a resin. A wiring board provided with a conductor layer connected to the protruding electrode is connected by press-contacting the electrode and the protruding electrode, and is made of a thermosetting resin interposed between the wiring board and the semiconductor element. Since the surface of the conductor layer is covered with the thermosetting resin and is not exposed, a highly reliable semiconductor device can be easily obtained at lower cost.

【００３５】またこの発明に係わる請求項３記載の半導
体装置は、請求項１または２において、導体層が形成さ
れた配線基板の周辺部領域の表面をレジスト膜で覆い、
該レジスト膜の開口部内に半導体素子を配置し、上記配
線基板と上記半導体素子との間に介在する熱硬化性樹脂
が上記レジスト膜上に渡って延在するため、配線基板が
大きくても導体層を容易に熱硬化性樹脂で覆うことがで
き、低コストで容易に信頼性の高い半導体装置が得られ
る。According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the surface of the peripheral region of the wiring board on which the conductor layer is formed is covered with a resist film,
A semiconductor element is arranged in the opening of the resist film, and a thermosetting resin interposed between the wiring substrate and the semiconductor element extends over the resist film. The layer can be easily covered with a thermosetting resin, and a highly reliable semiconductor device can be easily obtained at low cost.

【００３６】またこの発明に係わる請求項４記載の半導
体装置は、請求項１〜３のいずれかにおいて、配線基板
の厚さが約０．０５〜０．１ｍｍ程度であるため、反り
が低減できて、他のプリント配線板等に実装する際、確
実に実装できる信頼性の高い半導体装置が得られる。In the semiconductor device according to a fourth aspect of the present invention, the thickness of the wiring board is about 0.05 to 0.1 mm in any one of the first to third aspects, so that warpage can be reduced. As a result, a highly reliable semiconductor device that can be reliably mounted when mounted on another printed wiring board or the like can be obtained.

【００３７】またこの発明に係わる請求項５記載の半導
体装置は、請求項１〜４のいずれかにおいて、熱硬化性
樹脂が、樹脂中に絶縁性粒子を含有したため、熱硬化性
樹脂の線膨張係数を低減でき、熱硬化性樹脂と半導体素
子および配線基板との界面のせん断応力が低減できた信
頼性の向上した半導体装置が得られる。According to a fifth aspect of the present invention, there is provided the semiconductor device according to any one of the first to fourth aspects, wherein the thermosetting resin contains insulating particles in the resin, so that the linear expansion of the thermosetting resin is achieved. The coefficient can be reduced, and a semiconductor device with improved reliability in which the shear stress at the interface between the thermosetting resin and the semiconductor element and the wiring substrate can be reduced can be obtained.

【００３８】またこの発明に係わる請求項６記載の半導
体装置の製造方法は、請求項１〜５のいずれかに記載の
半導体装置の製造方法であって、配線基板上に、熱硬化
性樹脂から成る接着剤となるフィルム状の熱硬化シート
をＢステージ状態にて配置し、上記配線基板および半導
体素子の電極と突起電極とが相対した状態で、上記半導
体素子を上記配線基板に押しつけ、上記配線基板表面に
配設された導体層表面を加熱により溶融された上記熱硬
化性樹脂で覆った後、該熱硬化性樹脂を硬化させるた
め、低コストで信頼性の高い半導体装置を容易に製造す
ることができ、また生産性も向上できる。According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to any one of the first to fifth aspects, wherein a thermosetting resin is formed on the wiring substrate. A film-like thermosetting sheet as an adhesive is placed in a B-stage state, and the semiconductor element is pressed against the wiring board in a state where the electrodes of the wiring board and the semiconductor element are opposed to the projecting electrodes, and the wiring is formed. After covering the surface of the conductor layer disposed on the substrate surface with the thermosetting resin melted by heating, the thermosetting resin is cured, so that a low-cost and highly reliable semiconductor device can be easily manufactured. And productivity can be improved.

【００３９】またこの発明に係わる請求項７記載の半導
体装置の製造方法は、請求項１記載の半導体装置の製造
方法であって、配線基板上に、絶縁性粒子を含有する層
と含有しない層との２層構成であり熱硬化性樹脂から成
る接着剤となるフィルム状の熱硬化シートを、上記絶縁
性粒子を含有しない層を下方にしてＢステージ状態にて
配置し、上記配線基板の電極と半導体素子の突起電極と
が相対した状態で、上記半導体素子を上記配線基板に押
しつけ、上記配線基板表面に配設された導体層表面を加
熱により溶融された上記熱硬化性樹脂で覆った後、該熱
硬化性樹脂を硬化させるため、配線基板の電極と半導体
素子の突起電極との良好で安定した電気的接続が得られ
ると共に、熱硬化性樹脂と半導体素子および配線基板と
の界面のせん断応力が低減できた信頼性の向上した半導
体装置が低コストで容易に得られる。According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first aspect, wherein a layer containing insulating particles and a layer containing no insulating particles are formed on the wiring substrate. And a film-like thermosetting sheet serving as an adhesive made of a thermosetting resin is disposed in a B-stage state with the layer not containing the insulating particles downward, and the electrode of the wiring board is formed. After the semiconductor element is pressed against the wiring board with the protruding electrodes of the semiconductor element facing each other, and after covering the surface of the conductor layer disposed on the wiring board surface with the thermosetting resin melted by heating, Since the thermosetting resin is cured, good and stable electrical connection between the electrode of the wiring board and the protruding electrode of the semiconductor element can be obtained, and the shearing of the interface between the thermosetting resin and the semiconductor element and the wiring board can be achieved. Yes There semiconductor device with improved could be reduced reliability can be easily obtained at low cost.

【００４０】またこの発明に係わる請求項８記載の半導
体装置の製造方法は、請求項２記載の半導体装置の製造
方法であって、配線基板上に、絶縁性粒子を含有する層
と含有しない層との２層構成であり熱硬化性樹脂から成
る接着剤となるフィルム状の熱硬化シートを、上記絶縁
性粒子を含有する層を下方にしてＢステージ状態にて配
置し、上記配線基板の突起電極と半導体素子の電極とが
相対した状態で、上記半導体素子を上記配線基板に押し
つけ、上記配線基板表面に配設された導体層表面を加熱
により溶融された上記熱硬化性樹脂で覆った後、該熱硬
化性樹脂を硬化させるため、配線基板の突起電極と半導
体素子の電極との良好で安定した電気的接続が得られる
と共に、熱硬化性樹脂と半導体素子および配線基板との
界面のせん断応力が低減できた信頼性の向上した半導体
装置が低コストで容易に得られる。According to a eighth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the second aspect, wherein a layer containing insulating particles and a layer containing no insulating particles are formed on the wiring substrate. And a film-like thermosetting sheet serving as an adhesive made of a thermosetting resin is disposed in a B-stage state with the layer containing the insulating particles downward, and the protrusion of the wiring board is formed. After the semiconductor element is pressed against the wiring board in a state where the electrode and the electrode of the semiconductor element are opposed to each other, after covering the surface of the conductor layer disposed on the wiring board surface with the thermosetting resin melted by heating. In order to cure the thermosetting resin, good and stable electrical connection between the protruding electrode of the wiring board and the electrode of the semiconductor element can be obtained, and the shearing of the interface between the thermosetting resin and the semiconductor element and the wiring board can be achieved. stress Reduction can semiconductor device with improved reliability can be easily obtained at low cost.

【００４１】またこの発明に係わる請求項９記載の半導
体装置の製造方法に用いる接着剤は、熱硬化性樹脂から
成り、絶縁性粒子を含有する層と含有しない層との２層
構造のフィルム状熱硬化シートで構成されたため、半導
体素子と配線基板との接続において、突起電極と電極と
の良好で安定した電気的接続が容易に可能になり、信頼
性の向上した半導体装置が低コストで容易に得られる。The adhesive used in the method for manufacturing a semiconductor device according to the ninth aspect of the present invention is formed of a thermosetting resin, and has a two-layer film structure including a layer containing insulating particles and a layer not containing the insulating particles. Since it is made of a thermosetting sheet, good and stable electrical connection between the protruding electrode and the electrode can be easily made in connection between the semiconductor element and the wiring board, and a semiconductor device with improved reliability can be easily manufactured at low cost. Is obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 この発明の実施の形態１による半導体装置の
構造を示す断面図である。FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention;

【図２】 この発明の実施の形態２による半導体装置の
構造を示す断面図である。FIG. 2 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention;

【図３】 この発明の実施の形態３による半導体装置の
構造を示す断面図である。FIG. 3 is a sectional view showing a structure of a semiconductor device according to a third embodiment of the present invention;

【図４】 この発明の実施の形態４による半導体装置の
構造を示す断面図である。FIG. 4 is a sectional view showing a structure of a semiconductor device according to a fourth embodiment of the present invention;

【図５】 この発明の実施の形態５による半導体装置の
製造方法を示す断面図である。FIG. 5 is a sectional view illustrating a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention;

【図６】 この発明の実施の形態６による半導体装置の
製造方法を示す断面図である。FIG. 6 is a sectional view illustrating a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention.

【図７】 この発明の実施の形態６の別例による半導体
装置の製造方法を示す断面図である。FIG. 7 is a sectional view illustrating a method of manufacturing a semiconductor device according to another example of Embodiment 6 of the present invention;

【図８】 従来の半導体装置の構造を示す断面図であ
る。FIG. 8 is a cross-sectional view illustrating a structure of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１２ 半導体素子、１３ 電極、１４ 突起電極、１５
配線基板、１６ 導体層、１６ａ 電極、１７ 熱硬
化性樹脂から成る接着剤（熱硬化性接着剤）、１７ｂ
フィルム状熱硬化シートとしての接着フィルム、１７ｃ
絶縁性粒子を含有しない層としての第１のフィルム
層、１７ｄ 絶縁性粒子を含有する層としての第２のフ
ィルム層、２２ レジスト膜、２３ 突起電極、２４
絶縁性粒子。12 semiconductor element, 13 electrode, 14 projecting electrode, 15
Wiring board, 16 conductor layers, 16a electrode, 17 thermosetting resin adhesive (thermosetting adhesive), 17b
Adhesive film as film-like thermosetting sheet, 17c
A first film layer as a layer containing no insulating particles, 17d a second film layer as a layer containing insulating particles, 22 resist film, 23 projecting electrode, 24
Insulating particles.

フロントページの続き (72)発明者 利田 賢二 東京都千代田区丸の内二丁目２番３号 三 菱電機株式会社内 (72)発明者 北村 洋一 東京都千代田区丸の内二丁目２番３号 三 菱電機株式会社内 Ｆターム(参考） 5E314 AA25 BB03 CC01 DD06 FF21 GG19 5F044 KK02 KK17 LL11 LL15 RR17 RR18 RR19 5F061 AA01 BA04 CA05 CB02 Continuing from the front page (72) Inventor Kenji Toda 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation (72) Inventor Yoichi Kitamura 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Co., Ltd. In-house F term (reference) 5E314 AA25 BB03 CC01 DD06 FF21 GG19 5F044 KK02 KK17 LL11 LL15 RR17 RR18 RR19 5F061 AA01 BA04 CA05 CB02

Claims (9)

【特許請求の範囲】[Claims] 【請求項１】 突起電極を有する半導体素子と、絶縁性
の繊維に樹脂を含浸させて構成し、表面に上記突起電極
に相対する電極を含む導体層を配設した配線基板とを、
上記突起電極と上記電極とを圧接して接続し、上記配線
基板と上記半導体素子との間に介在した熱硬化性樹脂か
ら成る接着剤により固着された半導体装置において、上
記導体層の表面が上記熱硬化性樹脂により覆われて、露
出しないことを特徴とする半導体装置。1. A semiconductor element having a protruding electrode and a wiring board which is formed by impregnating a resin with insulating fibers and having a conductive layer including an electrode facing the protruding electrode on a surface thereof.
In a semiconductor device in which the protruding electrode and the electrode are pressed and connected to each other and fixed by an adhesive made of a thermosetting resin interposed between the wiring substrate and the semiconductor element, the surface of the conductor layer is A semiconductor device which is covered with a thermosetting resin and is not exposed. 【請求項２】 表面に電極を有する半導体素子と、絶縁
性の繊維に樹脂を含浸させて構成し、表面に上記電極に
相対する突起電極および該突起電極に接続する導体層を
配設した配線基板とを、上記電極と上記突起電極とを圧
接して接続し、上記配線基板と上記半導体素子との間に
介在した熱硬化性樹脂から成る接着剤により固着された
半導体装置において、上記導体層の表面が上記熱硬化性
樹脂により覆われて、露出しないことを特徴とする半導
体装置。2. A wiring comprising a semiconductor element having an electrode on a surface thereof and an insulating fiber impregnated with a resin, and having on the surface a protruding electrode facing the electrode and a conductor layer connected to the protruding electrode. In a semiconductor device, a substrate is connected by pressing the electrode and the protruding electrode by pressure, and fixed by an adhesive made of a thermosetting resin interposed between the wiring substrate and the semiconductor element; Wherein the surface of the semiconductor device is covered with the thermosetting resin and is not exposed. 【請求項３】 導体層が形成された配線基板の周辺部領
域の表面をレジスト膜で覆い、該レジスト膜の開口部内
に半導体素子を配置し、上記配線基板と上記半導体素子
との間に介在する熱硬化性樹脂が上記レジスト膜上に渡
って延在することを特徴とする請求項１または２記載の
半導体装置。3. The semiconductor device according to claim 1, wherein a surface of a peripheral region of the wiring substrate on which the conductor layer is formed is covered with a resist film, a semiconductor element is disposed in an opening of the resist film, and a semiconductor element is interposed between the wiring substrate and the semiconductor element. 3. The semiconductor device according to claim 1, wherein the thermosetting resin extends over the resist film. 【請求項４】 配線基板の厚さが約０．０５〜０．１ｍ
ｍ程度であることを特徴とする請求項１〜３のいずれか
に記載の半導体装置。4. The wiring board has a thickness of about 0.05 to 0.1 m.
The semiconductor device according to claim 1, wherein the distance is about m. 【請求項５】 熱硬化性樹脂が、樹脂中に絶縁性粒子を
含有したものであることを特徴とする請求項１〜４のい
ずれかに記載の半導体装置。5. The semiconductor device according to claim 1, wherein the thermosetting resin contains insulating particles in the resin. 【請求項６】 配線基板上に、熱硬化性樹脂から成る接
着剤となるフィルム状の熱硬化シートをＢステージ状態
にて配置し、上記配線基板および半導体素子の電極と突
起電極とが相対した状態で、上記半導体素子を上記配線
基板に押しつけ、上記配線基板表面に配設された導体層
表面を加熱により溶融された上記熱硬化性樹脂で覆った
後、該熱硬化性樹脂を硬化させることを特徴とする請求
項１〜５のいずれかに記載の半導体装置の製造方法。6. A film-shaped thermosetting sheet serving as an adhesive made of a thermosetting resin is arranged in a B-stage state on a wiring board, and the electrodes of the wiring board and the semiconductor element are opposed to the protruding electrodes. In this state, pressing the semiconductor element against the wiring substrate, covering the surface of the conductor layer disposed on the surface of the wiring substrate with the thermosetting resin melted by heating, and then curing the thermosetting resin. The method for manufacturing a semiconductor device according to claim 1, wherein: 【請求項７】 配線基板上に、絶縁性粒子を含有する層
と含有しない層との２層構成であり熱硬化性樹脂から成
る接着剤となるフィルム状の熱硬化シートを、上記絶縁
性粒子を含有しない層を下方にしてＢステージ状態にて
配置し、上記配線基板の電極と半導体素子の突起電極と
が相対した状態で、上記半導体素子を上記配線基板に押
しつけ、上記配線基板表面に配設された導体層表面を加
熱により溶融された上記熱硬化性樹脂で覆った後、該熱
硬化性樹脂を硬化させることを特徴とする請求項１記載
の半導体装置の製造方法。7. A film-like thermosetting sheet serving as an adhesive composed of a thermosetting resin and having a two-layer structure of a layer containing an insulating particle and a layer not containing the insulating particle is provided on the wiring substrate. The semiconductor element is pressed against the wiring board in a state where the electrode of the wiring board and the protruding electrode of the semiconductor element are opposed to each other, and the semiconductor element is disposed on the surface of the wiring board. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the surface of the provided conductor layer is covered with the thermosetting resin melted by heating, and then the thermosetting resin is cured. 【請求項８】 配線基板上に、絶縁性粒子を含有する層
と含有しない層との２層構成であり熱硬化性樹脂から成
る接着剤となるフィルム状の熱硬化シートを、上記絶縁
性粒子を含有する層を下方にしてＢステージ状態にて配
置し、上記配線基板の突起電極と半導体素子の電極とが
相対した状態で、上記半導体素子を上記配線基板に押し
つけ、上記配線基板表面に配設された導体層表面を加熱
により溶融された上記熱硬化性樹脂で覆った後、該熱硬
化性樹脂を硬化させることを特徴とする請求項２記載の
半導体装置の製造方法。8. A film-like thermosetting sheet serving as an adhesive made of a thermosetting resin having a two-layer structure of a layer containing insulating particles and a layer not containing the insulating particles is provided on the wiring substrate. The semiconductor element is pressed against the wiring board with the protruding electrode of the wiring board and the electrode of the semiconductor element facing each other, and the semiconductor element is placed on the surface of the wiring board. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the surface of the provided conductor layer is covered with the thermosetting resin melted by heating, and then the thermosetting resin is cured. 【請求項９】 熱硬化性樹脂から成り、絶縁性粒子を含
有する層と含有しない層との２層構造のフィルム状熱硬
化シートで構成されたことを特徴とする、請求項７また
は８記載の半導体装置の製造方法に用いる接着剤。9. A thermosetting sheet made of a thermosetting resin and having a two-layer structure of a layer containing insulating particles and a layer not containing insulating particles. Adhesive used in the method for manufacturing a semiconductor device.
JP11014126A 1999-01-22 1999-01-22 Semiconductor device, and its manufacture, and adhesive used therein Pending JP2000216195A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11014126A JP2000216195A (en) 1999-01-22 1999-01-22 Semiconductor device, and its manufacture, and adhesive used therein

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11014126A JP2000216195A (en) 1999-01-22 1999-01-22 Semiconductor device, and its manufacture, and adhesive used therein

Publications (1)

Publication Number Publication Date
JP2000216195A true JP2000216195A (en) 2000-08-04

Family

ID=11852444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11014126A Pending JP2000216195A (en) 1999-01-22 1999-01-22 Semiconductor device, and its manufacture, and adhesive used therein

Country Status (1)

Country Link
JP (1) JP2000216195A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007250573A (en) * 2006-03-13 2007-09-27 Seiko Epson Corp Process for manufacturing semiconductor device
JP2007305764A (en) * 2006-05-11 2007-11-22 Teikoku Tsushin Kogyo Co Ltd Manufacturing method of different shape component mounting substrate
US7400048B2 (en) 2005-10-10 2008-07-15 Samsung Electro-Mechanics Co., Ltd. Void-free circuit board and semiconductor package having the same
JP2011049298A (en) * 2009-08-26 2011-03-10 Fujitsu Semiconductor Ltd Method of manufacturing semiconductor device
JP2016182699A (en) * 2015-03-25 2016-10-20 パナソニックＩｐマネジメント株式会社 Film material and electronic component using the same, and method for manufacturing electronic component
JP2016184612A (en) * 2015-03-25 2016-10-20 富士通株式会社 Method for mounting semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7400048B2 (en) 2005-10-10 2008-07-15 Samsung Electro-Mechanics Co., Ltd. Void-free circuit board and semiconductor package having the same
CN100444373C (en) * 2005-10-10 2008-12-17 三星电机株式会社 Void-free circuit board and semiconductor package having the same
JP2007250573A (en) * 2006-03-13 2007-09-27 Seiko Epson Corp Process for manufacturing semiconductor device
JP2007305764A (en) * 2006-05-11 2007-11-22 Teikoku Tsushin Kogyo Co Ltd Manufacturing method of different shape component mounting substrate
JP2011049298A (en) * 2009-08-26 2011-03-10 Fujitsu Semiconductor Ltd Method of manufacturing semiconductor device
JP2016182699A (en) * 2015-03-25 2016-10-20 パナソニックＩｐマネジメント株式会社 Film material and electronic component using the same, and method for manufacturing electronic component
JP2016184612A (en) * 2015-03-25 2016-10-20 富士通株式会社 Method for mounting semiconductor device

Similar Documents

Publication Publication Date Title
KR100557049B1 (en) Semiconductor device and method of manufacturing same
US6621172B2 (en) Semiconductor device and method of fabricating the same, circuit board, and electronic equipment
KR19990082715A (en) Semiconductor device
JP3383811B2 (en) Semiconductor chip module and method of manufacturing the same
JP2001094003A (en) Semiconductor device and production method thereof
JP3654116B2 (en) Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
US6528889B1 (en) Electronic circuit device having adhesion-reinforcing pattern on a circuit board for flip-chip mounting an IC chip
JP2002026067A (en) Semiconductor device and its mounting method
JP2000277649A (en) Semiconductor and manufacture of the same
JP2000216195A (en) Semiconductor device, and its manufacture, and adhesive used therein
JP2000022300A (en) Wiring board and electronic unit
JP4085572B2 (en) Semiconductor device and manufacturing method thereof
JPH114064A (en) Anisotropic conductive resin and mounting structure for electronic component using the same
JP2007103614A (en) Semiconductor device and manufacturing method thereof
JP3225800B2 (en) Semiconductor device
JP4035949B2 (en) Wiring board, semiconductor device using the same, and manufacturing method thereof
JP3539528B2 (en) Semiconductor device and manufacturing method thereof
JPH10125725A (en) Semiconductor device and manufacturing method thereof
JP3611463B2 (en) Manufacturing method of electronic parts
JP3547270B2 (en) Mounting structure and method of manufacturing the same
JP2004247621A (en) Semiconductor device and its manufacturing method
JPH04171970A (en) Semiconductor device
JPH0831871A (en) Interface sealing film used for surface mount electronic device and surface mount structure
JPH11284022A (en) Semiconductor device and manufacture thereof
JP4520052B2 (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20040601

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050906

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20051107

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20051129

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060118

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20060214