JPH10125725A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JPH10125725A
JPH10125725A JP27605396A JP27605396A JPH10125725A JP H10125725 A JPH10125725 A JP H10125725A JP 27605396 A JP27605396 A JP 27605396A JP 27605396 A JP27605396 A JP 27605396A JP H10125725 A JPH10125725 A JP H10125725A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor element
layer
wiring board
adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27605396A
Other languages
Japanese (ja)
Inventor
Tsuneo Hamaguchi
恒夫 濱口
Akizo Tsuruta
明三 鶴田
Kenji Toshida
賢二 利田
Mitsunori Ishizaki
光範 石崎
Yoichi Kitamura
洋一 北村
Takahiro Nagamine
高宏 長嶺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP27605396A priority Critical patent/JPH10125725A/en
Publication of JPH10125725A publication Critical patent/JPH10125725A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent deterioration of insulating property of a conductive adhesive narrowly provided between fine electrodes of a semiconductor element caused by conductive particles of the adhesive, and which can connect the semiconductor element to a wiring substrate with a good productivity. SOLUTION: The semiconductor device includes a semiconductor element 1 having electrodes 2 and projected electrodes 3 each having a sectional area smaller than each of the electrodes 2, a wiring substrate 4 having electrodes 5 provided at positions opposed to the projected electrodes 3, and a plurality of adhesive layers provided between the element 1 and substrate 4. The plurality of adhesive layers include an adhesive-alone layer 14 not containing conductive particles 6 and arranged on the side of the element 1, and an anisotropy conductive adhesive layer 7 provided on the side of the substrate 4 for conducting the electrodes 3 and the electrodes 5 on the substrate and opposed thereto.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子と配線
基板の電極同士を異方性導電接着剤で接続することによ
って得られる半導体装置およびその製造方法に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device obtained by connecting a semiconductor element and electrodes of a wiring board with an anisotropic conductive adhesive and a method of manufacturing the same.

【0002】[0002]

【従来の技術】電子機器をより小型化するために、パッ
ケージされた半導体素子を配線基板にはんだ付けする方
法から、パッケージしないで裸のまま半導体素子を配線
基板に実装する方法に変わってきた。半導体素子を裸の
ままで配線基板に実装する方法として、半導体素子の裏
面を配線基板に導電性接着剤で接着し、半導体素子の電
極と配線基板の電極とをワイヤで接続する方法がある。
この方法は半導体素子と配線基板の電極とを一本一本ワ
イヤで接続するため、多数の電極を接続するのに時間が
かかる。また、接続される配線基板の電極を半導体素子
の周辺に配置するため、実装面積が半導体素子の面積よ
りも大きくとる必要がある。そこで、半導体素子とほぼ
同じ面積で実装する方法として、半導体素子を裏返し
て、配線基板電極に直接接続するフリップチップ接続方
法が開発された。
2. Description of the Related Art In order to further reduce the size of electronic equipment, there has been a change from a method of soldering a packaged semiconductor element to a wiring board to a method of mounting a semiconductor element on a wiring board without packaging without packaging. As a method of mounting a semiconductor element on a wiring board while bare, there is a method of bonding the back surface of the semiconductor element to the wiring board with a conductive adhesive, and connecting the electrode of the semiconductor element and the electrode of the wiring board with a wire.
In this method, since the semiconductor element and the electrodes of the wiring board are connected one by one by wires, it takes time to connect a large number of electrodes. Further, since the electrodes of the wiring board to be connected are arranged around the semiconductor element, the mounting area needs to be larger than the area of the semiconductor element. Therefore, as a method of mounting the semiconductor device with almost the same area as the semiconductor device, a flip chip connection method of turning the semiconductor device upside down and directly connecting to the wiring board electrode has been developed.

【0003】その方法として、(1)導電性接着剤を用
いて接続する方法(例えば、日刊工業新聞社発行、表面
実装技術、9月号1994年、48ページ)と(2)は
んだを用いて接続する方法(例えば、工業調査会、19
86年6月1日発行、サーフェイス・マウント・テクノ
ロジー、172ページ)がある。以下、図面を参照しな
がら説明する。図7は、導電性接着剤を用いて接続した
従来の半導体装置の構成を示す断面図である。図におい
て、1はパッケージしていない裸の半導体素子、2は半
導体素子1の上に形成された電極、3はこの半導体素子
上の電極2の上に形成された突起電極、4は配線基板、
5は配線基板4上に形成された電極、21は導電性接着
剤、22は封止剤を示す。
[0003] As the method, (1) a connection method using a conductive adhesive (for example, surface mounting technology, published by Nikkan Kogyo Shimbun, September issue, 1994, p. 48) and (2) a method using solder. How to connect (for example, Industrial Research Council, 19
Published June 1, 1986, Surface Mount Technology, p. 172). This will be described below with reference to the drawings. FIG. 7 is a cross-sectional view showing the configuration of a conventional semiconductor device connected using a conductive adhesive. In the figure, 1 is a bare semiconductor element not packaged, 2 is an electrode formed on the semiconductor element 1, 3 is a protruding electrode formed on the electrode 2 on the semiconductor element, 4 is a wiring board,
Reference numeral 5 denotes an electrode formed on the wiring board 4, reference numeral 21 denotes a conductive adhesive, and reference numeral 22 denotes a sealant.

【0004】このような構造を有した従来の半導体装置
の製造方法について説明する。まず、めっきを用いて、
半導体素子1の電極2上に突起電極3を形成する。次
に、平面板に均一膜厚に形成された導電性接着剤層(図
示せず)に、この突起電極3を押し付け、導電性接着剤
21を突起電極3に転写する。次に、半導体素子1と配
線基板4を向かい合わせ、半導体素子1の突起電極3と
配線基板4上の電極5との位置合わせた後に、半導体素
子1を配線基板4に押し付け、突起電極3と配線基板4
上の電極5とを導電性接着剤21を介して接触させる。
次に、約150℃の条件で数時間加熱して導電性接着剤
21を硬化させた後に、外部から湿気等の侵入を防ぐた
めの封止剤22を半導体素子1と配線基板4の間に注入
し、加熱硬化させることにより図7に示した半導体装置
を得ることができる。
A method of manufacturing a conventional semiconductor device having such a structure will be described. First, using plating,
The protruding electrode 3 is formed on the electrode 2 of the semiconductor element 1. Next, the protruding electrode 3 is pressed against a conductive adhesive layer (not shown) formed on the flat plate to have a uniform thickness, and the conductive adhesive 21 is transferred to the protruding electrode 3. Next, after the semiconductor element 1 and the wiring board 4 are opposed to each other and the protruding electrodes 3 of the semiconductor element 1 and the electrodes 5 on the wiring board 4 are aligned, the semiconductor element 1 is pressed against the wiring board 4 and Wiring board 4
The upper electrode 5 is brought into contact via the conductive adhesive 21.
Next, after heating the conductive adhesive 21 at a temperature of about 150 ° C. for several hours to cure the conductive adhesive 21, a sealant 22 for preventing invasion of moisture or the like from the outside is provided between the semiconductor element 1 and the wiring board 4. The semiconductor device shown in FIG. 7 can be obtained by injecting and heating and curing.

【0005】図8は、はんだを用いて接続する場合の従
来の半導体装置の構成を示す断面図である。図におい
て、1は半導体素子、2は半導体素子1の上に形成され
た電極、3はこの半導体素子上の電極2上に形成された
突起電極、4は配線基板、5は配線基板4の上に形成さ
れた電極、22は封止剤、23ははんだを示す。このよ
うな構造を有した従来の半導体装置の製造方法について
説明する。まず、半導体素子1の上に形成された電極の
2上に、蒸着等でCr、Cuの膜を形成した後、レジス
トをパターニングして、めっきまたは蒸着で、Pb−S
nのはんだの突起電極3を形成する。次に、あらかじめ
共晶はんだ23を供給してある配線基板4上の電極5と
位置合わせを行い、半導体素子1を加熱してはんだ23
を溶融させて、突起電極3と電極5を接合し、半導体素
子1と配線基板4の間に封止剤22を注入し、加熱硬化
させることにより、図8に示した半導体装置を得ること
ができる。
FIG. 8 is a cross-sectional view showing a configuration of a conventional semiconductor device when connection is made using solder. In the figure, 1 is a semiconductor element, 2 is an electrode formed on the semiconductor element 1, 3 is a protruding electrode formed on the electrode 2 on the semiconductor element, 4 is a wiring board, 5 is a wiring board 4 , 22 denotes a sealant, and 23 denotes solder. A conventional method for manufacturing a semiconductor device having such a structure will be described. First, a film of Cr and Cu is formed on the electrode 2 formed on the semiconductor element 1 by vapor deposition or the like, and then the resist is patterned and plated or vapor-deposited by Pb-S
An n-solder electrode 3 is formed. Next, the semiconductor element 1 is aligned with the electrode 5 on the wiring board 4 to which the eutectic solder 23 is supplied in advance, and the solder 23 is heated.
Is melted, the protruding electrode 3 and the electrode 5 are joined, the sealing agent 22 is injected between the semiconductor element 1 and the wiring substrate 4, and is cured by heating to obtain the semiconductor device shown in FIG. it can.

【0006】図9は、例えば、特公昭62−6652号
公報に記載された異方性導電接着剤によって半導体素子
と配線基板とを接続する従来の半導体装置の構成を示す
断面図である。図において、1は半導体素子、2は半導
体素子1の上に形成された電極、3はこの半導体素子上
の電極2上に形成された突起電極、4は配線基板、7は
異方性導電接着剤の層、9は配線基板4上の導電リード
線を示す。なお、異方性導電接着剤とは、接着剤中に金
属粒子、プラスチックボールの表面に金属をめきした粒
子などを分散したもので、圧力が加えられると接着剤が
排除され、電気的な導通が得られるものである。
FIG. 9 is a cross-sectional view showing the structure of a conventional semiconductor device for connecting a semiconductor element and a wiring board with an anisotropic conductive adhesive described in, for example, Japanese Patent Publication No. 62-6652. In the figure, 1 is a semiconductor element, 2 is an electrode formed on the semiconductor element 1, 3 is a protruding electrode formed on the electrode 2 on the semiconductor element, 4 is a wiring board, 7 is an anisotropic conductive adhesive. The agent layer 9 indicates conductive leads on the wiring board 4. The anisotropic conductive adhesive is obtained by dispersing metal particles in an adhesive, particles of metal plated on the surface of a plastic ball, and the like. Is obtained.

【0007】配線基板4上の導電リード線9上に異方性
導電接着剤の層7を形成し、突起電極3を有した半導体
素子1を押し付けると、突起電極3の下の部分の異方性
導電接着剤の層7は圧力が加えられた方向に導通する。
これにより、突起電極3と導電リード9は導通する。同
時に、半導体素子1は配線基板4に異方性導電接着剤の
層7の接着作用によって固着され、外部からの湿気やほ
こりの侵入を防止することができる。また、半導体素子
1の下面は異方性導電接着剤の層7によって全面的に配
線基板4に接着しているので接着面積が広くなり接合強
度も強くなる。
When a layer 7 of an anisotropic conductive adhesive is formed on a conductive lead wire 9 on a wiring board 4 and the semiconductor element 1 having the protruding electrode 3 is pressed, an anisotropic portion below the protruding electrode 3 is formed. The conductive conductive adhesive layer 7 conducts in the direction in which the pressure is applied.
As a result, the protruding electrode 3 and the conductive lead 9 conduct. At the same time, the semiconductor element 1 is fixed to the wiring board 4 by the adhesive action of the layer 7 of the anisotropic conductive adhesive, so that the invasion of moisture and dust from the outside can be prevented. Further, since the lower surface of the semiconductor element 1 is entirely bonded to the wiring board 4 by the anisotropic conductive adhesive layer 7, the bonding area is increased and the bonding strength is increased.

【0008】[0008]

【発明が解決しようとする課題】図7、図8に示した従
来の半導体装置には以下の問題点があった。 (1)半導体素子を接続のため、配線基板電極に押し当
てた時に、導電性接着剤またははんだの接着剤が横に広
がり、隣接の電極と接触し、ショートが発生し、微細電
極間距離の半導体素子の接続ができない。 (2)半導体素子の突起電極と配線基板の電極を導電性
接着剤またははんだで接続してから、信頼性を高めるた
めに半導体素子と配線基板間に封止剤を注入するため、
プロセスが多く生産性に欠ける。
The conventional semiconductor devices shown in FIGS. 7 and 8 have the following problems. (1) When a semiconductor element is pressed against a wiring board electrode for connection, a conductive adhesive or a solder adhesive spreads laterally and comes into contact with an adjacent electrode, causing a short circuit and reducing the distance between fine electrodes. Unable to connect semiconductor device. (2) After connecting the protruding electrode of the semiconductor element and the electrode of the wiring board with a conductive adhesive or solder, and then injecting a sealing agent between the semiconductor element and the wiring board to improve reliability,
Many processes lack productivity.

【0009】図9に示した従来技術はこれらの問題点を
一応解決してはいるが、突起電極間Aには導電性接着剤
の導電性の粒子は存在し、電極間隔Aが狭くなる微細電
極を有する半導体素子においては、突起電極間の導電性
粒子同士が擦りあって、突起電極間の絶縁抵抗が劣化し
たり、半導体素子の表面での電極間に導電粒子による導
通チャンネルができて電極間の絶縁性が劣化するという
問題点があった。
Although the prior art shown in FIG. 9 solves these problems for the time being, conductive particles of a conductive adhesive are present between the protruding electrodes A, and the fine particles in which the distance A between the electrodes is reduced. In a semiconductor element having electrodes, the conductive particles between the protruding electrodes rub against each other, thereby deteriorating the insulation resistance between the protruding electrodes or forming conductive channels between the electrodes on the surface of the semiconductor element by the conductive particles. There was a problem that the insulation between them deteriorated.

【0010】本発明は、電極間隔の狭い微細電極を有す
る半導体素子においても、電極間に介在する導電性接着
剤の導電粒子に起因する絶縁性の劣化を防止し、さらに
配線基板との良好なる接続を生産性良く実現する半導体
装置およびその製造方法を提供することを目的としてい
る。
According to the present invention, even in a semiconductor element having fine electrodes with a narrow electrode interval, deterioration of insulating properties due to conductive particles of a conductive adhesive interposed between the electrodes can be prevented, and furthermore, the present invention can be used with a wiring board. It is an object of the present invention to provide a semiconductor device which realizes connection with high productivity and a method of manufacturing the same.

【0011】[0011]

【課題を解決するための手段】この発明に係る半導体装
置は、電極上に該電極より小さな断面積の突起電極を有
する半導体素子と、突起電極と対向する位置に配設され
た電極を有する配線基板と、半導体素子と配線基板との
間に形成され、突起電極とこれに対向する前記配線基板
上の電極とを導通させる異方性導電接着剤の層とを備え
たものである。
A semiconductor device according to the present invention comprises a semiconductor element having a protruding electrode having a smaller cross-sectional area than an electrode on an electrode, and a wiring having an electrode disposed at a position facing the protruding electrode. The semiconductor device includes a substrate, and a layer of an anisotropic conductive adhesive formed between the semiconductor element and the wiring substrate and electrically connecting the protruding electrode and an electrode on the wiring substrate opposed to the protruding electrode.

【0012】また、この発明に係る半導体装置は、電極
上に該電極より小さな断面積の突起電極を有する半導体
素子と、突起電極と対向する位置に配設された電極を有
する配線基板と、半導体素子と配線基板との間に形成さ
れた複数層の接着剤の層とを備えた半導体装置であっ
て、複数層の接着剤の層は、半導体素子の側にあって導
電粒子を含まない接着剤の層と配線基板の側にあって突
起電極とこれに対向する配線基板上の電極とを導通させ
る異方性導電接着剤の層とで構成されたものである。
A semiconductor device according to the present invention includes a semiconductor element having a protruding electrode having a smaller sectional area than an electrode, a wiring board having an electrode disposed at a position facing the protruding electrode, and a semiconductor device. A semiconductor device comprising a plurality of layers of adhesive formed between an element and a wiring board, wherein the plurality of layers of adhesive are bonded on a side of the semiconductor element and containing no conductive particles. It is composed of a layer of an agent, a protruding electrode on the side of the wiring board, and a layer of an anisotropic conductive adhesive for conducting between the protruding electrode and the electrode on the wiring board facing the protruding electrode.

【0013】また、この発明に係る半導体装置の配線基
板は、ガラス基板であることを特徴とするものである。
また、この発明に係る半導体装置の配線基板は、プリン
ト基板と樹脂材で形成された配線層とを積層したことを
特徴とするものである。また、この発明に係る半導体装
置の配線基板は、可とう性を有した樹脂材で構成された
配線層であることを特徴とするものである。
Further, the wiring substrate of the semiconductor device according to the present invention is characterized in that it is a glass substrate.
Further, the wiring board of the semiconductor device according to the present invention is characterized in that a printed board and a wiring layer formed of a resin material are laminated. Further, the wiring board of the semiconductor device according to the present invention is characterized in that it is a wiring layer made of a flexible resin material.

【0014】さらに、この発明に係る半導体装置の製造
方法は、半導体素子の電極上に該電極より小さな断面積
を有する突起電極をボールボンダで形成する工程と、異
方性導電接着剤を配線基板上の電極および配線が形成さ
れた面に接着する工程と、突起電極を異方性導電接着剤
を介して配線基板の電極に押し付ける工程とを有したも
のである。
Further, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a protruding electrode having a smaller cross-sectional area than the electrode on a semiconductor element electrode by a ball bonder; The method includes a step of bonding the upper electrode and the wiring on the surface on which the wiring is formed, and a step of pressing the protruding electrode against the electrode of the wiring substrate via an anisotropic conductive adhesive.

【0015】また、この発明に係る半導体装置の製造方
法は、電極上に該電極より小さな断面積の突起電極を有
する半導体素子の表面に導電粒子を含まない接着剤の層
を形成する工程と、異方性導電接着剤の層を配線基板上
の電極および配線が形成された面に形成する工程と、導
電粒子を含まない接着剤の層が形成された半導体素子と
異方性導電接着剤の層が形成された配線基板とを押し付
けて接着する工程とを有したものである。
Further, the method of manufacturing a semiconductor device according to the present invention includes a step of forming a layer of an adhesive containing no conductive particles on a surface of a semiconductor element having a projecting electrode having a smaller sectional area than the electrode on the electrode; Forming a layer of an anisotropic conductive adhesive on the surface of the wiring substrate on which the electrodes and wiring are formed; and forming a semiconductor element having an adhesive layer containing no conductive particles and an anisotropic conductive adhesive. Pressing and bonding to the wiring board on which the layer is formed.

【0016】[0016]

【発明の実施の形態】以下、本発明の一実施の形態を図
面に基づいて説明する。尚、図において従来と同一符合
は従来のものと同一あるいは相当のものを表す。 実施の形態1.図1は、本発明の実施の形態1による半
導体装置の構成を示す断面図である。図において、1は
半導体素子、2は半導体素子1上に形成された電極、3
は突起電極、4は例えばガラス基板からなる配線基板、
5は配線基板4上に形成された電極、6は導電性粒子、
7は導電性粒子6を含む異方性導電接着剤の層である。
An embodiment of the present invention will be described below with reference to the drawings. In the drawings, the same reference numerals as those in the related art denote the same or corresponding parts in the related art. Embodiment 1 FIG. FIG. 1 is a sectional view showing a configuration of the semiconductor device according to the first embodiment of the present invention. In the figure, 1 is a semiconductor element, 2 is an electrode formed on the semiconductor element 1, 3
Is a projecting electrode, 4 is a wiring board made of, for example, a glass substrate,
5 is an electrode formed on the wiring board 4, 6 is conductive particles,
Reference numeral 7 denotes a layer of an anisotropic conductive adhesive containing conductive particles 6.

【0017】本実施の形態においては、各突起電極3の
断面積は、半導体素子1上に形成された電極2より小さ
い断面積となるように形成されているので、各電極2の
間の距離Bが短い場合でも配線基盤4上の電極5との接
続に用いられる突起電極3の間隔Aは大きくとれる。そ
のため、突起電極3の間において異方性導電接着剤の層
7中の導電性粒子6同士が互いに接触したり、擦りあう
ことは軽減され、突起電極3間の良好な絶縁性を確保す
ることができる。
In the present embodiment, since the cross-sectional area of each protruding electrode 3 is formed to be smaller than the cross-sectional area of the electrode 2 formed on the semiconductor element 1, the distance between each of the electrodes 2 is increased. Even when B is short, the interval A between the protruding electrodes 3 used for connection with the electrodes 5 on the wiring board 4 can be made large. Therefore, the conductive particles 6 in the anisotropic conductive adhesive layer 7 are prevented from coming into contact with each other or rubbing each other between the protruding electrodes 3, and good insulation between the protruding electrodes 3 is ensured. Can be.

【0018】尚、半導体素子1の電極2上の突起電極3
の材料は金、銅、ニッケル、はんだ等の金属であればよ
い。その形成方法は写真製版技術とめっきまたは蒸着等
の金属の成膜技術を用いて行うことができる。導電性粒
子6は直径が5μm程度のエポキシ等のプラスチック粒
子に金等の金属膜を形成したものからなる。他に、ニッ
ケルまたは金の金属粒子を用いてもよい。異方性導電接
着剤の層7は、接着剤の主剤として熱硬化型のエポキシ
樹脂を用いたが、熱可塑性の接着剤を用いてもよい。
The protruding electrode 3 on the electrode 2 of the semiconductor element 1
May be a metal such as gold, copper, nickel, and solder. The formation method can be performed using a photoengraving technique and a metal film forming technique such as plating or vapor deposition. The conductive particles 6 are formed by forming a metal film such as gold on plastic particles such as epoxy having a diameter of about 5 μm. Alternatively, nickel or gold metal particles may be used. In the layer 7 of the anisotropic conductive adhesive, a thermosetting epoxy resin is used as a main component of the adhesive, but a thermoplastic adhesive may be used.

【0019】また、本実施の形態においては、例えば、
大きさと間隔がそれぞれ60μm角と10μmをもつ半
導体素子の電極2の上に、大きさ50μm角の突起電極
3を形成した半導体素子1をITO(インジウム・スズ
酸化物)の材料で構成される電極5を有したガラス基板
で構成された配線基板4に接続したところ良好な導通を
得ることができた。従って、本実施の形態1によれば、
微細な電極間隔を有した半導体素子の配線基板への接続
において良好な絶縁性を確保し、かつ良好な導通を可能
にすることができる。また、ガラス基板は微細配線が可
能であり、配線基板としてガラス基板を用いることによ
り半導体素子の実装密度を向上することができる。
In the present embodiment, for example,
A semiconductor element 1 in which a bump electrode 3 having a size of 50 μm is formed on an electrode 2 of a semiconductor element having a size and an interval of 60 μm square and 10 μm, respectively, is formed of an ITO (indium tin oxide) material. 5 was connected to the wiring substrate 4 composed of a glass substrate having good conductivity. Therefore, according to the first embodiment,
In the connection of the semiconductor element having a fine electrode spacing to the wiring board, good insulation can be ensured and good conduction can be achieved. Further, fine wiring can be performed on a glass substrate, and the mounting density of a semiconductor element can be improved by using a glass substrate as the wiring substrate.

【0020】実施の形態2.図2は、本発明の実施の形
態2による半導体装置の構成を示す断面図である。断面
図である。図において、1は半導体素子、2は半導体素
子1上に形成された電極、3は突起電極、40は配線基
板、5は配線基板40上に形成された電極、6は導電性
粒子、7は導電性粒子6を含む異方性導電接着剤の層で
ある。また、8は配線層、10は凹部、11は樹脂材の
絶縁層、12は配線層8上の金属からなる導体層、15
はプリント基板、16はプリント基板15上の配線パタ
ーンである。
Embodiment 2 FIG. 2 is a sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention. It is sectional drawing. In the figure, 1 is a semiconductor element, 2 is an electrode formed on the semiconductor element 1, 3 is a protruding electrode, 40 is a wiring board, 5 is an electrode formed on the wiring board 40, 6 is conductive particles, 7 is This is a layer of an anisotropic conductive adhesive containing conductive particles 6. Reference numeral 8 denotes a wiring layer, 10 denotes a recess, 11 denotes an insulating layer of a resin material, 12 denotes a conductor layer made of metal on the wiring layer 8,
Denotes a printed board, and 16 denotes a wiring pattern on the printed board 15.

【0021】本実施の形態においても、各突起電極3の
断面積は、半導体素子1上に形成された電極2より小さ
い断面積となるように形成されているので、各電極2の
間の距離が短い場合でも配線基板40上の電極5との接
続に用いられる突起電極3の間隔は大きくとれる。その
ため、突起電極3の間において異方性導電接着剤の層7
中の導電性粒子6同士が互いに接触したり、擦りあうこ
とは軽減され、突起電極3間の良好な絶縁性を確保する
ことができる。さらに、図に示すように本実施の形態に
おいては、配線基板40はプリント基板15とその上に
形成された絶縁層11と導体層12からなる配線層8で
構成されているので、ガラス基板を用いたものより軽く
なる。また、プリント基板15の配線ピッチTは現状技
術では200μm程度が限界であるが、このような配線
基板40を用いることによって、配線層8上での配線ピ
ッチT′は100μmという微細配線を実現できる。
Also in the present embodiment, since the cross-sectional area of each protruding electrode 3 is formed to be smaller than the cross-sectional area of the electrode 2 formed on the semiconductor element 1, the distance between the electrodes 2 is reduced. Is shorter, the distance between the protruding electrodes 3 used for connection with the electrodes 5 on the wiring board 40 can be increased. Therefore, an anisotropic conductive adhesive layer 7
It is reduced that the conductive particles 6 inside contact each other or rub against each other, so that good insulation between the protruding electrodes 3 can be secured. Further, as shown in the figure, in the present embodiment, the wiring board 40 is composed of the printed board 15 and the wiring layer 8 formed of the insulating layer 11 and the conductor layer 12 formed thereon, Lighter than those used. The wiring pitch T of the printed circuit board 15 is limited to about 200 μm in the state of the art, but by using such a wiring board 40, fine wiring with a wiring pitch T ′ on the wiring layer 8 of 100 μm can be realized. .

【0022】配線基板40はプリント基板15の表面に
エポキシ等の樹脂を塗布し、写真製版技術を用いてバイ
アホールを形成して絶縁層11を形成後、めっきまたは
蒸着等で金属膜を成膜し、写真製版技術を用いて、金属
膜をパターニングすることによって、導体層 12を前
記絶縁層11上に形成することができる。この絶縁層1
1と導体層12の形成を繰返すことにより配線層8の多
層化が可能である。このような配線基板40は表面の凹
凸が大きく、電極5の高さにばらつきが生じる。
For the wiring board 40, a resin such as epoxy is applied to the surface of the printed board 15, a via hole is formed by photolithography, the insulating layer 11 is formed, and a metal film is formed by plating or vapor deposition. Then, the conductor layer 12 can be formed on the insulating layer 11 by patterning the metal film using a photoengraving technique. This insulating layer 1
By repeating the formation of the wiring layer 8 and the conductor layer 12, the wiring layer 8 can be multi-layered. Such a wiring board 40 has large irregularities on the surface, and the height of the electrode 5 varies.

【0023】配線基板40の表面に凹凸があると、突起
電極3と配線基板40の電極5との間の距離が異なるこ
とになるので、すべての接続箇所において良好な接続が
得られなくなるとい問題がある。しかし、この問題に対
しては突起電極3を配線基板40の電極5に押し付ける
際に、配線基板40の電極5を凹部10が生ずるまで押
込むことによって解決され、すべての突起電極3と配線
基板40の電極5とは導電性粒子6を介して確実に接続
することが可能になる。実際に、微細な電極間隔を有す
る半導体素子1を接続したところ、実施の形態1と同様
な結果を得ることができた。以上のように、本実施の形
態によれば、突起電極間の良好な絶縁性を確保し、か
つ、実装密度の向上と軽量化を図った半導体装置を実現
できる。
If the surface of the wiring board 40 has irregularities, the distance between the protruding electrode 3 and the electrode 5 of the wiring board 40 will be different, so that a good connection cannot be obtained at all connection points. There is. However, this problem can be solved by pressing the electrode 5 of the wiring board 40 until the concave portion 10 is formed when the protruding electrode 3 is pressed against the electrode 5 of the wiring board 40. Forty-five electrodes 5 can be reliably connected via conductive particles 6. Actually, when the semiconductor element 1 having a fine electrode spacing was connected, the same result as in the first embodiment could be obtained. As described above, according to the present embodiment, it is possible to realize a semiconductor device that secures good insulation between the protruding electrodes and improves the mounting density and reduces the weight.

【0024】実施の形態3.図3は、本発明の実施の形
態3による半導体装置の構成を示す断面図である。図に
おいて、1は半導体素子、2は半導体素子1上に形成さ
れた電極、3は突起電極、8は配線層、5は配線層8上
に形成された電極、6は導電性粒子、7は導電性粒子6
を含む異方性導電接着剤の層である。また、10は凹
部、11は樹脂材の絶縁層、12は配線層8上の金属か
らなる導体層である。図に示すように、本実施の形態で
は、実施の形態1において用いたガラス基板からなる配
線基板4の代わりに、実施の形態2で示したような配線
層8を配線基板そのものとして用いたものである。配線
層8の形成方法は実施の形態2と同様の方法を用いる。
絶縁層11の樹脂は実施の形態2ではエポキシ樹脂を用
いたが、より可とう性のあるポリイミドでもよい。
Embodiment 3 FIG. FIG. 3 is a sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention. In the figure, 1 is a semiconductor element, 2 is an electrode formed on the semiconductor element 1, 3 is a protruding electrode, 8 is a wiring layer, 5 is an electrode formed on the wiring layer 8, 6 is conductive particles, 7 is Conductive particles 6
This is a layer of an anisotropic conductive adhesive containing: Reference numeral 10 denotes a recess, 11 denotes an insulating layer of a resin material, and 12 denotes a conductor layer made of a metal on the wiring layer 8. As shown in the figure, in the present embodiment, the wiring layer 8 as shown in the second embodiment is used as the wiring substrate itself instead of the wiring substrate 4 made of the glass substrate used in the first embodiment. It is. The method for forming the wiring layer 8 is the same as that in the second embodiment.
Although the epoxy resin is used as the resin for the insulating layer 11 in the second embodiment, a more flexible polyimide may be used.

【0025】また、本実施の形態においても、各突起電
極3の断面積は、半導体素子1上に形成された電極2よ
り小さい断面積となるように形成されているので、各電
極2の間の距離が短い場合でも配線層8上の電極5との
接続に用いられる突起電極3の間隔は大きくとれる。そ
のため、突起電極3の間において異方性導電接着剤の層
7中の導電性粒子6同士が互いに接触したり、擦りあう
ことは軽減され、突起電極3間の良好な絶縁性を確保す
ることができる。
Also in the present embodiment, the cross-sectional area of each protruding electrode 3 is formed so as to be smaller than the cross-sectional area of the electrode 2 formed on the semiconductor element 1. Is small, the distance between the protruding electrodes 3 used for connection with the electrodes 5 on the wiring layer 8 can be increased. Therefore, the conductive particles 6 in the anisotropic conductive adhesive layer 7 are prevented from coming into contact with each other or rubbing each other between the protruding electrodes 3, and good insulation between the protruding electrodes 3 is ensured. Can be.

【0026】配線基板としての配線層8の表面に凹凸が
あると、突起電極3と配線層8上の電極5との間の距離
が異なることになるので、すべての接続箇所において良
好な接続が得られなくなるとい問題がある。しかし、こ
の問題に対しても実施の形態2の場合と同様に、突起電
極3を配線層8の電極5に押し付ける際に、配線層8の
電極5が凹部10を生ずるまで押込むことによって解決
され、すべての突起電極3と配線層8上の電極5とは導
電性粒子6を介して確実に接続することが可能になる。
さらに、本実施の形態においては、配線基板としてフレ
キシブルな樹脂材を用いた配線層8のみで構成したこと
により、配線層8は半導体素子1と配線層8との熱膨張
係数差により発生する熱応力を十分吸収できるので、突
起電極3と配線層8上の電極5との長期間にわたる接続
の信頼性を向上することができる。
If the surface of the wiring layer 8 as a wiring substrate has irregularities, the distance between the protruding electrode 3 and the electrode 5 on the wiring layer 8 will be different, so that a good connection can be obtained at all connection points. There is a problem that it cannot be obtained. However, this problem can be solved by pressing the protruding electrode 3 against the electrode 5 of the wiring layer 8 until the electrode 5 of the wiring layer 8 has the concave portion 10 as in the case of the second embodiment. As a result, all the protruding electrodes 3 and the electrodes 5 on the wiring layer 8 can be reliably connected via the conductive particles 6.
Further, in the present embodiment, since the wiring board is constituted only by the wiring layer 8 using a flexible resin material, the wiring layer 8 is formed by a thermal expansion coefficient difference between the semiconductor element 1 and the wiring layer 8. Since the stress can be sufficiently absorbed, the reliability of the connection between the protruding electrode 3 and the electrode 5 on the wiring layer 8 over a long period can be improved.

【0027】実施の形態4.図4は、本発明の実施の形
態4による製造方法を示す図である。図において、1は
半導体素子、2は半導体素子1上に形成された電極、3
は突起電極、4は配線基板、5は配線基板4上に形成さ
れた電極、6は導電性粒子、7は導電性粒子6を含む異
方性導電接着剤の層である。図(a)は、半導体素子1
の電極2上にボールボンダで突起13を形成した状態を
示す。図(b)は、この突起13を平板で押し付け、突
起13の高さを均等にすると共に、突起13の先端を平
坦にし、突起電極3を形成した状態を示す。図(c)
は、配線基板4上に異方性導電接着剤の層7を形成した
状態を示す。さらに、図(d)は突起電極3をもつ半導
体素子1を配線基板4に押し付けて加熱し、突起電極3
と配線基板4の電極5が導通した状態を示す。このよう
に本実施の形態による半導体装置の製造方法によれば、
ボールボンダを用いて突起電極3を形成することによ
り、写真製版やめっきなどの煩雑な工程を経ることな
く、容易に突起電極3を形成できるという効果がある。
Embodiment 4 FIG. 4 is a diagram showing a manufacturing method according to the fourth embodiment of the present invention. In the figure, 1 is a semiconductor element, 2 is an electrode formed on the semiconductor element 1, 3
Denotes a projecting electrode, 4 denotes a wiring board, 5 denotes an electrode formed on the wiring board 4, 6 denotes conductive particles, and 7 denotes a layer of an anisotropic conductive adhesive containing the conductive particles 6. FIG. 1A shows a semiconductor device 1.
2 shows a state in which a projection 13 is formed on the electrode 2 by a ball bonder. FIG. 2B shows a state in which the projection 13 is pressed with a flat plate to make the height of the projection 13 uniform, the tip of the projection 13 is flattened, and the projection electrode 3 is formed. Figure (c)
Shows a state in which the layer 7 of the anisotropic conductive adhesive is formed on the wiring board 4. Further, FIG. 4D shows that the semiconductor element 1 having the protruding electrode 3 is pressed against the wiring board 4 and is heated, so that the
And a state where the electrode 5 of the wiring board 4 is conducted. As described above, according to the method for manufacturing a semiconductor device according to the present embodiment,
By forming the protruding electrodes 3 using a ball bonder, there is an effect that the protruding electrodes 3 can be easily formed without going through complicated steps such as photoengraving and plating.

【0028】実施の形態5.前述の実施の形態1におい
ては、半導体素子1の電極2は突起電極3より大きい断
面積を有しているため、半導体素子1の電極2の露出し
ている部分に導電性粒子6が存在すると、隣接する電極
2同士が導電性粒子6を介して導通チャネルができ、絶
縁信頼性が劣化する場合があるが、本実施の形態はこの
ような問題点をも改善するものである。図5は、本発明
の実施の形態5による半導体装置の構成を示す断面図で
ある。図において、1は半導体素子、2は半導体素子1
上に形成された電極、3は突起電極、4は配線基板、5
は配線基板4上に形成された電極、6は導電性粒子、7
は導電性粒子6を含む異方性導電接着剤の層、14は異
方性導電接着剤の層7と同一の接着剤を用いているが導
電性粒子6は含まない接着剤のみの層である。
Embodiment 5 In Embodiment 1 described above, since the electrode 2 of the semiconductor element 1 has a larger cross-sectional area than the protruding electrode 3, it is assumed that the conductive particles 6 exist in the exposed portion of the electrode 2 of the semiconductor element 1. In some cases, a conductive channel may be formed between the adjacent electrodes 2 via the conductive particles 6 and insulation reliability may be degraded. However, the present embodiment also solves such a problem. FIG. 5 is a sectional view showing a configuration of a semiconductor device according to a fifth embodiment of the present invention. In the figure, 1 is a semiconductor element, 2 is a semiconductor element 1
The electrodes formed on the top, 3 are protruding electrodes, 4 is a wiring board, 5
Is an electrode formed on the wiring board 4, 6 is conductive particles, 7
Is a layer of an anisotropic conductive adhesive containing conductive particles 6, and 14 is a layer of only an adhesive using the same adhesive as the layer 7 of anisotropic conductive adhesive but not containing the conductive particles 6. is there.

【0029】このように、本実施の形態では、半導体素
子1と配線基板4間には導電性粒子6を含む異方性導電
接着剤の層7とこの異方性導電接着剤の層7と同じ接着
剤を用い導電性粒子6を含まない接着剤のみの層14の
2つの層の接着剤の層が形成されている。尚、製造時の
生産効率を考慮すると、半導体素子1と配線基板4間の
接着剤を同時に硬化する必要があるため、導電性粒子6
のない接着剤の層14と導電性粒子6のある層7の接着
剤は同一材料の接着剤にする必要がある。
As described above, in the present embodiment, the layer 7 of the anisotropic conductive adhesive containing the conductive particles 6 and the layer 7 of the anisotropic conductive adhesive are provided between the semiconductor element 1 and the wiring board 4. The same adhesive is used to form two adhesive layers, that is, an adhesive-only layer 14 that does not include the conductive particles 6. In consideration of the production efficiency at the time of manufacturing, the adhesive between the semiconductor element 1 and the wiring board 4 needs to be cured at the same time.
The adhesive of the layer 14 of the adhesive without the layer and the adhesive of the layer 7 with the conductive particles 6 must be made of the same material.

【0030】本実施の形態においても、各突起電極3の
断面積は、半導体素子1上に形成された電極2より小さ
い断面積となるように形成されているので、各電極2同
士の間の距離Bが短い場合でも配線基板4上の電極5と
の接続に用いられる突起電極3同士の間隔Aは大きくと
れる。そのため、異方性導電接着剤の層7中では、各突
起電極3の間において導電性粒子6同士が互いに接触し
たり、擦りあうことは軽減され、突起電極3間の良好な
絶縁性を確保することができる。さらに、図5に示すよ
うに半導体素子1の配線基板4側の面には導電性粒子6
を含まない接着剤のみの層14を構成することにより、
隣接する電極2同士の間に導電性粒子6を介して導通チ
ャネルができるのを確実に防止するので、半導体素子1
の配線基板4側の面に形成された電極2間で絶縁信頼性
が劣化するのを防止できる。
Also in the present embodiment, since the cross-sectional area of each protruding electrode 3 is formed to be smaller than the cross-sectional area of the electrode 2 formed on the semiconductor element 1, the distance between the electrodes 2 is small. Even when the distance B is short, the distance A between the protruding electrodes 3 used for connection with the electrodes 5 on the wiring board 4 can be large. Therefore, in the layer 7 of the anisotropic conductive adhesive, the conductive particles 6 are prevented from coming into contact with each other or rubbing each other between the projecting electrodes 3, and good insulation between the projecting electrodes 3 is secured. can do. Further, as shown in FIG. 5, conductive particles 6 are provided on the surface of semiconductor element 1 on the side of wiring substrate 4.
By forming the layer 14 of only the adhesive not containing
Since a conductive channel is reliably prevented from being formed between the adjacent electrodes 2 via the conductive particles 6, the semiconductor element 1
The deterioration of insulation reliability between the electrodes 2 formed on the surface on the side of the wiring board 4 can be prevented.

【0031】実施の形態6.図6は、本発明の実施の形
態6による製造方法を示す断面図である。図において、
1は半導体素子、2は半導体素子1上に形成された電
極、3は突起電極、4は配線基板、5は配線基板4上に
形成された電極、6は導電性粒子、7は導電性粒子6を
含む異方性導電接着剤の層、14は異方性導電接着剤の
層7と同一の接着剤を用いているが導電性粒子6は含ま
ない接着剤のみの層である。図6(a)は、突起電極3
を形成した半導体素子1の表面に導電性粒子6のない接
着剤のみの層14を形成した状態を示す。図6(b)
は、配線基板4の上に異方性導電接着剤の層7を形成し
た状態を示す。図6(c)は、異方性導電接着剤の層7
を形成した配線基板4に対して導電性粒子6のない接着
剤のみの層14を形成した半導体素子1を押し付けて加
熱し、半導体素子1の突起電極3と配線基板4上の電極
5との導通をとると同時に、導電性粒子6のない接着剤
のみの層14と異方性導電接着剤の層7を加熱して硬化
した状態を示す。
Embodiment 6 FIG. FIG. 6 is a sectional view showing the manufacturing method according to the sixth embodiment of the present invention. In the figure,
1 is a semiconductor element, 2 is an electrode formed on the semiconductor element 1, 3 is a protruding electrode, 4 is a wiring board, 5 is an electrode formed on the wiring board 4, 6 is conductive particles, and 7 is conductive particles. The layer 14 of an anisotropic conductive adhesive containing 6 uses the same adhesive as the layer 7 of anisotropic conductive adhesive, but is a layer of only the adhesive not containing the conductive particles 6. FIG. 6A shows the projection electrode 3.
1 shows a state in which a layer 14 made of only an adhesive without conductive particles 6 is formed on the surface of the semiconductor element 1 on which is formed. FIG. 6 (b)
Shows a state in which a layer 7 of an anisotropic conductive adhesive is formed on the wiring board 4. FIG. 6C shows the layer 7 of the anisotropic conductive adhesive.
The semiconductor element 1 on which the layer 14 of only the adhesive without the conductive particles 6 is formed is pressed against the wiring board 4 on which the conductive particles 6 are formed, and heated. This shows a state in which the layer 14 made of only the adhesive without the conductive particles 6 and the layer 7 made of the anisotropic conductive adhesive are cured by heating while conducting.

【0032】このように、あらかじめ半導体素子1の表
面に導電性粒子6のない接着剤のみの層14を形成して
おくことにより、導電性粒子6のある異方性導電接着剤
の層7と導電性粒子6のない接着剤のみの層14を完全
に分離することが可能となり、配線基板4に半導体素子
1を押し付け加熱して接着剤を硬化する際に、接着剤が
軟化して流動し、導電性粒子6が半導体素子1上の電極
2の間に存在することを完全に防止することができる。
従って、本実施の形態による半導体装置の製造方法よれ
ば、半導体素子1上の隣接する電極2同士の間に導電性
粒子6を介して導通チャネルができるのを防止し、半導
体素子1の配線基板4側の面に形成された電極2の間で
絶縁信頼性が劣化するのを防止できる半導体装置を実現
することができる。
As described above, by forming the layer 14 of only the adhesive without the conductive particles 6 on the surface of the semiconductor element 1 in advance, the layer 7 of the anisotropic conductive adhesive with the conductive particles 6 is formed. It becomes possible to completely separate the layer 14 containing only the adhesive without the conductive particles 6, and when the semiconductor element 1 is pressed against the wiring board 4 and heated to cure the adhesive, the adhesive softens and flows. In addition, the presence of the conductive particles 6 between the electrodes 2 on the semiconductor element 1 can be completely prevented.
Therefore, according to the method of manufacturing a semiconductor device according to the present embodiment, a conductive channel is prevented from being formed between the adjacent electrodes 2 on the semiconductor element 1 via the conductive particles 6, and the wiring substrate of the semiconductor element 1 is formed. It is possible to realize a semiconductor device capable of preventing insulation reliability from being deteriorated between the electrodes 2 formed on the surface on the fourth side.

【0033】[0033]

【発明の効果】この発明によれば、電極上に該電極より
小さな断面積の突起電極を有する半導体素子と、突起電
極と対向する位置に配設された電極を有する配線基板
と、半導体素子と配線基板との間に形成され、突起電極
とこれに対向する前記配線基板上の電極とを導通させる
異方性導電接着剤の層とを備えたので、微細な電極間隔
を有した半導体素子の配線基板への接続において、突起
電極間の距離を大きくすることができ、良好な絶縁性を
確保し、かつ良好な導通を可能にすることができる半導
体装置を提供できるという効果がある。
According to the present invention, there is provided a semiconductor device having a protruding electrode having a smaller cross-sectional area on an electrode, a wiring board having an electrode disposed at a position facing the protruding electrode, and a semiconductor device comprising: Since the semiconductor device has a fine electrode spacing, the semiconductor device includes a protruding electrode and a layer of an anisotropic conductive adhesive that conducts between the protruding electrode and an electrode on the wiring substrate facing the protruding electrode. In connection to a wiring board, there is an effect that a distance between the protruding electrodes can be increased, a good insulating property can be ensured, and a semiconductor device capable of achieving good conduction can be provided.

【0034】また、この発明によれば、電極上に該電極
より小さな断面積の突起電極を有する半導体素子と、突
起電極と対向する位置に配設された電極を有する配線基
板と、半導体素子と配線基板との間に形成された複数層
の接着剤の層とを備えた半導体装置であって、複数層の
接着剤の層は、半導体素子の側にあって導電粒子を含ま
ない接着剤の層と配線基板の側にあって突起電極とこれ
に対向する配線基板上の電極とを導通させる異方性導電
接着剤の層とで構成することにより、突起電極間の良好
な絶縁性を確保し、かつ、半導体素子の隣接する電極同
士の間に導電性粒子を介して導通チャネルができるのを
確実に防止することができるので、絶縁性の非常に良好
な半導体装置を実現できるという効果がある。
According to the present invention, a semiconductor element having a protruding electrode having a smaller cross-sectional area on an electrode, a wiring board having an electrode disposed at a position facing the protruding electrode, and a semiconductor element are provided. A plurality of adhesive layers formed between the wiring board and the wiring board, wherein the plurality of adhesive layers are formed of an adhesive that does not contain conductive particles on the side of the semiconductor element. Good insulation between the protruding electrodes is ensured by forming the protruding electrodes on the side of the layer and the wiring board and a layer of an anisotropic conductive adhesive that conducts between the protruding electrodes and the electrodes on the wiring board facing the protruding electrodes. In addition, since a conductive channel can be reliably prevented from being formed between adjacent electrodes of the semiconductor element via conductive particles, an effect of realizing a semiconductor device having very good insulating properties can be achieved. is there.

【0035】また、この発明によれば、その配線基板は
微細な配線が可能なガラス基板を用いるので、良好な絶
縁性を確保し、かつ、実装密度の向上を図ることのでき
る半導体装置を実現できるという効果がある。また、こ
の発明によれば、その配線基板はプリント基板と樹脂材
で形成された配線層とを積層したので、良好な絶縁性を
確保し、かつ、実装密度の向上と軽量化を図った半導体
装置を実現できるという効果がある。また、この発明に
よれば、その配線基板は可とう性を有した樹脂材で構成
された配線層を用いたので、良好な絶縁性を確保し、か
つ、長期間にわたる接続の信頼性の向上が図れる半導体
装置を実現することができるという効果がある。
Further, according to the present invention, a glass substrate capable of fine wiring is used as the wiring substrate, thereby realizing a semiconductor device capable of ensuring good insulating properties and improving the mounting density. There is an effect that can be. Further, according to the present invention, since the printed circuit board is formed by laminating a printed circuit board and a wiring layer formed of a resin material, a semiconductor that ensures good insulating properties, and has an improved mounting density and reduced weight. There is an effect that the device can be realized. Further, according to the present invention, since the wiring board uses the wiring layer made of a flexible resin material, good insulation is ensured, and the reliability of connection over a long period is improved. There is an effect that a semiconductor device that can achieve the above can be realized.

【0036】また、この発明によれば、半導体素子の電
極上に該電極より小さな断面積を有する突起電極をボー
ルボンダで形成する工程を有しているので、突起電極の
形成は写真製版やめっきなどの複雑な工程を不要とし、
生産効率のよい半導体装置の製造方法を提供できるとい
う効果がある。
Further, according to the present invention, since a step of forming a projecting electrode having a smaller cross-sectional area than the electrode on the electrode of the semiconductor element by using a ball bonder, it is possible to form the projecting electrode by photolithography or plating. Eliminates the need for complicated processes such as
There is an effect that a method for manufacturing a semiconductor device with high production efficiency can be provided.

【0037】また、この発明によれば、電極上に該電極
より小さな断面積の突起電極を有する半導体素子の表面
に導電粒子を含まない接着剤の層を形成する工程と、異
方性導電接着剤の層を配線基板上の電極および配線が形
成された面に形成する工程と、導電粒子を含まない接着
剤の層が形成された半導体素子と異方性導電接着剤の層
が形成された配線基板とを押し付けて接着する工程とを
有しているので、半導体素子の隣接する電極同士の間に
導電性粒子を介して導通チャネルができるのを確実に防
止することができ、絶縁性の非常に良好な半導体装置の
製造方法を提供できるという効果がある。
According to the invention, a step of forming an adhesive layer containing no conductive particles on a surface of a semiconductor element having a protruding electrode having a smaller cross-sectional area than the electrode is provided on the electrode. Forming a layer of the agent on the surface of the wiring substrate on which the electrodes and the wiring are formed; and forming a semiconductor element having a layer of an adhesive containing no conductive particles and a layer of an anisotropic conductive adhesive. And a step of pressing and adhering to the wiring substrate, so that it is possible to reliably prevent a conductive channel from being formed between adjacent electrodes of the semiconductor element via conductive particles, and to provide an insulating property. There is an effect that a very good method for manufacturing a semiconductor device can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態1による半導体装置の構成
を示す断面図である。
FIG. 1 is a sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention;

【図2】本発明の実施の形態2による半導体装置の構成
を示す断面図である。
FIG. 2 is a sectional view illustrating a configuration of a semiconductor device according to a second embodiment of the present invention;

【図3】本発明の実施の形態3による半導体装置の構成
を示す断面図である。
FIG. 3 is a sectional view illustrating a configuration of a semiconductor device according to a third embodiment of the present invention;

【図4】本発明の実施の形態4による半導体装置の製造
方法を説明するための図である。
FIG. 4 is a view illustrating a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

【図5】本発明の実施の形態5による半導体装置の構成
を示す断面図である。
FIG. 5 is a sectional view showing a configuration of a semiconductor device according to a fifth embodiment of the present invention.

【図6】本発明の実施の形態6による半導体装置の製造
方法を説明するための図である。
FIG. 6 is a view illustrating a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention.

【図7】従来の半導体装置の構成を示す断面図である。FIG. 7 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

【図8】従来の半導体装置の構成を示す断面図である。FIG. 8 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

【図9】異方性導電接着剤を用いた従来の半導体装置の
構成を示す断面図である。
FIG. 9 is a cross-sectional view showing a configuration of a conventional semiconductor device using an anisotropic conductive adhesive.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 半導体素子上の電極 3
突起電極 4 配線基板 5 配線基板上の電極 6
導電性粒子 7 異方性導電接着剤の層 8 配線層 9
導電リード 10 配線基板の凹部 11 絶縁層 12
導体層 13 突起 14 接着剤のみの層 15
プリント基板 16 配線パターン 21 導電性接着剤 22
封止剤 23 はんだ
Reference Signs List 1 semiconductor element 2 electrode on semiconductor element 3
Protruding electrode 4 Wiring board 5 Electrode on wiring board 6
Conductive particles 7 anisotropic conductive adhesive layer 8 wiring layer 9
Conductive lead 10 concave portion of wiring board 11 insulating layer 12
Conductive layer 13 Protrusion 14 Adhesive only layer 15
Printed circuit board 16 Wiring pattern 21 Conductive adhesive 22
Sealant 23 Solder

───────────────────────────────────────────────────── フロントページの続き (72)発明者 石崎 光範 東京都千代田区丸の内二丁目2番3号 三 菱電機株式会社内 (72)発明者 北村 洋一 東京都千代田区丸の内二丁目2番3号 三 菱電機株式会社内 (72)発明者 長嶺 高宏 東京都千代田区丸の内二丁目2番3号 三 菱電機株式会社内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Mitsunori Ishizaki 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Inventor Yoichi Kitamura 2-3-2 Marunouchi, Chiyoda-ku, Tokyo (72) Inventor Takahiro Nagamine 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 電極上に該電極より小さな断面積の突起
電極を有する半導体素子と、 前記突起電極と対向する位置に配設された電極を有する
配線基板と、 前記半導体素子と前記配線基板との間に形成され、前記
突起電極とこれに対向する前記配線基板上の電極とを導
通させる異方性導電接着剤の層とを備えたことを特徴と
する半導体装置。
A semiconductor element having a protruding electrode having a smaller cross-sectional area than the electrode, a wiring board having an electrode disposed at a position facing the protruding electrode, the semiconductor element and the wiring board, And a layer of an anisotropic conductive adhesive formed between the protruding electrodes and an electrode on the wiring board facing the protruding electrodes.
【請求項2】 電極上に該電極より小さな断面積の突起
電極を有する半導体素子と、 前記突起電極と対向する位置に配設された電極を有する
配線基板と、 前記半導体素子と前記配線基板との間に形成された複数
層の接着剤の層とを備えた半導体装置であって、 前記複数層の接着剤の層は、前記半導体素子の側にあっ
て導電粒子を含まない接着剤の層と前記配線基板の側に
あって前記突起電極とこれに対向する前記配線基板上の
電極とを導通させる異方性導電接着剤の層とで構成され
ていることを特徴とする半導体装置。
2. A semiconductor element having a projecting electrode having a smaller cross-sectional area than an electrode on an electrode, a wiring board having an electrode disposed at a position facing the projecting electrode, the semiconductor element and the wiring board, A plurality of layers of adhesive formed between the plurality of layers of the adhesive, wherein the plurality of layers of the adhesive are on the side of the semiconductor element, the layer of the adhesive containing no conductive particles And a layer of an anisotropic conductive adhesive on the side of the wiring board, which electrically connects the protruding electrode to an electrode on the wiring board facing the protruding electrode.
【請求項3】 配線基板は、ガラス基板であることを特
徴とする請求項1または2記載の半導体装置。
3. The semiconductor device according to claim 1, wherein the wiring substrate is a glass substrate.
【請求項4】 配線基板は、プリント基板と樹脂材で形
成された配線層とを積層したものであることを特徴とす
る請求項1または2記載の半導体装置。
4. The semiconductor device according to claim 1, wherein the wiring board is formed by laminating a printed board and a wiring layer formed of a resin material.
【請求項5】 配線基板は、可とう性を有した樹脂材で
構成された配線層であることを特徴とする請求項1また
は2記載の半導体装置。
5. The semiconductor device according to claim 1, wherein the wiring board is a wiring layer made of a resin material having flexibility.
【請求項6】 半導体素子の電極上に該電極より小さな
断面積を有する突起電極をボールボンダで形成する工程
と、 異方性導電接着剤を配線基板上の電極および配線が形成
された面に接着する工程と、 前記突起電極を前記異方性導電接着剤を介して前記配線
基板の電極に押し付ける工程とを有したことを特徴とす
る半導体装置の製造方法。
6. A step of forming a projecting electrode having a smaller cross-sectional area than an electrode on an electrode of a semiconductor element by a ball bonder, and applying an anisotropic conductive adhesive to a surface of the wiring substrate on which the electrode and the wiring are formed. A method of manufacturing a semiconductor device, comprising: a step of bonding; and a step of pressing the protruding electrode against an electrode of the wiring board via the anisotropic conductive adhesive.
【請求項7】 電極上に該電極より小さな断面積の突起
電極を有する半導体素子の表面に導電粒子を含まない接
着剤の層を形成する工程と、 異方性導電接着剤の層を配線基板上の電極および配線が
形成された面に形成する工程と、 前記導電粒子を含まない接着剤の層が形成された半導体
素子と異方性導電接着剤の層が形成された配線基板とを
押し付けて接着する工程とを有したことを特徴とする半
導体装置の製造方法。
7. A step of forming an adhesive layer containing no conductive particles on a surface of a semiconductor element having a projecting electrode having a smaller cross-sectional area than the electrode on the electrode; Forming the upper electrode and the wiring on the surface on which the wiring is formed; pressing the semiconductor element on which the adhesive layer not containing the conductive particles is formed and the wiring substrate on which the anisotropic conductive adhesive layer is formed; And bonding the semiconductor device.
JP27605396A 1996-10-18 1996-10-18 Semiconductor device and manufacturing method thereof Pending JPH10125725A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27605396A JPH10125725A (en) 1996-10-18 1996-10-18 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27605396A JPH10125725A (en) 1996-10-18 1996-10-18 Semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JPH10125725A true JPH10125725A (en) 1998-05-15

Family

ID=17564143

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27605396A Pending JPH10125725A (en) 1996-10-18 1996-10-18 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH10125725A (en)

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WO2000002244A1 (en) * 1998-07-01 2000-01-13 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board, and electronic device
WO2000033375A1 (en) * 1998-12-02 2000-06-08 Seiko Epson Corporation Anisotropic conductor film, semiconductor chip, and method of packaging
US7007834B2 (en) * 2000-12-20 2006-03-07 PAC Tech—Packaging Technologies GmbH Contact bump construction for the production of a connector construction for substrate connecting surfaces
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US6426566B1 (en) 1998-12-02 2002-07-30 Seiko Epson Corporation Anisotropic conductor film, semiconductor chip, and method of packaging
WO2000033375A1 (en) * 1998-12-02 2000-06-08 Seiko Epson Corporation Anisotropic conductor film, semiconductor chip, and method of packaging
US7042644B2 (en) 1998-12-10 2006-05-09 Seiko Epson Corporation Optical substrate and display device using the same
US7007834B2 (en) * 2000-12-20 2006-03-07 PAC Tech—Packaging Technologies GmbH Contact bump construction for the production of a connector construction for substrate connecting surfaces
CN100339966C (en) * 2004-05-11 2007-09-26 友达光电股份有限公司 Two-dimensional display
JP2008244290A (en) * 2007-03-28 2008-10-09 Cmk Corp Multilayer printed wiring board
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