JP2000286293A - Semiconductor device and circuit board for mounting semiconductor element - Google Patents

Semiconductor device and circuit board for mounting semiconductor element

Info

Publication number
JP2000286293A
JP2000286293A JP11087178A JP8717899A JP2000286293A JP 2000286293 A JP2000286293 A JP 2000286293A JP 11087178 A JP11087178 A JP 11087178A JP 8717899 A JP8717899 A JP 8717899A JP 2000286293 A JP2000286293 A JP 2000286293A
Authority
JP
Japan
Prior art keywords
film
anisotropic conductive
conductive film
circuit board
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11087178A
Other languages
Japanese (ja)
Inventor
Yuji Hotta
祐治 堀田
Yoshio Yamaguchi
美穂 山口
Akiko Matsumura
亜紀子 松村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Priority to JP11087178A priority Critical patent/JP2000286293A/en
Priority to US09/537,690 priority patent/US6538309B1/en
Publication of JP2000286293A publication Critical patent/JP2000286293A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/01005—Boron [B]
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    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
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    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To further improve productivity in a mounting process in connecting a semiconductor element and a circuit board via an anisotropic conductive film. SOLUTION: A semiconductor element 1 and an anisotropic film 2 are integrally jointed, and a semiconductor device is formed. The end parts of the conduction paths 21 of a film 2 are brought into contact with the respective electrodes 11 of the element 1, or they are jointed. Then, the semiconductor device where electrical connection with an outer part is realized via the film 2 is obtained. In a mounting substrate, a circuit board and the anisotropic conductive film are integrally jointed, and a bear chip can be mounted through the film. The anisotropic conductive film 2 has a structure, where plural metallic conductors 21 are installed in a film substrate 22 formed of insulating resin in a state where the conductors 21 are mutually insulated and in a state, where they pass through the film substrate in a thickness direction as the conduction paths.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、ベアチップ状態で
の半導体素子を回路基板に接続する技術分野に属し、そ
の実装性向上のための新たなる半導体装置および回路基
板に関するものである。The present invention belongs to the technical field of connecting a semiconductor element in a bare chip state to a circuit board, and relates to a new semiconductor device and a circuit board for improving its mountability.

【０００２】[0002]

【従来の技術】ＩＣなどの半導体素子は、通常、ウエハ
上に多数形成された後、個々のチップに分断され、回路
基板に接続されて用いられる。ＩＣのさらなる大規模な
集積化によって、１つのチップ上に形成される電極数は
増大し、電極の形状や配置パターンは、より微細で狭ピ
ッチなものとなっている。また、実装技術の面では、チ
ップと回路基板との接続にワイヤーで橋渡しする方法を
用いず、チップの電極位置に、回路基板の導体部分を対
応させて両者を接続する方法（例えば、フリップチップ
ボンディング）が用いられるようになっている。また、
接続法とも関連して、チップを裸のまま基板に実装して
用いるベアチップ実装が行われるようになっている。2. Description of the Related Art Normally, a large number of semiconductor devices such as ICs are formed on a wafer, then divided into individual chips, and used by being connected to a circuit board. Due to the further large-scale integration of ICs, the number of electrodes formed on one chip has increased, and the shapes and arrangement patterns of the electrodes have become finer and narrower in pitch. Also, in terms of mounting technology, a method of connecting the chip and the circuit board with a conductor portion of the circuit board corresponding to the electrode position of the chip without using a method of bridging with a wire (for example, a flip chip) Bonding) is used. Also,
In connection with the connection method, a bare chip mounting method is used in which a chip is mounted on a substrate while being bare.

【０００３】上記のように、チップの電極と、回路基板
の導体部分とを対応させて接続する際の接続法の１つと
して、チップと回路基板との間に異方導電性フィルムを
介在させる方法が挙げられる。As described above, as one of the connecting methods for connecting the electrodes of the chip and the conductors of the circuit board in a corresponding manner, an anisotropic conductive film is interposed between the chip and the circuit board. Method.

【０００４】異方導電性フィルムは、導電性について異
方性を示すフィルムであり、フィルムの表裏を貫通する
方向には導電性を示すが、フィルムの面が拡張する方向
には絶縁性を示すものである。[0004] An anisotropic conductive film is a film exhibiting anisotropy in conductivity, showing conductivity in a direction penetrating the front and back of the film, but showing insulation in a direction in which the surface of the film expands. Things.

【０００５】[0005]

【発明が解決しようとする課題】異方導電性フィルムを
介してチップを実装するには、チップ、異方導電性フィ
ルム、回路基板の３者を重ね合わせ、互いに位置合せし
たうえで、チップと異方導電性フィルムとの接合、異方
導電性フィルムと回路基板との接合を一度に行わねばな
らない。しかし、３者を一度に位置合せするには高度な
位置合せ技術が必要であり、単純なチップ実装装置をそ
のまま用いることができず、実装工程での生産性が低い
という問題があった。In order to mount a chip via an anisotropic conductive film, a chip, an anisotropic conductive film, and a circuit board are superimposed, aligned with each other, and then mounted on the chip. The bonding with the anisotropic conductive film and the bonding between the anisotropic conductive film and the circuit board must be performed at one time. However, in order to align the three members at once, a high-level alignment technique is required, and a simple chip mounting apparatus cannot be used as it is, and there is a problem that productivity in a mounting process is low.

【０００６】本発明の課題は上記問題を解決し、半導体
素子と回路基板とを異方導電性フィルムを介して接続す
る際の、実装工程における生産性をさらに向上させるこ
とにある。An object of the present invention is to solve the above-mentioned problem and to further improve the productivity in a mounting step when a semiconductor element and a circuit board are connected via an anisotropic conductive film.

【０００７】[0007]

【課題を解決するための手段】上記課題は、次の態様に
よって解決される。 （１）絶縁性樹脂からなるフィルム基板中に、金属導線
が互いに絶縁された状態で且つ該フィルム基板を厚み方
向に貫通した状態で、導通路として複数設けられた構造
を有する異方導電性フィルムが、半導体素子の電極面に
接合され、半導体素子の各電極が、異方導電性フィルム
中の導通路を介して外部との電気的な接続が可能な状態
とされていることを特徴とする半導体装置。The above object is attained by the following mode. (1) An anisotropic conductive film having a structure in which a plurality of conductive paths are provided in a film substrate made of an insulating resin in a state where metal conductive wires are insulated from each other and penetrate the film substrate in a thickness direction. Is bonded to the electrode surface of the semiconductor element, and each electrode of the semiconductor element is in a state where it can be electrically connected to the outside via conduction paths in the anisotropic conductive film. Semiconductor device.

【０００８】（２）絶縁性樹脂からなるフィルム基板中
に、金属導線が互いに絶縁された状態で且つ該フィルム
基板を厚み方向に貫通した状態で、導通路として複数設
けられた構造を有する異方導電性フィルムが、ウエハ上
に形成された複数の半導体素子の全ての電極面に接合さ
れ、半導体素子の各電極が、異方導電性フィルム中の導
通路を介して外部との電気的な接続が可能な状態とされ
ていることを特徴とする半導体装置。(2) Anisotropically having a structure in which a plurality of conductive paths are provided in a film substrate made of an insulating resin in a state where metal wires are insulated from each other and penetrate the film substrate in the thickness direction. A conductive film is bonded to all electrode surfaces of a plurality of semiconductor elements formed on a wafer, and each electrode of the semiconductor element is electrically connected to the outside through a conductive path in the anisotropic conductive film. A semiconductor device, wherein the semiconductor device is in a state in which it can be operated.

【０００９】（３）半導体素子の電極と、異方導電性フ
ィルムの導通路の端部とが、接触または接合の状態とさ
れており、この接触または接合の状態とされている部分
における、両者の材料の組み合わせが、電極側をアルミ
ニウムとし導通路側を金とする組み合わせ、または電極
側をバリアメタルとし、導通路側を半田とする組み合わ
せである上記（１）または（２）記載の半導体装置。(3) The electrode of the semiconductor element and the end of the conductive path of the anisotropic conductive film are in a contact or a joint state. The semiconductor device according to (1) or (2), wherein the combination of the materials is a combination of aluminum on the electrode side and gold on the conduction path side, or a combination of the electrode side as a barrier metal and the conduction path side as solder.

【００１０】（４）絶縁性樹脂からなるフィルム基板中
に、金属導線が互いに絶縁された状態で且つ該フィルム
基板を厚み方向に貫通した状態で、導通路として複数設
けられた構造を有する異方導電性フィルムが、半導体素
子の電極に対応する導体パターンとして形成された実装
用回路を絶縁性基板の一方の面に有する回路基板の、実
装用回路側の面に接合され、回路基板の実装用回路が、
異方導電性フィルムを介して半導体素子との電気的な接
続が可能な状態とされていることを特徴とする半導体素
子実装用回路基板。(4) Anisotropically having a structure in which a plurality of conductive paths are provided in a film substrate made of an insulating resin in a state where metal wires are insulated from each other and penetrate the film substrate in the thickness direction. A conductive film is bonded to the mounting circuit side surface of the circuit board having a mounting circuit formed as a conductor pattern corresponding to the electrode of the semiconductor element on one surface of the insulating substrate, and is used for mounting the circuit board. The circuit is
A circuit board for mounting a semiconductor element, wherein the circuit board is capable of being electrically connected to a semiconductor element via an anisotropic conductive film.

【００１１】（５）回路基板の実装用回路と異方導電性
フィルムの導通路の端部とが接触または接合の状態とさ
れており、この接触または接合の状態とされている部分
における、両者の材料の組み合わせが、実装用回路側を
半田とし導通路側を金とする組み合わせである上記
（４）記載の半導体素子実装用回路基板。(5) The mounting circuit of the circuit board and the end of the conductive path of the anisotropic conductive film are in contact or joint, and both of the portions in the contact or joint are in contact with each other. (4) The circuit board for mounting a semiconductor element according to the above (4), wherein the combination of the materials is a combination in which the mounting circuit side is solder and the conduction path side is gold.

【００１２】[0012]

【発明の実施の形態】先ず、上記（１）、（２）の態様
である半導体装置について説明する。本発明による上記
（１）の態様の半導体装置は、図１に示すように、ベア
チップ状態（パッシベーション膜を含む裸のチップの状
態）の半導体素子１の電極１１側の面に、後述の異方導
電性フィルム２を一体的に接合し、１つのチップとした
ものである。半導体素子１の各電極１１（図では１１
ａ、１１ｂが現れている）には、異方導電性フィルム２
の導通路２１の端部が、接触または接合の状態で接続さ
れている。例えば、図１では、電極１１ｂには、導通路
２１ａ、２１ｂが対応し、接触または接合の状態となっ
ている。これによって、ベアチップ状態の半導体素子１
は、異方導電性フィルム２を介して外部（特に回路基
板）との電気的な接続が可能な１つの半導体装置となっ
ており、しかも、分断直後のチップと全く同様に扱うこ
とができるようになっている。DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a description will be given of a semiconductor device according to the above embodiments (1) and (2). As shown in FIG. 1, the semiconductor device according to the aspect (1) according to the present invention has an anisotropic structure described later on a surface on the electrode 11 side of the semiconductor element 1 in a bare chip state (a state of a bare chip including a passivation film). The conductive film 2 is integrally joined to form one chip. Each electrode 11 (11 in the figure) of the semiconductor element 1
a and 11b appear), the anisotropic conductive film 2
Are connected in a contact or joint state. For example, in FIG. 1, the conductive paths 21a and 21b correspond to the electrode 11b, and are in a contact or joint state. Thereby, the semiconductor element 1 in a bare chip state
Is a semiconductor device that can be electrically connected to the outside (particularly, a circuit board) via the anisotropic conductive film 2 and can be handled in exactly the same manner as a chip immediately after being cut. It has become.

【００１３】この構成によって、フリップチップボンダ
ーなどの実装装置をそのまま利用できるようになるため
に実装工程における生産性が向上し、チップ、異方導電
性フィルム、回路基板の、３者の接続体が効率良く得ら
れるようになる。また、用いられる異方導電性フィルム
は、後述のように金属導線と絶縁性樹脂とからなる構造
体であり適度な弾性率を有するものであるから、高い接
続信頼性をもって外部との接続が可能なチップである。According to this configuration, since a mounting device such as a flip chip bonder can be used as it is, productivity in a mounting process is improved, and a three-member connection body of a chip, an anisotropic conductive film, and a circuit board is formed. It can be obtained efficiently. In addition, the anisotropic conductive film used is a structure composed of a metal conductor and an insulating resin and has an appropriate elastic modulus as described later, so that it can be connected to the outside with high connection reliability. Is a good chip.

【００１４】本発明の半導体装置の構成要素の１つであ
るベアチップ状態の半導体素子は、異方導電性フィルム
を介して回路基板に実装し得るものであればよいが、１
つの発光素子のような単発的なものよりも、ＣＰＵ、メ
モリー、種々の演算回路を集積したプロセッサなど、多
数の電極が狭ピッチで配置された素子の方が、本発明の
有用性が顕著となる。The bare chip semiconductor element, which is one of the constituent elements of the semiconductor device of the present invention, may be any element that can be mounted on a circuit board via an anisotropic conductive film.
The usefulness of the present invention is more remarkable in an element in which a large number of electrodes are arranged at a narrow pitch, such as a CPU, a memory, and a processor in which various arithmetic circuits are integrated, than a single element such as one light-emitting element. Become.

【００１５】また、本発明でいう半導体装置は、個々に
素子分断されたものだけでなく、ウエハ上に半導体素子
が複数形成されたものに１枚の異方導電性フィルムを接
合したものをも含む。このような半導体装置は、分断前
の中間体であるとみなしてもよいし、分断するしないに
かかわらず、外部との接続が可能な装置であるとみなし
てもよい。このような半導体装置が、上記（２）の態様
である。The semiconductor device according to the present invention is not limited to a device in which a plurality of semiconductor elements are formed on a wafer, but also a device in which a single anisotropic conductive film is joined to the semiconductor device. Including. Such a semiconductor device may be regarded as an intermediate before division, or may be regarded as a device that can be connected to the outside regardless of division. Such a semiconductor device is the aspect of the above (2).

【００１６】本発明の半導体装置を実装すべき相手の回
路基板は、フレキシブルな基板やリジッドな基板など、
当該半導体装置を実装し得る導体部分を有するものであ
ればよい。該回路基板の構造は、ベアチップ状態の半導
体素子を実装できるように、素子の電極パターンに対応
する導体パターンを絶縁性基板の一方の面に少なくとも
有するものであり、基板内部や他方の面に形成された回
路と接続されていたり、リード接点、バンプ接点などを
有するものもある。The circuit board on which the semiconductor device of the present invention is to be mounted may be a flexible board or a rigid board.
What is necessary is just to have the conductor part which can mount the said semiconductor device. The structure of the circuit board has a conductor pattern corresponding to the electrode pattern of the element on at least one surface of the insulating substrate so that the semiconductor element in a bare chip state can be mounted, and is formed on the inside of the substrate or on the other surface. Some are connected to a printed circuit or have a lead contact, a bump contact, or the like.

【００１７】本発明の半導体装置の構成要素の１つであ
る異方導電性フィルムは、図２に単品の状態として示す
ように、絶縁性樹脂からなるフィルム基板２２中に、導
通路２１として金属導線が複数設けられた構造を有する
ものである。導通路同士は、互いに絶縁され、かつフィ
ルム基板２２を厚み方向に貫通した状態とされたもので
ある。The anisotropic conductive film, which is one of the constituent elements of the semiconductor device of the present invention, is formed as a single piece in FIG. It has a structure in which a plurality of conducting wires are provided. The conduction paths are insulated from each other and penetrate the film substrate 22 in the thickness direction.

【００１８】また、図２の態様に対して図３、図４に示
すように、フィルム基板２２の樹脂材料と導通路２１と
の間にさらに他の材料からなる層２３が設けられてもよ
い。このような層は、何層にも重ねて設けてもよく、ま
た、絶縁性、導電性など、用途や求められる特性に応じ
て材料を選択すればよい。例えば、図３において、フィ
ルム基板２２を構成する樹脂材料に接着性の高いものを
用い、導通路２１を取り巻く層２３に耐熱絶縁性の高い
材料を用いるなどの態様が挙げられる。As shown in FIGS. 3 and 4 with respect to the embodiment of FIG. 2, a layer 23 made of another material may be provided between the resin material of the film substrate 22 and the conductive path 21. . Such a layer may be provided in any number of layers, and a material may be selected in accordance with a use or required characteristics such as insulating property and conductivity. For example, in FIG. 3, a mode in which a resin material having high adhesiveness is used for the resin material forming the film substrate 22 and a material having high heat-resistant insulation is used for the layer 23 surrounding the conductive path 21 is exemplified.

【００１９】フィルム基板を構成する絶縁性樹脂として
は、熱硬化性樹脂、熱可塑性樹脂などが挙げられる。例
えば、熱可塑性ポリイミド樹脂、エポキシ樹脂、ポリエ
ーテルイミド樹脂、ポリアミド樹脂、フェノキシ樹脂、
アクリル樹脂、ポリカルボジイミド樹脂、フッ素樹脂、
ポリエステル樹脂、ポリウレタン樹脂、ポリアミドイミ
ド樹脂などが挙げられ、目的に応じて適宜選択される。
これらの樹脂は、単独でもあるいは混合して使用しても
よい。Examples of the insulating resin constituting the film substrate include a thermosetting resin and a thermoplastic resin. For example, thermoplastic polyimide resin, epoxy resin, polyetherimide resin, polyamide resin, phenoxy resin,
Acrylic resin, polycarbodiimide resin, fluororesin,
Examples thereof include a polyester resin, a polyurethane resin, and a polyamideimide resin, which are appropriately selected according to the purpose.
These resins may be used alone or in combination.

【００２０】フィルム基板の厚みは、１０μｍ〜２００
μｍ程度、特に２５μｍ〜１５０μｍ程度が信頼性およ
び薄型化の点で好ましい。The thickness of the film substrate is from 10 μm to 200 μm.
A thickness of about μm, particularly about 25 μm to 150 μm, is preferable in terms of reliability and thickness reduction.

【００２１】導通路を構成する金属導線の材料は、銅、
金、アルミニウム、ニッケルなどが好ましく、特に導電
性の点から、銅、金が好ましい。金属導線のなかでも、
例えばＪＩＳ Ｃ ３１０３に規定された銅線などのよ
うに電気を伝導すべく製造されたものがより好ましく、
電気的特性、機械的特性、さらにはコストの点でも最も
優れた導通路となる。The material of the metal wire constituting the conduction path is copper,
Gold, aluminum, nickel and the like are preferable, and particularly, copper and gold are preferable from the viewpoint of conductivity. Among the metal wires,
For example, those manufactured to conduct electricity, such as copper wires specified in JIS C 3103, are more preferable.
This is the most excellent conduction path in terms of electrical characteristics, mechanical characteristics, and cost.

【００２２】導通路の断面（通路方向と垂直に切断）の
形状、大きさ、数は、チップの電極に応じて適宜選択す
ることができるが、ピッチ５０μｍ以下のようなファイ
ンピッチの電極配置パターンに対応するには、外径５〜
３０μｍとすることが好ましい。上記の条件を満たせ
ば、導通路の断面形状は、円形や、多角形など、どのよ
うな形状であってもよい。チップの１つの電極には、１
個〜３個程度の複数の導通路を対応させるのが好まし
い。The shape, size and number of the cross section of the conductive path (cut perpendicular to the direction of the path) can be appropriately selected according to the electrode of the chip, but the electrode arrangement pattern having a fine pitch of 50 μm or less. In order to respond to
It is preferably 30 μm. As long as the above conditions are satisfied, the cross-sectional shape of the conduction path may be any shape such as a circle or a polygon. One electrode of the chip has 1
Preferably, a plurality of about three to three conducting paths are made to correspond.

【００２３】フィルム基板の面に対して、導通路の端部
は、突起していても、窪んでいても、フィルム面と同一
面でもよく、これらの状態が混在していてもよい。ま
た、フィルム基板の一方の面では、導通路が突起し、他
方の面では窪んでいるなどの態様でもよく、組み合わせ
は自由である。導通路の端部の凹凸の態様は、接合すべ
きチップの電極に応じて、また、実装相手の回路基板に
応じて選択すればよい。通常、チップの電極、および実
装相手の回路基板の導体部分は、微小な凹状を呈するパ
ッドの場合が多いため、図２（ｂ）に示すように、フィ
ルム基板の両方の面ともに導通路が突起した態様が、信
頼性の高い接続のためには好ましい。With respect to the surface of the film substrate, the end of the conduction path may be protruded or depressed, may be flush with the film surface, or a mixture of these states. Further, the conductive path may be protruded on one surface of the film substrate, and may be depressed on the other surface, and the combination is free. The shape of the unevenness at the end of the conduction path may be selected according to the electrode of the chip to be joined and according to the circuit board to be mounted. In general, the electrodes of the chip and the conductors of the circuit board to be mounted are often pads having a minute concave shape. Therefore, as shown in FIG. This embodiment is preferable for highly reliable connection.

【００２４】フィルム面から導通路の端部を突起させる
場合の突起量は、０．０１μｍ〜５μｍ程度、特に０．
１μｍ〜２μｍ程度が接続信頼性の点で好ましい。フィ
ルム基板の面から導通路の端部を突起させる方法は、後
述のとおりである。When projecting the end of the conductive path from the film surface, the amount of projection is about 0.01 μm to 5 μm, especially about 0.1 μm.
About 1 μm to 2 μm is preferable in view of connection reliability. The method of projecting the end of the conduction path from the surface of the film substrate is as described below.

【００２５】導通路の端部の表面は、導通性が高い金属
材料や耐腐食性に優れた金やニッケルなどの材料でさら
に被覆してもよい。また、導通路の材料、特に半導体素
子側の端部を被覆する材料は、半導体素子の電極の表面
の材料に応じて、好ましいものを選択すればよい。例え
ば、アルミニウム（電極側）と金（導通路側）、バリア
メタル（電極側）と半田（導通路側）などの組み合わせ
が挙げられる。バリアメタルは、素子内の配線材料とし
て用いられるＡｌと、外部の金属との拡散反応を防止す
る層を構成すべく用いられる金属であって、Ｃｒ、Ａ
ｕ、Ｎｉ等の単体および合金などが挙げられる。The surface of the end of the conduction path may be further covered with a highly conductive metal material or a material such as gold or nickel having excellent corrosion resistance. Further, as the material of the conduction path, particularly, the material for covering the end portion on the semiconductor element side, a preferable material may be selected according to the material of the surface of the electrode of the semiconductor element. For example, a combination of aluminum (electrode side) and gold (conducting path side), barrier metal (electrode side) and solder (conducting path side), and the like can be given. The barrier metal is a metal used to form a layer for preventing a diffusion reaction between Al used as a wiring material in the device and an external metal, and includes Cr, A
Simple substances such as u and Ni, and alloys are exemplified.

【００２６】導通路は、フィルム基板内により密に配列
されるのがよい。フィルム面を見たときの導通路の配列
のパターンは、図２（ａ）に示すような最密状、図４に
示すような正方行列状、その他、ランダムな密集状態で
あってもよいが、微細な電極に対応するには最密状が好
ましい。The conducting paths are preferably arranged more densely in the film substrate. The pattern of the arrangement of the conductive paths when looking at the film surface may be a close-packed shape as shown in FIG. 2A, a square matrix as shown in FIG. 4, or a random dense state. In order to cope with fine electrodes, the densest shape is preferable.

【００２７】金属導線が導通路としてフィルム基板を多
数貫通した構造のものを得るには、多数の絶縁電線を密
に束ねた状態で互いに分離できないように固定し、各絶
縁電極と角度をなす面を切断面として、所望のフィルム
厚さにスライスする方法が挙げられる。なかでも、本発
明の異方導電性フィルムの製造方法として最も好ましい
ものとしては、次のの工程またはの工
程を有する製造方法が挙げられる。In order to obtain a structure in which metal wires penetrate a large number of film substrates as conduction paths, a large number of insulated wires are tightly bundled and fixed so that they cannot be separated from each other. Is used as a cut surface, and a method of slicing to a desired film thickness is exemplified. Among them, the most preferable method for producing the anisotropic conductive film of the present invention is a production method having the following steps or steps.

【００２８】導通路の直径（例えば、１０〜５０μ
ｍ）を有する金属導線の表面に、絶縁性樹脂からなる被
覆層を１層以上形成して絶縁導線とし、これを芯材に巻
線する工程。 上記巻線によって得られたコイルを加熱および／また
は加圧して、巻き付けられた絶縁導線の被覆層どうしを
融着および／または圧着させて一体化しコイルブロック
を形成する工程。 前記の工程で得られたコイルブロックを、巻きつけ
られた絶縁導線と角度をなして交差する平面を断面とし
て所定のフィルム厚さに切断する工程。 上記で得られたフィルム状物の絶縁性樹脂の部分を
エッチングし、金属導線をフィルム面から突起させる工
程。 上記で得られたフィルム状物のフィルム面に露出し
ている金属導線の端面にさらに金属を堆積させて、フィ
ルム面から突起させる工程。The diameter of the conduction path (for example, 10 to 50 μm)
m) forming at least one coating layer made of an insulating resin on the surface of the metal conductor having the above structure to form an insulated conductor, and winding this around a core material. A step of heating and / or pressurizing the coil obtained by the winding, and fusing and / or crimping the wound coating layers of the insulated conductor to integrate them to form a coil block. A step of cutting the coil block obtained in the above step into a predetermined film thickness with a plane intersecting at an angle with the wound insulated conducting wire as a cross section. A step of etching the insulating resin portion of the film-like material obtained above to project the metal conductor from the film surface. A step of further depositing a metal on the end face of the metal wire exposed on the film surface of the film-like product obtained above and projecting the metal wire from the film surface.

【００２９】上記〜の工程は、絶縁電線を最も効率
よく密に束ねることができ、かつ、図２（ａ）に示すよ
うな導通路の最密な集合パターンを容易に得ることがで
きる方法である。上記〜の工程の後に、導通路を突
起させる方法によって、上記またはの工程を選択し
加えればよい。The above steps (1) to (3) are methods in which insulated wires can be bundled most efficiently and densely, and a dense pattern of conducting paths as shown in FIG. 2 (a) can be easily obtained. is there. After the above steps (1) to (4), the above steps or the above steps may be selected and added depending on the method of projecting the conduction path.

【００３０】上記の製造方法によれば、金属導線の表面
に形成した被覆層が、最後にはフィルム基板となる。金
属導線の表面に被覆層を形成する際には、絶縁用、接着
用など種々の特性に応じた材料を多層に形成することが
できる。よって、得られた異方導電性フィルムは、導電
性、誘電性、絶縁性、接着性、強度などの種々の電気的
特性、機械的特性が、フィルム面が拡張する方向に変化
するものとなる。上記の製造方法における〜の各工
程については、国際公開公報ＷＯ９８／０７２１６「異
方導電性フィルムおよびその製造方法」に記載の技術を
参照してもよい。According to the above manufacturing method, the coating layer formed on the surface of the metal conductor finally becomes a film substrate. When the coating layer is formed on the surface of the metal conductor, materials corresponding to various characteristics such as insulation and adhesion can be formed in multiple layers. Therefore, the obtained anisotropic conductive film has various electrical and mechanical properties such as conductivity, dielectric properties, insulation properties, adhesiveness, and strength, which change in the direction in which the film surface expands. . About each process of-in the said manufacturing method, you may refer to the technique as described in International Publication WO98 / 07216 "Anisotropic conductive film and its manufacturing method".

【００３１】半導体素子と異方導電性フィルムとを接合
するに際しては、半導体素子の電極に対応する導通路
は、高い信頼性をもってその電極に接続（接触や接合な
ど）されなければならない。そのためには、異方導電性
フィルム全体に適度な弾性が必要である。異方導電性フ
ィルムの全体としての弾性率は、導電性と同様に異方性
を有し、フィルム厚み方向とフィルム面方向とでは異な
る。本発明では、異方導電性フィルムの全体としての好
ましい弾性率を、フィルム面方向について規定し、温度
範囲２５℃〜１２５℃において、０．１〜５ＧＰａとす
ることが、冷熱サイクルを加えられた後の接続信頼性の
面から好ましい。When a semiconductor element is bonded to an anisotropic conductive film, a conductive path corresponding to an electrode of the semiconductor element must be connected to the electrode with high reliability (contact, bonding, etc.). For that purpose, the entire anisotropic conductive film needs to have appropriate elasticity. The elastic modulus of the anisotropic conductive film as a whole has anisotropy as in the case of conductivity, and differs between the film thickness direction and the film surface direction. In the present invention, the preferred elastic modulus of the anisotropic conductive film as a whole is defined in the film surface direction, and in a temperature range of 25 ° C. to 125 ° C., 0.1 to 5 GPa is applied to the cooling and heating cycle. This is preferable from the viewpoint of later connection reliability.

【００３２】異方導電性フィルムの構造全体としての弾
性率を決定する要素としては、導通路の材料、導通路の
断面形状や全長、導通路の配置の密度や配置パターン、
フィルム基板の材料、フィルム基板の厚みなどである。
これらの要素を選択し、上記弾性率の範囲とすればよ
い。The elements that determine the elastic modulus of the entire structure of the anisotropic conductive film include the material of the conductive path, the cross-sectional shape and the total length of the conductive path, the density and the layout pattern of the conductive path, and the like.
The material of the film substrate, the thickness of the film substrate, and the like.
What is necessary is just to select these elements and make it into the said elastic modulus range.

【００３３】電極と導通路との接続状態は、金属同士の
溶着による接合状態であっても、接触しているだけの状
態であってもよく、半導体素子と異方導電性フィルムと
の接合に応じて選択すればよい。半導体素子と異方導電
性フィルムとの接合には、フィルム基板の材料に接着性
を有するものを用いその接着性を利用する接合（電極と
導通路とは接触だけでもよい）、電極と導通路とを溶着
させてその接合力を利用する接合、フィルム基板の材料
に接着性を有するものを用いかつ電極と導通路とを溶着
させる接合、などが挙げられる。The connection state between the electrode and the conductive path may be a connection state by welding of metals or a state where they are only in contact with each other, and may be a connection state between a semiconductor element and an anisotropic conductive film. It should just be selected according to. For bonding the semiconductor element and the anisotropic conductive film, a material having adhesiveness to the material of the film substrate is used, and the bonding utilizing the adhesiveness (the electrode and the conductive path may be in contact only), the electrode and the conductive path And bonding utilizing the bonding force of the film substrate, bonding using a material having adhesiveness to the material of the film substrate and welding the electrode and the conductive path, and the like.

【００３４】接着性を有する材料とは、それ自体がその
ままの状態でまたは加圧されて接着性を示す材料、また
は、そのままの状態では接着性を示さないが加熱（加圧
を伴ってもよい）により接着可能となる材料をいう。後
者の材料としては、熱可塑性樹脂や、熱硬化性樹脂など
が挙げられる。The material having an adhesive property is a material which exhibits an adhesive property as it is or is pressed, or a material which does not exhibit the adhesive property as it is but may be heated (with pressurization). ) Means a material that can be bonded. Examples of the latter material include a thermoplastic resin and a thermosetting resin.

【００３５】半導体素子と異方導電性フィルムとを接合
する場合、素子に対応する大きさの異方導電性フィルム
を１つ１つ接合するという製造方法としてもよいが、ウ
エハ上に形成された状態の複数の半導体素子に、それら
の半導体素子を包含する大きさ（例えば、ウエハと同じ
大きさ）の１枚の異方導電性フィルムを接合し、各素子
の電極とそれらに対応する導通路との接続を確定させた
後で、異方導電性フィルムと共に半導体素子を個々のチ
ップに分断するという製造方法が、最も生産性が高く、
しかも信頼性の高い接合が得られる。また上記したよう
に、そのときの分断前の状態のものを独立した１つの装
置であるとするとき、それが上記（２）の態様の装置で
ある。When a semiconductor element and an anisotropic conductive film are joined, a method of joining anisotropic conductive films of a size corresponding to the element one by one may be used. A single anisotropic conductive film of a size (for example, the same size as a wafer) including the semiconductor elements is joined to the plurality of semiconductor elements in the state, and the electrodes of each element and the corresponding conductive paths After establishing the connection with, the manufacturing method of dividing the semiconductor element into individual chips together with the anisotropic conductive film is the most productive,
Moreover, a highly reliable joint can be obtained. Further, as described above, when the device before the division at that time is regarded as one independent device, it is the device of the above-mentioned (2).

【００３６】次に、上記（４）、（５）の態様である半
導体素子実装用回路基板（以下、「実装用基板」ともよ
ぶ）について説明する。本発明の実装用基板は、図５に
示すように、回路基板３に、異方導電性フィルム２が接
合されたものである。回路基板３は、絶縁性基板３２の
一方の面に実装用回路３１が形成されたものであり、実
装用回路３１は、ベアチップ状態の半導体素子の電極に
対応する導体パターンとして形成されたものである。回
路基板３には、異方導電性フィルム２の導通路２１の端
部が、接触しているかまたは接合されており、異方導電
性フィルム２を介して、チップを回路基板３に実装でき
るようになっている。Next, a description will be given of a circuit board for mounting a semiconductor element (hereinafter, also referred to as a “mounting board”) according to the above embodiments (4) and (5). As shown in FIG. 5, the mounting substrate of the present invention is obtained by joining an anisotropic conductive film 2 to a circuit board 3. The circuit board 3 has a mounting circuit 31 formed on one surface of an insulating substrate 32, and the mounting circuit 31 is formed as a conductor pattern corresponding to an electrode of a semiconductor element in a bare chip state. is there. An end of the conductive path 21 of the anisotropic conductive film 2 is in contact with or bonded to the circuit board 3 so that a chip can be mounted on the circuit board 3 via the anisotropic conductive film 2. It has become.

【００３７】この構成によって、上記（１）の態様の場
合と同様、フリップチップボンダーなどの実装装置をそ
のまま利用できるようになるために実装工程における生
産性が向上し、チップ、異方導電性フィルム、回路基板
の、３者の接続体が効率良く得られるようになる。ま
た、上記（１）の態様の場合と同様、異方導電性フィル
ムの特徴によって、高い接続信頼性をもってチップの実
装が可能な基板となっている。With this configuration, as in the case of the above mode (1), the mounting device such as a flip chip bonder can be used as it is, so that the productivity in the mounting process is improved, and the chip and the anisotropic conductive film can be used. , And a circuit board of the three members can be efficiently obtained. Further, as in the case of the above embodiment (1), the characteristics of the anisotropic conductive film make the substrate on which the chip can be mounted with high connection reliability.

【００３８】本発明の実装用基板を構成する異方導電性
フィルムや回路基板、また、本発明の実装用基板に実装
すべきベアチップ状態の半導体素子などは、上記（１）
の態様の説明で述べたとおりである。また、半導体素
子、異方導電性フィルム、回路基板の３者を好ましく接
合するために規定すべき異方導電性フィルム全体の弾性
率も、上記（１）の態様の説明で述べたものと同様であ
る。異方導電性フィルムと回路基板との接合、導通路と
実装用回路との接続状態は、上記（１）の態様の説明で
述べた異方導電性フィルムと半導体素子との接合、導通
路と電極との接続状態を参照してよい。The anisotropic conductive film and the circuit board constituting the mounting board of the present invention, and the semiconductor element in a bare chip state to be mounted on the mounting board of the present invention are as described in (1) above.
This is as described in the description of the aspect. In addition, the elastic modulus of the entire anisotropic conductive film to be specified for preferably joining the semiconductor element, the anisotropic conductive film, and the circuit board is the same as that described in the description of the above embodiment (1). It is. The connection between the anisotropically conductive film and the circuit board and the connection between the conductive path and the mounting circuit are described in connection with the connection between the anisotropically conductive film and the semiconductor element described in the description of the above embodiment (1). You may refer to the connection state with the electrode.

【００３９】[0039]

【実施例】実施例１ 本実施例では、上記（１）の態様の実例として、ウエハ
上に配列された半導体素子に対して、それらを全てカバ
ーする大面積の異方導電性フィルムを接合し、素子分断
して、本発明の半導体装置を製作した。異方導電性フィ
ルムは、上記で挙げたの工程を含む製造方法に
よって製作した。EXAMPLE 1 In this example, as an example of the above mode (1), a large-area anisotropic conductive film covering all of the semiconductor elements arranged on a wafer was bonded to the semiconductor elements. Then, the semiconductor device of the present invention was manufactured by separating the elements. The anisotropic conductive film was manufactured by a manufacturing method including the steps described above.

【００４０】〔半導体素子〕直径８ｉｎｃｈの円板状の
シリコンウエハ基板上に、１０ｍｍ×１０ｍｍの半導体
素子（集積回路）がマトリクス状に形成されたものを用
いた。該素子の各電極は、平坦なＡｌパッドである。[Semiconductor Element] A semiconductor element (integrated circuit) of 10 mm × 10 mm was formed in a matrix on a disk-shaped silicon wafer substrate having a diameter of 8 inches. Each electrode of the device is a flat Al pad.

【００４１】〔異方導電性フィルム〕半導体素子に接合
する前の、単品としての異方導電性フィルムの仕様は次
のとおりである。構造は、ポリカルボジイミド樹脂から
なるフィルム基板に、直径１８μｍの銅線が貫通した状
態で保持され導通路となっている構造である。フィルム
基板の厚みは６０μｍ、導通路の両端部ともに、フィル
ムの両面から各々突き出した態様である。その突起の量
は、両面共に等しく、各々０．５μｍであり、この突き
出た部分には、さらに厚さ０．１μｍの金メッキを施し
た。よって、個々の導通路のトータル長さは約６１．２
μｍ（＝異方導電性フィルムの総厚み）である。異方導
電性フィルムの外周形状はウエハ基板と同じとし、ウエ
ハ基板上に形成された半導体素子を全てカバーし得るも
のとした。[Anisotropically Conductive Film] The specifications of the anisotropically conductive film as a single product before bonding to the semiconductor element are as follows. The structure is a structure in which a copper wire having a diameter of 18 μm penetrates a film substrate made of a polycarbodiimide resin and is held as a conductive path. The thickness of the film substrate is 60 μm, and both ends of the conduction path are projected from both sides of the film. The amount of the protrusion is the same on both surfaces, each being 0.5 μm, and the protruding portion is further plated with gold having a thickness of 0.1 μm. Therefore, the total length of each conductive path is about 61.2.
μm (= the total thickness of the anisotropic conductive film). The outer peripheral shape of the anisotropic conductive film was the same as that of the wafer substrate, and was able to cover all the semiconductor elements formed on the wafer substrate.

【００４２】異方導電性フィルムの製造工程において巻
線に用いた絶縁導線は、直径１８μｍの銅線の表面に、
ポリカルボジイミド樹脂をコーティングして被覆層とし
たものである。導通路同士は、巻線時の整列巻きによっ
て、図２（ａ）に示すように、ほぼ最密の状態で集合し
ており、隣合った２つの導通路の中心軸線間距離は４０
μｍである。この異方導電性フィルムのフィルム面方向
についての構造全体の弾性率は、３．０ＧＰａであっ
た。The insulated conductive wire used for winding in the process of manufacturing the anisotropic conductive film was formed on the surface of a copper wire having a diameter of 18 μm.
A coating layer is formed by coating a polycarbodiimide resin. As shown in FIG. 2 (a), the conductive paths are gathered in an almost close-packed state by the aligned winding at the time of winding, and the distance between the center axes of two adjacent conductive paths is 40.
μm. The elastic modulus of the entire structure in the film surface direction of the anisotropic conductive film was 3.0 GPa.

【００４３】上記半導体素子がマトリクス状に形成され
たシリコンウエハ基板上に、上記異方導電性フィルムを
載せ、フッ素フィルムでカバーし、オートクレーヴの缶
内に入れ、２００℃、１０ｋｇｆの条件でウエハに異方
導電性フィルムを貼り付けた。この状態が、上記（２）
の態様の半導体装置であって、全ての素子の電極は、異
方導電性フィルムを介して外部との接続が可能な状態と
なっている。The anisotropic conductive film was placed on a silicon wafer substrate on which the semiconductor elements were formed in a matrix, covered with a fluorine film, and placed in an autoclave can at 200 ° C. and 10 kgf. An anisotropic conductive film was attached to the substrate. This state corresponds to the above (2)
In the semiconductor device according to the aspect, the electrodes of all the elements can be connected to the outside via the anisotropic conductive film.

【００４４】得られた上記（２）の態様の半導体装置
（ウエハ上に複数形成された状態の素子に異方導電性フ
ィルムが接合されたもの）を、ダイシングマシンによっ
て、個々の半導体装置（１０ｍｍ×１０ｍｍ）に分断
し、上記（１）の態様の半導体装置を得た。The obtained semiconductor device of the embodiment (2) (in which a plurality of elements formed on a wafer and an anisotropic conductive film joined thereto) is separated into individual semiconductor devices (10 mm in size) by a dicing machine. × 10 mm) to obtain the semiconductor device of the above embodiment (1).

【００４５】得られた上記（１）の態様の半導体装置
は、従来の実装装置であるフリップチップボンダーをそ
のまま利用することによって、相手の回路基板に実装す
ることができた。これによって、〔半導体素子／異方導
電性フィルム／回路基板〕という、異方導電性フィルム
が介在した３層構造の実装体を、高い生産性で組み立て
得ることがわかった。また、異方導電性フィルムが介在
した半導体素子と回路基板との接続状態は、サーマルサ
イクルテスト（−２５℃〜１２５℃）において導通不良
の発生率が０／２００であり、好ましいものであった。The obtained semiconductor device of the embodiment (1) could be mounted on a mating circuit board by directly using a flip chip bonder which is a conventional mounting device. As a result, it has been found that a three-layer package having an anisotropic conductive film interposed therebetween, [semiconductor element / anisotropic conductive film / circuit board], can be assembled with high productivity. Further, the connection state between the semiconductor element and the circuit board with the anisotropic conductive film interposed therebetween was favorable because the rate of conduction failure was 0/200 in a thermal cycle test (−25 ° C. to 125 ° C.). .

【００４６】実施例２ 本実施例では、上記（４）の態様の実例として、チップ
をパッケージに封入するための回路基板（回路の表面に
は厚さ２１μｍの半田メッキを付与）の回路側の面に異
方導電性フィルムを接合し、本発明の実装用基板を製作
した。異方導電性フィルムは、実施例１と同様、上記で
挙げたの工程を含む製造方法によって製作し
た。Embodiment 2 In this embodiment, as an example of the above mode (4), a circuit board for enclosing a chip in a package (a 21 μm-thick solder plating is applied to the surface of the circuit) is provided on the circuit side. An anisotropic conductive film was bonded to the surface to produce a mounting substrate of the present invention. The anisotropic conductive film was manufactured by the manufacturing method including the above-mentioned steps as in Example 1.

【００４７】〔実装対象の半導体素子〕厚さ３７０μ
ｍ、外形１０ｍｍ×１０ｍｍのベアチップ状態の集積回
路である。電極は平坦なＡｌパッドである。[Semiconductor element to be mounted] 370 μm in thickness
m, an integrated circuit in a bare chip state having an outer shape of 10 mm × 10 mm. The electrodes are flat Al pads.

【００４８】〔回路基板〕厚さ１ｍｍのガラスエポキシ
基板（ＦＲ−４）上に、銅からなる回路パターンが形成
されたものである。回路パターンは、上記実装対象とな
る半導体素子の電極に対応する回路パターンとして形成
されている。回路パターンの回路幅は１００μｍ、隣合
った回路間の間隙部分の幅は１００μｍである。[Circuit Board] A circuit pattern made of copper is formed on a glass epoxy board (FR-4) having a thickness of 1 mm. The circuit pattern is formed as a circuit pattern corresponding to the electrode of the semiconductor element to be mounted. The circuit width of the circuit pattern is 100 μm, and the width of the gap between adjacent circuits is 100 μm.

【００４９】〔異方導電性フィルム〕実施例１に用いた
ものと構造上の仕様、製造方法は同じである。当該フィ
ルムの外形は、実装すべきチップの外形を考慮し、１０
ｍｍ×１０ｍｍとした。[Anisotropic Conductive Film] The structural specifications and manufacturing method are the same as those used in Example 1. The external shape of the film should be 10
mm × 10 mm.

【００５０】上記回路基板の実装側の面のうち素子が占
有すべき領域（チップをボンディングする位置）に、上
記異方導電性フィルムを載せ、フリップチップボンダー
で接合し、本発明の実装用基板を得た。このときの接合
条件は、１８０℃、２０秒、荷重２０ｋｇｆである。ま
た、フリップチップボンダーを使用するに際しては、そ
のボンディング機能だけを利用できるように、該ボンダ
ーのヘッド部分（本来、チップに接する部分）に、フッ
素フィルムを貼っておいた。The anisotropic conductive film is placed on a region (position where a chip is to be bonded) occupied by elements on the mounting side of the circuit board, and bonded by a flip chip bonder. I got The joining conditions at this time are 180 ° C., 20 seconds, and a load of 20 kgf. When using a flip chip bonder, a fluorine film was stuck on the head portion of the bonder (the portion that is originally in contact with the chip) so that only the bonding function can be used.

【００５１】上記で得られた実装用基板に対して、上記
ベアチップ状態の半導体素子を、従来の実装装置である
フリップチップボンダーを用いて実装を試みたところ、
好ましく実装することができた。これによって、実施例
１と同様、〔半導体素子／異方導電性フィルム／回路基
板〕という、異方導電性フィルムが介在した３層構造の
実装体を、高い生産性で組み立て得ることがわかった。
また、異方導電性フィルムが介在した半導体素子と回路
基板との接続状態は、実施例１と同様、好ましいもので
あった。When the above-described bare chip semiconductor element was mounted on the mounting board obtained above using a flip chip bonder which is a conventional mounting apparatus,
It could be implemented favorably. As a result, similarly to Example 1, it was found that a three-layer package having an anisotropic conductive film interposed therebetween, [semiconductor element / anisotropic conductive film / circuit board], could be assembled with high productivity. .
Further, the connection state between the semiconductor element and the circuit board with the anisotropic conductive film interposed therebetween was favorable as in the case of the first embodiment.

【００５２】[0052]

【発明の効果】本発明によって、異方導電性フィルムを
介したチップの実装でありながら、従来の実装装置が利
用できるようになった。これによって、半導体素子／異
方導電性フィルム／回路基板の３者の実装体を製造する
際の、実装工程における生産性が向上した。According to the present invention, a conventional mounting apparatus can be used while mounting a chip via an anisotropic conductive film. As a result, the productivity in the mounting process when manufacturing the three-membered package of the semiconductor element / anisotropic conductive film / circuit board is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体装置の構成を示す断面図であ
る。半導体素子１の詳細な内部構造は省略しており、電
極が素子のどの位置にあるかだけを示している。説明の
ために、各部の寸法比を誇張して変えている。ハッチン
グは、領域を区別するために用いている。FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device of the present invention. The detailed internal structure of the semiconductor device 1 is omitted, and only the position of the electrode on the device is shown. For the sake of explanation, the dimensional ratio of each part is exaggerated. Hatching is used to distinguish regions.

【図２】本発明に用いられる異方導電性フィルムの一例
を示す模式図である。図２（ａ）は、フィルム面を見た
図であって、導通路の配列パターンを示すためにフィル
ム面の一部を拡大して示している。図２（ｂ）は、図２
（ａ）のＸ−Ｘ断面を示している。FIG. 2 is a schematic view showing an example of an anisotropic conductive film used in the present invention. FIG. 2A is a view of the film surface, in which a part of the film surface is enlarged to show an arrangement pattern of the conductive paths. FIG.
3A shows an XX cross section.

【図３】本発明に用いられる異方導電性フィルムの他の
例を示す模式図である。FIG. 3 is a schematic view showing another example of the anisotropic conductive film used in the present invention.

【図４】本発明に用いられる異方導電性フィルムの、導
通路の配列パターンの一例を示す図である。図２（ａ）
と同様、フィルム面を見た図であって、フィルム面の一
部を拡大して示しており、フィルムの外周形状を示すも
のではない。FIG. 4 is a view showing an example of an arrangement pattern of conductive paths of the anisotropic conductive film used in the present invention. FIG. 2 (a)
3 is a view of the film surface, similar to FIG. 3, showing a part of the film surface in an enlarged manner, and not showing the outer peripheral shape of the film.

【図５】本発明の実装用基板の構成を示す断面図であ
る。回路基板３の内部構造、層間接続構造などは省略し
ており、異方導電性フィルムとの接続側の実装用回路３
１がどの位置にあるかだけを示している。また、実装用
回路３１を誇張して厚く描いているために、異方導電性
フィルム２と回路基板３との間に大きな間隙があるよう
な図となっているが、実際にはほとんどの部分で密着し
ている。FIG. 5 is a cross-sectional view illustrating a configuration of a mounting board of the present invention. The internal structure and interlayer connection structure of the circuit board 3 are omitted, and the mounting circuit 3 on the connection side with the anisotropic conductive film is omitted.
Only the position of 1 is shown. In addition, since the mounting circuit 31 is exaggerated and drawn thick, there is a large gap between the anisotropic conductive film 2 and the circuit board 3; It is in close contact.

【符号の説明】[Explanation of symbols]

１ 半導体素子 １１ 電極 ２ 異方導電性フィルム ２１ 導通路 ２２ フィルム基板 DESCRIPTION OF SYMBOLS 1 Semiconductor element 11 Electrode 2 Anisotropic conductive film 21 Conduction path 22 Film substrate

───────────────────────────────────────────────────── フロントページの続き (72)発明者 松村 亜紀子 大阪府茨木市下穂積１丁目１番２号 日東 電工株式会社内 Ｆターム(参考） 5F044 KK03 LL09  ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Akiko Matsumura 1-1-2 Shimohozumi, Ibaraki-shi, Osaka Nitto Denko Corporation F-term (reference) 5F044 KK03 LL09

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 絶縁性樹脂からなるフィルム基板中に、
金属導線が互いに絶縁された状態で且つ該フィルム基板
を厚み方向に貫通した状態で、導通路として複数設けら
れた構造を有する異方導電性フィルムが、半導体素子の
電極面に接合され、半導体素子の各電極が、異方導電性
フィルム中の導通路を介して外部との電気的な接続が可
能な状態とされていることを特徴とする半導体装置。1. A film substrate comprising an insulating resin,
An anisotropic conductive film having a structure provided as a plurality of conductive paths is joined to an electrode surface of a semiconductor element in a state where metal conductive wires are insulated from each other and penetrate the film substrate in a thickness direction, and the semiconductor element is Wherein each of the electrodes is in a state where it can be electrically connected to the outside via conductive paths in the anisotropic conductive film. 【請求項２】 絶縁性樹脂からなるフィルム基板中に、
金属導線が互いに絶縁された状態で且つ該フィルム基板
を厚み方向に貫通した状態で、導通路として複数設けら
れた構造を有する異方導電性フィルムが、ウエハ上に形
成された複数の半導体素子の全ての電極面に接合され、
半導体素子の各電極が、異方導電性フィルム中の導通路
を介して外部との電気的な接続が可能な状態とされてい
ることを特徴とする半導体装置。2. A film substrate comprising an insulating resin,
In a state where the metal conductive wires are insulated from each other and penetrate the film substrate in the thickness direction, an anisotropic conductive film having a structure provided as a plurality of conductive paths is formed of a plurality of semiconductor elements formed on a wafer. Bonded to all electrode surfaces,
A semiconductor device, wherein each electrode of a semiconductor element is in a state where it can be electrically connected to the outside via conductive paths in an anisotropic conductive film. 【請求項３】 半導体素子の電極と、異方導電性フィル
ムの導通路の端部とが、接触または接合の状態とされて
おり、この接触または接合の状態とされている部分にお
ける、両者の材料の組み合わせが、電極側をアルミニウ
ムとし導通路側を金とする組み合わせ、または電極側を
バリアメタルとし、導通路側を半田とする組み合わせで
ある請求項１または２記載の半導体装置。3. An electrode of a semiconductor element and an end of a conductive path of an anisotropic conductive film are in a contact or joint state, and both of the two parts in a part in the contact or joint state. 3. The semiconductor device according to claim 1, wherein the combination of materials is a combination of aluminum on the electrode side and gold on the conductive path side, or a combination of a barrier metal on the electrode side and solder on the conductive path side. 4. 【請求項４】 絶縁性樹脂からなるフィルム基板中に、
金属導線が互いに絶縁された状態で且つ該フィルム基板
を厚み方向に貫通した状態で、導通路として複数設けら
れた構造を有する異方導電性フィルムが、 半導体素子の電極に対応する導体パターンとして形成さ
れた実装用回路を絶縁性基板の一方の面に有する回路基
板の、実装用回路側の面に接合され、 回路基板の実装用回路が、異方導電性フィルムを介して
半導体素子との電気的な接続が可能な状態とされている
ことを特徴とする半導体素子実装用回路基板。4. In a film substrate made of an insulating resin,
An anisotropic conductive film having a structure provided as a plurality of conductive paths is formed as a conductor pattern corresponding to an electrode of a semiconductor element in a state where metal conductive wires are insulated from each other and penetrate the film substrate in a thickness direction. The circuit board having the mounted mounting circuit on one side of the insulating substrate is bonded to the mounting circuit side surface, and the mounting circuit of the circuit board is electrically connected to the semiconductor element through the anisotropic conductive film. A circuit board for mounting a semiconductor element, wherein the circuit board is in a state where it can be electrically connected. 【請求項５】 回路基板の実装用回路と異方導電性フィ
ルムの導通路の端部とが接触または接合の状態とされて
おり、この接触または接合の状態とされている部分にお
ける、両者の材料の組み合わせが、実装用回路側を半田
とし導通路側を金とする組み合わせである請求項４記載
の半導体素子実装用回路基板。5. The mounting circuit of the circuit board and the end of the conductive path of the anisotropic conductive film are in a contact or joint state, and in the contact or joint part, both of them are connected. 5. The circuit board for mounting a semiconductor element according to claim 4, wherein the combination of materials is a combination in which the mounting circuit side is solder and the conduction path side is gold.
JP11087178A 1999-03-29 1999-03-29 Semiconductor device and circuit board for mounting semiconductor element Pending JP2000286293A (en)

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