JP2002151549A - Anisotropic conductive film - Google Patents

Anisotropic conductive film

Info

Publication number
JP2002151549A
JP2002151549A JP2000342509A JP2000342509A JP2002151549A JP 2002151549 A JP2002151549 A JP 2002151549A JP 2000342509 A JP2000342509 A JP 2000342509A JP 2000342509 A JP2000342509 A JP 2000342509A JP 2002151549 A JP2002151549 A JP 2002151549A
Authority
JP
Japan
Prior art keywords
film
anisotropic conductive
conductive film
circuit board
solder layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000342509A
Other languages
Japanese (ja)
Inventor
Kensuke Nishi
賢介 西
Yoshio Yamaguchi
美穂 山口
Yuji Hotta
祐治 堀田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Priority to JP2000342509A priority Critical patent/JP2002151549A/en
Publication of JP2002151549A publication Critical patent/JP2002151549A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide an anisotropic conductive film which can bond at least a semiconductor element and an electrode and/or a circuit board and an electrode easily and rigidly with high reliability while suppressing damage on the semiconductor element and the circuit board as much as possible. SOLUTION: The anisotropic conductive film 1 comprises a film basic material 2 of insulating material, and a plurality of conduction paths 3 insulated from each other in the film basic material 2 and arranged substantially in parallel with the thickness direction Z thereof to penetrate the film basic material 2 wherein the conduction path 3 has a part 4 projecting from the film basic material plane 2a on at least one side in the axial direction and the projecting part 4 has a solder later 6 like a thin film at the forward end thereof.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は異方導電性フィルム
に関し、詳しくは半導体素子と回路基板との接合に使用
される異方導電性フィルムに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an anisotropic conductive film, and more particularly, to an anisotropic conductive film used for bonding a semiconductor element to a circuit board.

【0002】[0002]

【従来の技術】異方導電性フィルムは、導電性について
異方性を示すフィルムであり、フィルムの表裏を貫通す
る方向には導電性を示すが、フィルム面が広がる方向に
は絶縁性を示すものである。したがってウエハ状態から
切り出した裸の半導体素子(チップ)と外部回路基板
(以下、単に回路基板と称す)との間に異方導電性フィ
ルムを挿入し、これら三者を接合することで、半導体素
子の電極と回路基板の電極とが異方導電性フィルムの導
通路を介して電気的に接続された半導体装置を得ること
ができる。近年の半導体集積回路の大規模な集積化、接
続端子(電極パッドなど)のファインピッチ化に伴い、
半導体素子の実装における異方導電性フィルムの使用は
益々増大しつつある。
2. Description of the Related Art An anisotropic conductive film is a film exhibiting anisotropy in conductivity. The film exhibits conductivity in a direction penetrating the front and back of the film, but exhibits insulation in a direction in which the film surface spreads. Things. Therefore, an anisotropic conductive film is inserted between a bare semiconductor element (chip) cut out from a wafer state and an external circuit board (hereinafter, simply referred to as a circuit board), and these three elements are joined to form a semiconductor element. And the electrodes of the circuit board are electrically connected to each other through the conductive path of the anisotropic conductive film. With the recent large-scale integration of semiconductor integrated circuits and fine pitch of connection terminals (electrode pads, etc.),
The use of anisotropic conductive films in mounting semiconductor devices is increasing.

【0003】従来、異方導電性フィルムとしては、接着
性の絶縁材料からなるフィルム中に、導通路となる導電
性微粒子を分散させて形成したものが知られている。し
かし、この従来の異方導電性フィルムは、構造上、ファ
インピッチ化した対象物との接続が難しいという問題
や、半導体素子の電極形状を凸状(バンプ状)にしなけ
ればならないという問題がある。そこで、ファインピッ
チ化に対応し得る異方導電性フィルムとして、本件出願
人は、国際公開公報WO98/07216において、複
数の導通路が互いに絶縁されて、フィルムの厚み方向に
貫通してなる異方導電性フィルム(すなわち、多数の導
通路が互いに絶縁されながら、各々が絶縁性樹脂からな
るフィルム基材を貫通し、各導通路の両端部がフィルム
基材の表裏面に露出した構造のフィルム)を提案してい
る。
[0003] Conventionally, as an anisotropic conductive film, a film formed by dispersing conductive fine particles serving as a conductive path in a film made of an adhesive insulating material is known. However, this conventional anisotropic conductive film has a problem that it is difficult to connect to an object having a fine pitch due to its structure, and a problem that the electrode shape of a semiconductor element must be convex (bump shape). . In view of this, as an anisotropic conductive film capable of coping with fine pitch, the present applicant has disclosed in International Publication WO98 / 07216 an anisotropic conductive film in which a plurality of conductive paths are insulated from each other and penetrate in the thickness direction of the film. Conductive film (that is, a film having a structure in which a number of conductive paths are insulated from each other, each penetrates a film base made of an insulating resin, and both ends of each conductive path are exposed on the front and back surfaces of the film base). Has been proposed.

【0004】[0004]

【発明が解決しようとする課題】フィルムの厚み方向に
導通路が貫通した構造の異方導電性フィルムを介して半
導体素子と回路基板とが電気的に接続された半導体装置
において、異方導電性フィルムと半導体素子間および異
方導電性フィルムと回路基板間の接合は、通常、接着性
を有するフィルム基材を半導体素子の電極面(回路基板
の電極面)に接着させて、導通路と電極とを接触状態に
保持して行っている。しかしこのような態様では、フィ
ルム基材に用いる絶縁性樹脂の種類によって、充分な接
合力が得られない場合や充分な電気的導通性が得られな
い場合がある。
SUMMARY OF THE INVENTION In a semiconductor device in which a semiconductor element and a circuit board are electrically connected via an anisotropic conductive film having a structure in which a conductive path penetrates in the thickness direction of the film, an anisotropic conductive film is provided. The bonding between the film and the semiconductor element and between the anisotropic conductive film and the circuit board is usually performed by bonding a film substrate having adhesiveness to the electrode surface of the semiconductor element (electrode surface of the circuit board) to form a conductive path and an electrode. Are kept in contact with each other. However, in such an embodiment, depending on the type of insulating resin used for the film substrate, there may be cases where sufficient bonding strength cannot be obtained or sufficient electrical conductivity cannot be obtained.

【0005】また上記のような態様では、加熱および加
圧の処理を施して接合を行うが、導通路と電極との間で
充分に信頼性の高い接触状態を得るためには、280℃
〜350℃程度の温度、1.4MPa〜3.0MPa程
度の圧力にて、0.3分〜1分程度の間、上記処理を行
うことが必要とされ、このため半導体素子及び回路基板
へのダメージが大きい。
In the above-described embodiment, the bonding is performed by applying heat and pressure. However, in order to obtain a sufficiently reliable contact state between the conductive path and the electrode, the bonding temperature is 280 ° C.
It is necessary to perform the above-mentioned processing at a temperature of about 350 ° C. and a pressure of about 1.4 MPa to 3.0 MPa for about 0.3 to 1 minute. Great damage.

【0006】本発明の目的は、上記事情に鑑みなされた
もので、少なくとも半導体素子との電極間および/また
は回路基板との電極間を高い信頼性にて簡易にかつ強固
に接合でき、しかもこの接合に際しての半導体素子およ
び回路基板へのダメージを可及的に抑制できる異方導電
性フィルムを提供することである。
SUMMARY OF THE INVENTION The object of the present invention has been made in view of the above circumstances, and it is possible to easily and firmly join at least the electrodes between the semiconductor element and the electrodes between the electrodes with the circuit board with high reliability. An object of the present invention is to provide an anisotropic conductive film capable of minimizing damage to a semiconductor element and a circuit board during bonding.

【0007】[0007]

【課題を解決するための手段】本発明者らは、上記課題
を解決するため鋭意研究を行った結果、本発明を完成す
るに至った。本発明は、以下のとおりである。 (1)絶縁性材料からなるフィルム基材と、該フィルム
基材内において互いに絶縁され、その軸線方向が該フィ
ルム基材の厚み方向と略平行に配置されて貫通する導電
性を有する複数の導通路とを備え、該導通路は、軸線方
向の少なくとも一方側にフィルム基材面から突出する突
出部を備え、該突出部がその先端に薄膜状の半田層を有
することを特徴とする異方導電性フィルム。 (2)該突出部の平均突出高さが0.1μm〜7μmで
あることを特徴とする上記(1)に記載の異方導電性フ
ィルム。 (3)半田層の厚みが0.1μm〜5μmであることを
特徴とする上記(1)または(2)に記載の異方導電性
フィルム。 (4)導通路がフィルム基材の両面から突出する突出部
を備え、該突出部がその先端に薄膜状の半田層を有する
ことを特徴とする上記(1)〜(3)に記載の異方導電
性フィルム。
Means for Solving the Problems The present inventors have made intensive studies to solve the above-mentioned problems, and as a result, have completed the present invention. The present invention is as follows. (1) A film substrate made of an insulating material and a plurality of conductive members which are insulated from each other in the film substrate, and are arranged so that their axial directions are substantially parallel to the thickness direction of the film substrate and penetrate therethrough. A passage, wherein the conduction path has a protrusion protruding from the film substrate surface on at least one side in the axial direction, and the protrusion has a thin-film solder layer at the tip thereof. Conductive film. (2) The anisotropic conductive film according to the above (1), wherein the average protrusion height of the protrusion is 0.1 μm to 7 μm. (3) The anisotropic conductive film according to the above (1) or (2), wherein the thickness of the solder layer is 0.1 μm to 5 μm. (4) The method according to any one of (1) to (3), wherein the conductive path includes a projecting portion projecting from both surfaces of the film substrate, and the projecting portion has a thin-film solder layer at a tip thereof. One side conductive film.

【0008】[0008]

【発明の実施の形態】以下、本発明を詳細に説明する。
図1は、本発明の好ましい一例の異方導電性フィルム1
を簡略化して示す断面図である。図1に示すように、本
発明の異方導電性フィルム1は、絶縁性材料からなるフ
ィルム基材2と、導電性材料からなる複数の導通路3と
を基本的に備える。導通路3は、その軸線方向の長さが
フィルム基材2の厚み方向Zの長さ(厚み)よりも大き
く、かつフィルム基材2を貫通してなり、その少なくと
も一端に、好ましくは図1に示す態様のように両側に、
フィルム面2aから突出する突出部4を有する。該導通
路3は、少なくともフィルム基材2内の部分(以下、
「基材内導通部5」と呼ぶことがある)が、該フィルム
基材2の厚み方向Zと略平行(図1においては平行)と
なるように配置される。
BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail.
FIG. 1 shows a preferred example of an anisotropic conductive film 1 of the present invention.
FIG. As shown in FIG. 1, the anisotropic conductive film 1 of the present invention basically includes a film substrate 2 made of an insulating material and a plurality of conductive paths 3 made of a conductive material. The conduction path 3 has a length in the axial direction larger than the length (thickness) of the film substrate 2 in the thickness direction Z and penetrates through the film substrate 2. On both sides as in the embodiment shown in
It has a projection 4 projecting from the film surface 2a. The conduction path 3 is formed at least in a portion within the film substrate 2 (hereinafter, referred to as a portion).
The “substrate 5 in the substrate” may be referred to as being substantially parallel to the thickness direction Z of the film substrate 2 (parallel in FIG. 1).

【0009】本発明において、上記突出部4は、その先
端、すなわちフィルム面2aから最も離反した端部分に
薄膜状の半田層6を有する。該半田層6を形成する材料
としては、Sn、Sn/Ag、Sn/Pb、Sn/Z
n、Sn/Ag/Cu、Sn/Biなどが挙げられる。
上記半田層6の形成方法としては、スクリーン印刷、電
解めっき、無電解めっきなどが挙げられる。
In the present invention, the protruding portion 4 has a thin-film solder layer 6 at its tip, that is, at the end farthest from the film surface 2a. Materials for forming the solder layer 6 include Sn, Sn / Ag, Sn / Pb, and Sn / Z.
n, Sn / Ag / Cu, Sn / Bi and the like.
Examples of a method for forming the solder layer 6 include screen printing, electrolytic plating, and electroless plating.

【0010】図2は、図1に示した本発明の異方導電性
フィルム1を用いた半導体素子11と回路基板12との
接合例を簡略化して示す図である。まず、図2(a)に
示すように、たとえば50℃〜150℃程度に加熱され
たステージ(図示せず)上に回路基板12を載置し、該
回路基板12上に本発明の異方導電性フィルム1を載置
する。この際、異方導電性フィルム1の導通路3を回路
基板12の電極13に位置合わせする。
FIG. 2 is a simplified diagram showing an example of joining a semiconductor element 11 and a circuit board 12 using the anisotropic conductive film 1 of the present invention shown in FIG. First, as shown in FIG. 2A, the circuit board 12 is placed on a stage (not shown) heated to, for example, about 50 ° C. to 150 ° C., and the anisotropic material of the present invention is placed on the circuit board 12. The conductive film 1 is placed. At this time, the conductive path 3 of the anisotropic conductive film 1 is aligned with the electrode 13 of the circuit board 12.

【0011】次に、図2(b)に示すように、半導体素
子11を、その電極14が回路基板12の電極13上に
位置する導通路3に相対するよう位置合わせしながら、
異方導電性フィルム1上に載置する。すなわち、導通路
3を挟んで半導体素子11の電極14と回路基板12の
電極13とが相対するような配置にて、半導体素子11
と回路基板12とで、異方導電性フィルム1を挟み込む
ようにする。このような状態で、半導体素子11、異方
導電性フィルム1および回路基板12からなる構成体
(以下、「半導体装置15」と呼ぶことがある。)に、
一定時間加熱を施す。この際、後述するように、場合に
よっては、該フィルム1の厚み方向Zに沿って加圧しな
がら行う。
Next, as shown in FIG. 2B, the semiconductor element 11 is aligned while its electrodes 14 are opposed to the conductive paths 3 located on the electrodes 13 of the circuit board 12.
It is placed on the anisotropic conductive film 1. That is, the semiconductor element 11 is arranged in such a manner that the electrode 14 of the semiconductor element 11 and the electrode 13 of the circuit board 12 face each other with the conduction path 3 interposed therebetween.
And the circuit board 12 sandwich the anisotropic conductive film 1. In such a state, a structure (hereinafter, sometimes referred to as “semiconductor device 15”) including the semiconductor element 11, the anisotropic conductive film 1, and the circuit board 12 is provided.
Heat for a certain time. At this time, as will be described later, in some cases, the pressing is performed along the thickness direction Z of the film 1.

【0012】本発明の異方導電性フィルム1は、上記の
ように導通路3が特定の平均突出高さの突出部4を有
し、さらに該突出部4はそのフィルム面2aから最も離
反した端部分に半田層6を有する。このように本発明に
おいては、半導体素子11および回路基板12にそれぞ
れ溶着することを意図する半田層6をフィルム面2aよ
り突出させてなる構造である。半田層6は、溶融固化す
ることによって金属や樹脂の種類を選ばず概ね種々の材
料面に強固に接合でき、しかも該半田層6にて導通路と
電極間の接合を行うことで充分な信頼性で電気的接続が
行える。これによって半導体素子の電極および回路基板
の電極に相対する位置の半田層を電極に接合し、電極に
相対しない位置の半田層を半導体素子表面の保護膜(パ
ッシベーション膜)および/または回路基板の基板面な
どに接合して、高い信頼性にて容易にかつ強固に半導体
装置15の各部材間の接合を行うことができる。
In the anisotropic conductive film 1 of the present invention, as described above, the conduction path 3 has the protrusion 4 having a specific average protrusion height, and the protrusion 4 is most separated from the film surface 2a. A solder layer 6 is provided at an end portion. As described above, the present invention has a structure in which the solder layer 6 intended to be welded to the semiconductor element 11 and the circuit board 12 respectively protrudes from the film surface 2a. The solder layer 6 can be firmly bonded to various material surfaces irrespective of the type of metal or resin by being melted and solidified, and sufficient reliability can be obtained by bonding between the conductive path and the electrode with the solder layer 6. Electrical connection can be made. Thus, the solder layer at a position facing the electrode of the semiconductor element and the electrode of the circuit board is bonded to the electrode, and the solder layer at a position not facing the electrode is formed on the protective film (passivation film) on the surface of the semiconductor element and / or the substrate of the circuit board. By joining to a surface or the like, the members of the semiconductor device 15 can be easily and firmly joined with high reliability.

【0013】このように本発明においては、半田層6の
みを用いることで容易かつ強固な接合が可能であるの
で、フィルム基材の接着のみで接合する場合とは異な
り、より短い時間の加熱のみで上記接合を行うことがで
きる。本発明の異方導電性フィルム1を用いて、半田層
6のみで接合を行う場合、通常、230℃〜300℃、
好ましくは230℃〜280℃の温度で、3秒〜40
秒、好ましくは5秒〜30秒の条件で、好適な接合を実
現できる。
As described above, in the present invention, since only the solder layer 6 can be used for easy and strong bonding, unlike the case of bonding only by bonding the film substrate, only the heating for a shorter time is required. The above bonding can be performed. When bonding is performed using only the solder layer 6 using the anisotropic conductive film 1 of the present invention, usually, 230 ° C. to 300 ° C.,
Preferably at a temperature of 230 ° C to 280 ° C for 3 seconds to 40
Suitable bonding can be realized under the conditions of seconds, preferably 5 seconds to 30 seconds.

【0014】また後述のように、フィルム基材2の材料
として、少なくとも加熱によって、あるいは加熱および
加圧によって接着性を示すような樹脂材料を用いる場合
には、半田層6による接合に加えて、フィルム基材2の
接着によっても上記接合を行うことができる。図2に
は、半田層6の溶融固化に加えて、フィルム基材2によ
る接着でも上記接合を行っている場合を示している。本
発明におけるフィルム基材として加熱のみによって接着
性を示す樹脂材料を用いた場合、フィルム基材の加熱に
よる接着のみで同様の接合を行う構成と比較して、30
秒〜60秒程度のより短い時間でより強固な接合を行う
ことができる。また本発明におけるフィルム基材として
加熱および加圧にて接着性を示す樹脂材料を用いた場合
であっても、フィルム基材の加熱および加圧による接着
のみで同様の接合を行う構成と比較して、0.2MPa
〜1.5MPa程度のより低い圧力で、かつ5秒〜30
秒程度のより短い時間でしかもより強固な接合を行うこ
とができる。このように本発明の異方導電性フィルム1
を用いることによって、上記程度の温度に晒しながら、
従来に比べてより短い時間条件にて、加圧も行う場合に
は、より低い圧力でよいので、接合による半導体素子お
よび回路基板へのダメージを抑制できる。
As will be described later, when a resin material that exhibits adhesiveness at least by heating or by heating and pressing is used as the material of the film substrate 2, in addition to the joining by the solder layer 6, The above bonding can also be performed by bonding the film substrate 2. FIG. 2 shows a case where the above-described bonding is performed not only by melting and solidifying the solder layer 6 but also by bonding with the film substrate 2. When a resin material showing adhesiveness only by heating is used as the film base material in the present invention, compared with a configuration in which similar bonding is performed only by bonding the film base material by heating,
Stronger bonding can be performed in a shorter time of about 60 seconds to 60 seconds. Further, even when a resin material showing adhesiveness by heating and pressing is used as the film substrate in the present invention, it is compared with a configuration in which similar bonding is performed only by bonding the film substrate by heating and pressing. And 0.2MPa
A lower pressure of about 1.5 MPa, and 5 seconds to 30
A stronger bonding can be performed in a shorter time of about seconds. Thus, the anisotropic conductive film 1 of the present invention
By using, while exposing to the temperature of the above degree,
In the case where pressure is also applied under shorter time conditions than in the conventional case, lower pressure may be used, so that damage to the semiconductor element and the circuit board due to bonding can be suppressed.

【0015】本発明において、突出部4のフィルム面2
aからの平均突出高さは、0.1μm〜7μm、好まし
くは0.1μm〜4μmである。該平均突出高さが、
0.1μm未満であると、チップ及び基板と接続する
際、低圧でのボンディングが困難となる虞があり好まし
くない。また該平均突出高さが7μmを超えると、半田
層が厚い場合には導通路間でのショートが発生し、半田
層が薄い場合には接続が困難となる虞があるため好まし
くない。本発明の異方導電性フィルム1を、後述するよ
うな電極の端面を除く周囲にポリイミドなどの樹脂にて
保護膜が形成された半導体素子の実装に用いる場合に
は、上記平均突出高さは、上記範囲の中でも特に0.1
μm〜4μmに選ばれるのが好ましい。上記突出部4の
平均突出高さは、フィルム基材2の厚み方向の一方Z1
側と他方Z2側とで同一であってもよく、また上記範囲
内で互いに異なっていてもよい。本発明においては、同
じ側の各突出部の突出高さが略同一に形成されるのが好
ましい。
In the present invention, the film surface 2 of the projection 4
The average protrusion height from a is 0.1 μm to 7 μm, preferably 0.1 μm to 4 μm. The average protrusion height is
If the thickness is less than 0.1 μm, it may be difficult to perform bonding at a low pressure when connecting to a chip and a substrate, which is not preferable. On the other hand, if the average protrusion height exceeds 7 μm, a short circuit occurs between the conductive paths when the solder layer is thick, and a connection may be difficult when the solder layer is thin. When the anisotropic conductive film 1 of the present invention is used for mounting a semiconductor element having a protective film formed of a resin such as polyimide around an electrode except for an end face of the electrode as described below, the average protrusion height is , Among the above ranges, especially 0.1
It is preferable to select from μm to 4 μm. The average projecting height of the projecting portion 4 is one of Z1 in the thickness direction of the film substrate 2.
Side and the other Z2 side may be the same, or may be different from each other within the above range. In the present invention, it is preferable that the protruding heights of the protruding portions on the same side are formed to be substantially the same.

【0016】上記のように本発明における半田層6は、
0.1μm〜7μmの平均突出高さにてフィルム面2a
から突出する突出部4のうち、該フィルム面2aから最
も離反した端部分に形成される。これによって、同じ半
田層を形成するにしても、上記半田層がフィルム面から
突出していない(該半田層の端面がフィルム面と同一の
面を形成している、あるいはフィルム面から陥没してい
る)異方導電性フィルムを用いた場合とは異なり、フィ
ルム面から突出した半田層6にてより容易に確実な電気
的接続を行うことが可能である。これによって上記場合
と比較しても、接合に際した圧力、時間などの条件を緩
和でき、したがって半導体素子および回路基板の接合に
際したダメージをより抑制できる。
As described above, the solder layer 6 in the present invention
Film surface 2a at an average protrusion height of 0.1 μm to 7 μm
Is formed at an end portion of the protruding portion 4 protruding from the film surface 2a farthest from the film surface 2a. Thereby, even if the same solder layer is formed, the solder layer does not protrude from the film surface (the end surface of the solder layer forms the same surface as the film surface, or is depressed from the film surface) 3) Unlike the case where an anisotropic conductive film is used, a reliable electrical connection can be easily performed with the solder layer 6 protruding from the film surface. As a result, even when compared with the above case, conditions such as pressure and time required for bonding can be relaxed, and therefore, damage when bonding the semiconductor element and the circuit board can be further suppressed.

【0017】本発明における半田層6は、その厚みが
0.1μm〜5μmであるのが好ましく、0.4μm〜
4μmであるのがより好ましい。半田層6の厚みが0.
1μm未満であると、チップおよび基板電極との金属接
合ができず、充分に電気的導通を得ることができない場
合があるため好ましくない。また半田層6の厚みが5μ
mを超えると、半田層が流れて導通路間でショートが発
生する場合があるため好ましくない。各半田層6の厚み
も、フィルム基材2の厚み方向の一方Z1側と他方Z2
側とで同一であってもよく、また上記範囲内で互いに異
なっていてもよい。
The thickness of the solder layer 6 in the present invention is preferably from 0.1 μm to 5 μm, more preferably from 0.4 μm to 5 μm.
More preferably, it is 4 μm. The thickness of the solder layer 6 is 0.
When the thickness is less than 1 μm, metal bonding between the chip and the substrate electrode cannot be performed, and sufficient electrical conduction may not be obtained, which is not preferable. The thickness of the solder layer 6 is 5 μm.
If it exceeds m, the solder layer flows and a short circuit may occur between the conductive paths, which is not preferable. The thickness of each solder layer 6 is also different from one Z1 side and the other Z2 in the thickness direction of the film base 2.
And the same may be different from each other within the above range.

【0018】このように半田層6における半田の量を、
上記溶着に必要最低限な量に選ぶことによって、上記半
田の溶着の際に互いに隣り合う突出部4における半田層
6の半田同士が互いに溶着して短絡が起こる不具合を確
実に防止でき、半田の溶着を利用した接続信頼性の高い
半導体素子11および回路基板12の接合を実現でき
る。
As described above, the amount of solder in the solder layer 6 is
By selecting the minimum necessary amount for the above-mentioned welding, it is possible to reliably prevent a problem that the solders of the solder layers 6 in the protruding portions 4 adjacent to each other are welded to each other to cause a short circuit when the solder is welded. Bonding of the semiconductor element 11 and the circuit board 12 with high connection reliability using welding can be realized.

【0019】なお本明細書における「半導体素子」は、
ウエハから分断されたチップを意味する。このようなチ
ップとしては、半導体結晶層と電極とを含んで構成され
る一種の回路であって、発光素子のような単純な構造の
もの、CPU、メモリ、種々の演算回路を集積したプロ
セッサなどが挙げられる。チップはSiやGaAsなど
の半導体結晶の他に、GaN系半導体を成長させるため
のサファイア結晶など、半導体結晶層などを成長させ得
る結晶基板であればよい。
In this specification, "semiconductor element"
It means a chip separated from the wafer. Such a chip is a kind of circuit including a semiconductor crystal layer and an electrode, which has a simple structure such as a light emitting element, a CPU, a memory, a processor in which various arithmetic circuits are integrated, and the like. Is mentioned. The chip may be a crystal substrate capable of growing a semiconductor crystal layer or the like, such as a sapphire crystal for growing a GaN-based semiconductor, in addition to a semiconductor crystal such as Si or GaAs.

【0020】また上記回路基板12としては、半導体素
子のためのパッケージ用基材や、半導体素子を他のデバ
イスに実装するための一般的なプリント回路基板などが
挙げられる。
Examples of the circuit board 12 include a package base for a semiconductor element and a general printed circuit board for mounting the semiconductor element on another device.

【0021】なお図2において、半導体素子11はベア
チップ状態(パッシベーション膜を含む裸のチップの状
態)を示し、素子の内部構造は省略している。また、回
路基板12は、便宜上、基板表面に在る配線を省略して
示している。
In FIG. 2, the semiconductor element 11 shows a bare chip state (a state of a bare chip including a passivation film), and the internal structure of the element is omitted. In addition, the circuit board 12 is shown with wirings on the surface of the board omitted for convenience.

【0022】異方導電性フィルム1の導通路3の断面
(通路方向と垂直に切断)の形状、大きさ、数は、半導
体素子の電極に応じて適宜選択することができるが、ピ
ッチが50μm以下のようなファインピッチの電極配置
パターンに対応するには、外径を5μm〜30μmとす
ることが好ましい。上記の条件を満たせば、導通路3の
断面形状は、円形や、多角形など、どのような形状であ
ってもよい。半導体素子の1つの電極の大きさが、たと
えば100μm×100μmの場合、半導体素子の1つ
の電極には、1個〜25個程度の複数の導通路を対応さ
せるのが好ましい。また、フィルム面をみたときの導通
路3の配列パターンは、最密状、正方行列状、その他ラ
ンダムな密集状態のいずれであってもよいが、微細な電
極に対応するには最密状が好ましい。
The shape, size, and number of the cross section (cut perpendicular to the passage direction) of the conductive path 3 of the anisotropic conductive film 1 can be appropriately selected according to the electrode of the semiconductor element, but the pitch is 50 μm. In order to cope with the following fine pitch electrode arrangement pattern, the outer diameter is preferably 5 μm to 30 μm. As long as the above conditions are satisfied, the cross-sectional shape of the conduction path 3 may be any shape such as a circle or a polygon. When the size of one electrode of the semiconductor element is, for example, 100 μm × 100 μm, it is preferable that one electrode of the semiconductor element has a plurality of approximately 1 to 25 conductive paths. Further, the arrangement pattern of the conductive paths 3 when viewed from the film surface may be any of a close-packed shape, a square matrix-like shape, and a random dense state. preferable.

【0023】上述のように半田層6における半田の量を
必要最低限とした構成は、半導体素子のファインピッチ
に対応して導通路の外径を小さくし、かつ単位面積あた
りの導通路の本数を多くした異方導電性フィルムを使用
する場合に特に有用である。この構成では、たとえば導
通路のピッチ(配置間隔)が25μm以下のような異方
導電性フィルムを用いる場合であっても、隣接する導通
路間の半田による電気的導通(短絡)を確実に防止する
ことができる。
As described above, in the configuration in which the amount of solder in the solder layer 6 is minimized, the outer diameter of the conductive path is reduced in accordance with the fine pitch of the semiconductor element, and the number of conductive paths per unit area is reduced. This is particularly useful when using an anisotropic conductive film having an increased amount of. In this configuration, even when an anisotropic conductive film having a conductive path pitch (arrangement interval) of 25 μm or less is used, electrical conduction (short circuit) due to solder between adjacent conductive paths is reliably prevented. can do.

【0024】異方導電性フィルムの導通路を形成する材
料としては、公知の導電性材料が挙げられるが、電気特
性の点で銅、金、アルミニウム、ニッケルなどの金属材
料が好ましく、さらには導電性の点から、銅、金がより
好ましい。これらの金属製導通路の外径は5μm〜10
0μm、好ましくは12μm〜30μmである。
As a material for forming a conductive path of the anisotropic conductive film, a known conductive material can be cited, but a metal material such as copper, gold, aluminum, and nickel is preferable in terms of electric characteristics. In terms of properties, copper and gold are more preferable. The outer diameter of these metal conducting paths is 5 μm to 10 μm.
0 μm, preferably 12 μm to 30 μm.

【0025】導通路3の材料は上記の通りであるが、同
じ金属材料であっても導通路3の形成方法によって導電
性や弾性率など種々の特性が異なる。導通路3は、フィ
ルム基材に形成した貫通孔内に金属材料をめっきで析出
させて得たものであってもよいが、金属線を、フィルム
基材を貫通させて導通路とした態様が好ましい。金属線
の中でも、たとえばJIS C 3103に規定された
銅線などのように電気を伝導すべく製造された金属銅線
が好ましく、電気的特性、機械的特性、さらにはコスト
の点でも最も優れた導通路となる。
Although the material of the conductive path 3 is as described above, various characteristics such as conductivity and elastic modulus are different depending on the method of forming the conductive path 3 even if the same metal material is used. The conducting path 3 may be obtained by depositing a metal material in a through-hole formed in the film base material by plating. preferable. Among the metal wires, for example, a metal copper wire manufactured to conduct electricity, such as a copper wire specified in JIS C 3103, is preferable, and is most excellent in terms of electrical characteristics, mechanical characteristics, and cost. It becomes a conduction path.

【0026】上記のような金属線がフィルム基材を貫通
した状態のものを得るには、導線を樹脂材料で被覆して
なる多数の絶縁導線を密に束ねた状態で互いに分離でき
ないように固定し、各絶縁導線と角度を成す面を切断面
として、所望のフィルム厚みにスライスする方法が挙げ
られる。このような態様の異方導電性フィルムおよびそ
の製造方法については、国際公開公報WO98/072
16「異方導電性フィルムおよびその製造方法」に詳し
く記載されている。
In order to obtain the above-mentioned metal wire penetrating the film substrate, a large number of insulated conductors formed by coating the conductors with a resin material are tightly bundled and fixed so that they cannot be separated from each other. Then, there is a method of slicing to a desired film thickness using a surface forming an angle with each insulated conductor as a cut surface. The anisotropic conductive film of such an embodiment and a method for producing the same are described in International Publication WO98 / 072.
16 "Anisotropic conductive film and method for producing the same".

【0027】また、芯材に絶縁導線を密に巻き付け、加
熱、場合によっては加熱および加圧によって、樹脂材料
を互いに接合させたものから複数のブロックを切り出し
て、これらを所望の異方導電性フィルムの大きさに併せ
て適宜積み重ねて互いに接合させ、この接合物から異方
導電性フィルムを得てもいい。
Further, a plurality of blocks are cut out from a resin material bonded to each other by tightly winding an insulated conductive wire around a core material and heating, and in some cases, heating and pressurizing, and these are cut into a desired anisotropic conductive material. The anisotropic conductive film may be obtained from the joined product by appropriately stacking and joining them according to the size of the film.

【0028】突出部の半田層を除く残余の部分(以下、
「突出導通部分7」と呼ぶことがある)を形成する方法
としては、フィルム面2aに露出する導通路2の端面に
めっきや蒸着によって金属を堆積させる従来公知の方法
が挙げられる。このような金属材料としては、たとえば
銅、ニッケル、金、パラジウム、クロムなどが挙げられ
る。
The remaining portion of the projecting portion excluding the solder layer (hereinafter referred to as the
As a method of forming the “projecting conductive portion 7”, a conventionally known method of depositing a metal by plating or vapor deposition on the end surface of the conductive path 2 exposed on the film surface 2a can be used. Examples of such a metal material include copper, nickel, gold, palladium, and chromium.

【0029】また、フィルム面2aに導通路2の端面が
露出したものに対して、フィルム基材のみが選択的に除
去されるエッチングを施して、突出導通部分7を形成す
るようにしてもよい。エッチング方法としては、ウエッ
トエッチングや、プラズマエッチング、アルゴンイオン
レーザ、KrFエキシマレーザなどのドライエッチング
などの手法を単独または併用して使用することができ
る。ウエットエッチングにおけるエッチング液はフィル
ム基材の材料、導通路の材料を考慮して選択されるが、
たとえば、ジメチルアセトアミド、ジオキサン、テトラ
ヒドロフラン、塩化メチレンなどが挙げられる。
Further, the protruding conductive portion 7 may be formed by performing etching on the film surface 2a where the end face of the conductive path 2 is exposed to selectively remove only the film base material. . As an etching method, a method such as wet etching, plasma etching, dry etching such as an argon ion laser and a KrF excimer laser can be used alone or in combination. The etching solution in wet etching is selected in consideration of the material of the film base material and the material of the conduction path,
For example, dimethylacetamide, dioxane, tetrahydrofuran, methylene chloride and the like can be mentioned.

【0030】本発明においては、上記突出導通部分7を
形成せずに、半田層のみをフィルム面から突出させたも
の(すなわち半田層自身が突出部である態様)であって
もよいが、上述の電気的接合を確実かつ強固に行う観点
からは、突出導通部分を有するように実現されるのが好
ましい。
In the present invention, a configuration in which only the solder layer protrudes from the film surface without forming the protruding conductive portion 7 (that is, a mode in which the solder layer itself is a protruding portion) may be used. From the viewpoint of securely and firmly performing the electrical joining of the above, it is preferable that the electrical connection is realized so as to have a projecting conductive portion.

【0031】本発明における異方導電性フィルム1の厚
みとしては、10μm〜200μmが好ましく、中でも
25μm〜100μmがより好ましい。該厚みが10μ
m未満であると、樹脂量が少ないためチップ及び基板接
続時にボイドが発生し、充分な接続信頼性が得られない
虞があり好ましくない。また該厚みが200μmを超え
ると、チップ及び基板接続時に導通路が傾斜する虞があ
り好ましくない。
The thickness of the anisotropic conductive film 1 in the present invention is preferably from 10 μm to 200 μm, and more preferably from 25 μm to 100 μm. The thickness is 10μ
If it is less than m, voids are generated at the time of connecting the chip and the substrate because the amount of resin is small, and there is a possibility that sufficient connection reliability may not be obtained, which is not preferable. On the other hand, if the thickness exceeds 200 μm, the conductive path may be inclined when connecting the chip and the substrate, which is not preferable.

【0032】異方導電性フィルムの線膨張係数および弾
性率は、半導体素子、回路基板との接合性(接着力、導
通性)に影響する。異方導電性フィルムの線膨張係数は
フィルムの厚み方向と面内方向とでは異なるが、30℃
〜50℃の温度範囲における面内方向の線膨張係数が好
ましくは10ppm〜150ppm、より好ましくは1
0ppm〜80ppmの範囲であれば、より良好な接合
性が得られる。なお上記線膨張係数は、熱機械分析(T
MA)装置を用いて好適に測定できる。
The coefficient of linear expansion and the modulus of elasticity of the anisotropic conductive film affect the bonding properties (adhesive strength and conductivity) with the semiconductor element and the circuit board. The coefficient of linear expansion of the anisotropic conductive film differs between the thickness direction and the in-plane direction of the film.
The coefficient of linear expansion in the in-plane direction in the temperature range of 5050 ° C. is preferably 10 ppm to 150 ppm, more preferably 1 ppm.
When the content is in the range of 0 ppm to 80 ppm, better bonding properties can be obtained. The coefficient of linear expansion is determined by thermomechanical analysis (T
MA) can be suitably measured using an apparatus.

【0033】また、異方導電性フィルムの弾性率もフィ
ルムの厚み方向と面内方向では異なるが、25℃〜40
℃の温度範囲における面内方向の弾性率が好ましくは1
GPa〜5GPa、より好ましくは1GPa〜4GPa
の範囲にあれば、より良好な接着性が得られる。ここで
の線膨張係数および弾性率は、導通路が先端に半田層を
有する状態の、異方導電性フィルムの面内方向(フィル
ム面が広がる方向)に関する値である。なお上記弾性率
は、動的粘弾性測定装置を用いて好適に測定できる。
The elastic modulus of the anisotropic conductive film is also different between the thickness direction and the in-plane direction of the film.
The elastic modulus in the in-plane direction in a temperature range of ° C is preferably 1
GPa to 5 GPa, more preferably 1 GPa to 4 GPa
Within this range, better adhesiveness can be obtained. Here, the linear expansion coefficient and the elastic modulus are values relating to the in-plane direction of the anisotropic conductive film (the direction in which the film surface expands) in a state where the conductive path has a solder layer at the tip. In addition, the said elastic modulus can be measured suitably using a dynamic viscoelasticity measuring device.

【0034】異方導電性フィルムの構造全体としての弾
性率を決定する要素としては、導通路の材料、導通路の
断面形状や全長、導通路の配置の密度や配置パターン、
フィルム基材の材料、フィルム基材の厚みなどである。
これらの要素を選択し、上記弾性率の範囲とすればよ
い。
The factors that determine the elastic modulus of the entire structure of the anisotropic conductive film include the material of the conductive path, the cross-sectional shape and the total length of the conductive path, the density and pattern of the conductive path, and the like.
The material of the film base, the thickness of the film base, and the like.
What is necessary is just to select these elements and make it into the said elastic modulus range.

【0035】本発明における異方導電性フィルム1のフ
ィルム基材2に用いられる絶縁性樹脂としては、従来公
知の種々の樹脂材料が利用できる。特に、ポリエステル
樹脂(軟化点:180℃〜220℃)、ポリアミド樹脂
(軟化点:150℃〜210℃)、ポリカルボジイミド
樹脂(軟化点:140℃〜180℃)、フェノキシ樹脂
(軟化点:130℃〜160℃)、エポキシ樹脂(軟化
点:100℃〜150℃)などのような加熱加圧時に接
着性を示す材料が好ましい。
As the insulating resin used for the film substrate 2 of the anisotropic conductive film 1 in the present invention, various conventionally known resin materials can be used. In particular, polyester resin (softening point: 180 ° C to 220 ° C), polyamide resin (softening point: 150 ° C to 210 ° C), polycarbodiimide resin (softening point: 140 ° C to 180 ° C), phenoxy resin (softening point: 130 ° C) To 160.degree. C.), epoxy resin (softening point: 100.degree. C. to 150.degree. C.), and a material exhibiting adhesiveness when heated and pressed.

【0036】なお本明細書中における軟化点は、熱機械
分析(TMA)で、次の条件で測定したときの、TMA
チャートの屈曲点の温度をさす。 モード:引張モード、サンプルサイズ:4mm幅、チャ
ック間距離:10mm、引張荷重:1g、昇温速度:1
0℃/分
[0036] The softening point in the present specification is measured by thermomechanical analysis (TMA) under the following conditions.
The temperature at the inflection point of the chart. Mode: tensile mode, sample size: 4 mm width, distance between chucks: 10 mm, tensile load: 1 g, temperature rising rate: 1
0 ° C / min

【0037】本発明の異方導電性フィルム1において
は、上述のように突出部4先端の半田層6のみで、充分
に強固でかつ高い接続信頼性にて、半導体素子と回路基
板との間の接合を行うことができる。上記のようにフィ
ルム基材2の材料として、上記のように加熱加圧時に接
着性を示す樹脂材料を用い、半田層6に併せてフィルム
基材2の接着によっても接合することによって、半導体
素子および/または回路基板へのさらに確実で強固な接
合が可能となる。
In the anisotropic conductive film 1 of the present invention, as described above, only the solder layer 6 at the tip of the protruding portion 4 provides a sufficiently strong and high connection reliability between the semiconductor element and the circuit board. Can be joined. As described above, as the material of the film substrate 2, a resin material having an adhesive property when heated and pressed as described above is used, and the film substrate 2 is also joined to the solder layer 6 by bonding, whereby a semiconductor element is formed. And / or more secure and strong bonding to the circuit board is possible.

【0038】フィルム基材2によっても上記接合を行う
場合、以下の手順で行うことが好ましい。 まず図2(a)に示したように、半田層6が半導体素
子11の電極14および回路基板12の電極13に相対
して接触するよう、半導体素子11、異方導電性フィル
ム1および回路基板12の三者を位置合わせする。
In the case where the above-mentioned joining is also performed using the film substrate 2, it is preferable to perform the following procedure. First, as shown in FIG. 2A, the semiconductor element 11, the anisotropic conductive film 1, and the circuit board 12 are arranged such that the solder layer 6 is in contact with the electrode 14 of the semiconductor element 11 and the electrode 13 of the circuit board 12. Align the 12 members.

【0039】次に、上記構成体を、半田の溶融温度よ
りも低い温度にて加熱、場合によっては加熱・加圧す
る。これによって半田層6の半田を流動させることな
く、フィルム基材2のみを流動固化させて異方導電性フ
イルムを介して半導体素子11および回路基板12を接
着する。このフィルム基材2の流動固化の際、フィルム
基材2を形成する樹脂は、突出部4間の空間に流入して
固化する。これにより上記接着後は、半田層6をフィル
ム基材2の壁で囲んだ状態とできる。
Next, the above structure is heated at a temperature lower than the melting temperature of the solder, and in some cases, is heated and pressed. As a result, only the film substrate 2 is flow-solidified without flowing the solder of the solder layer 6, and the semiconductor element 11 and the circuit board 12 are bonded via the anisotropic conductive film. When the film substrate 2 is fluidized and solidified, the resin forming the film substrate 2 flows into the space between the protrusions 4 and solidifies. Thus, after the above-mentioned bonding, the solder layer 6 can be surrounded by the wall of the film substrate 2.

【0040】上記接着の際の加熱の温度は、半田の種
類、フィルム基材を形成する樹脂の種類によっても異な
るが、好ましくは140℃〜220℃、より好ましくは
140℃〜180℃である。該温度が140℃未満であ
る場合には、フィルム基材2の半導体素子11および/
または回路基板12への接着力が充分に得られなくなる
虞があり好ましくない。また該温度が220℃を超える
場合には、該接着の際に半田が流動する虞があり好まし
くない。また加熱とともに加圧を行う場合の圧力は、
0.3MPa〜3.0MPaが好ましく、0.5MPa
〜2.5MPaがより好ましい。該圧力が0.3MPa
未満であると、加圧による接着力の向上が期待できない
ため好ましくなく、また該圧力が3.0MPaを超える
場合には、該熱融着の際に導通路の倒れ(傾き)が生じ
てしまう虞があるため好ましくない。
The heating temperature at the time of the above-mentioned bonding varies depending on the type of solder and the type of resin forming the film substrate, but is preferably 140 ° C. to 220 ° C., and more preferably 140 ° C. to 180 ° C. If the temperature is lower than 140 ° C., the semiconductor elements 11 and / or
Alternatively, the adhesive strength to the circuit board 12 may not be sufficiently obtained, which is not preferable. If the temperature exceeds 220 ° C., the solder may flow during the bonding, which is not preferable. In addition, when pressurizing with heating, the pressure is:
0.3 MPa to 3.0 MPa is preferable, and 0.5 MPa
-2.5 MPa is more preferable. The pressure is 0.3MPa
When the pressure is less than 3.0 MPa, it is not preferable because the adhesive strength cannot be expected to be improved by pressurization. When the pressure exceeds 3.0 MPa, collapse (inclination) of the conduction path occurs during the heat fusion. It is not preferable because there is a fear.

【0041】次に、さらに加熱を行って、フィルムの
表側、裏側の半田層6をそれぞれ半導体素子11の電極
14、回路基板12の電極13に溶融接合する。この
際、各導通路3の先端の半田層6は、それぞれフィルム
基材2の壁に囲まれていることから、互いに隣接する半
田層同士が接触(融合)してしまうことなく、溶融固化
して半導体素子11の電極14および回路基板12の電
極13に溶融接合する。
Next, by further heating, the solder layers 6 on the front side and the back side of the film are melt-bonded to the electrode 14 of the semiconductor element 11 and the electrode 13 of the circuit board 12, respectively. At this time, since the solder layer 6 at the end of each conduction path 3 is surrounded by the wall of the film base material 2, the solder layers adjacent to each other are melted and solidified without contact (fusion). To melt-bond to the electrode 14 of the semiconductor element 11 and the electrode 13 of the circuit board 12.

【0042】本発明の異方導電性フィルムを使用し、上
記のような方法で接合を行うことによって、異方導電性
フィルムの隣接する導通路間が電気的絶縁状態を維持
し、半導体素子の電極および/または回路基板の電極間
に短絡が生じていない、高信頼性の半導体装置を形成で
きる。
By using the anisotropic conductive film of the present invention and performing bonding by the above-described method, an electrically insulating state is maintained between adjacent conductive paths of the anisotropic conductive film, and A highly reliable semiconductor device in which a short circuit does not occur between electrodes and / or electrodes of a circuit board can be formed.

【0043】上記異方導電性フィルムのフィルム基材の
接着および半田層の溶融接合作業に使用される加熱装置
としては、たとえば、IRリフロー装置などが使用され
る。また、フィルム基材の接着を加熱および加圧で行う
場合の加熱・加圧装置としては、たとえば、オートクレ
ーブやフリップチップボンダーなどの他、プレス装置
(所望の加熱手段(ヒータ手段、熱風送風機など)が付
加されたもの)などが使用される。
As a heating device used for bonding the film base of the anisotropically conductive film and melting and joining the solder layer, for example, an IR reflow device is used. In addition, as a heating / pressing device when the bonding of the film substrate is performed by heating and pressing, for example, in addition to an autoclave, a flip chip bonder, and the like, a pressing device (desired heating means (heater means, hot air blower, etc.)) Are added).

【0044】なお半田層は、通常、異方導電性フィルム
表裏面から突出する全ての導通路の先端に対して設ける
のが好ましいが、半導体素子、回路基板などに対して充
分な接合強度が得られ、目的の導通性が得られるのであ
れば、必ずしも、全ての導通路に半田層を設けなくても
よい。たとえば片側の突出部にのみ半田層を設けてもよ
く、またフィルムの同一面から突出する各突出部のう
ち、一部のみに選択的に半田層を設けるように実現して
もよい。
Usually, it is preferable to provide the solder layer at the ends of all the conductive paths protruding from the front and back surfaces of the anisotropic conductive film, but it is possible to obtain a sufficient bonding strength to a semiconductor element, a circuit board and the like. Therefore, as long as the desired conductivity can be obtained, it is not always necessary to provide a solder layer on all the conduction paths. For example, a solder layer may be provided only on one protruding portion, or a solder layer may be selectively provided only on a part of each protruding portion protruding from the same surface of the film.

【0045】なお異方導電性フィルムの導通路の半導体
素子側または回路基板側のいずれか片側の先端のみに半
田層を設けた場合、半田層を設けていない側の導通路の
先端は、半導体素子の電極または回路基板の電極に直接
接触して電気的な導通状態をつくるようにする。
When a solder layer is provided only on one end of the conductive path of the anisotropic conductive film on either the semiconductor element side or the circuit board side, the end of the conductive path on which the solder layer is not provided is connected to the semiconductor layer. An electrical conduction state is created by directly contacting the electrodes of the element or the electrodes of the circuit board.

【0046】[0046]

【実施例】実施例 以下の半導体素子(チップ)、回路基板および異方導電
性フィルムを用意した。 チップ:外形が8mm×8mm、厚みが300μmのシ
リコンチップ11であって、図3(a),(b)に示す
ように、シリコン基層15回路形成面に厚み1μmの窒
化珪素層16、その上に厚み3μmのポリイミド層17
が積層されている。電極パッド14のサイズは100μ
m×100μmで、電極パッド配列は200μmのピッ
チでチップ11周囲にペリフェラルに配置したものであ
る。パッド14表面は、Ni/Auめっき処理が施さ
れ、ポリイミド層17と同じ高さである。 回路基板:外形40mm×40mm、厚み25μmのポ
リイミド上に、厚み15μmの配線パターンが形成され
ており、配線パターン表面はNi/Auめっき処理が施
されている。 異方導電性フィルム:後述の方法により作製した、ポリ
カルボジイミド樹脂からなる厚み70μmのフィルム基
材に、導通路(外径:0.03mmの銅線)が50μm
のピッチで最密状に並んで貫通した外形8.2mm×
8.2mmの異方導電性フィルムのフィルム面から露出
した銅線の端部分に、無電解めっき法にて半田(Sn)
層を形成したもの。突出部の高さ:3μm、半田層の厚
み:2μm、30℃〜50℃の温度範囲における面内方
向の線膨張係数:73.3ppm(熱機械分析装置(T
MA/SS100、セイコーインスツルメンツ社製)を
用いて測定)、25℃〜40℃の温度範囲における面内
方向の弾性率:3.4GPa(動的粘弾性測定装置(D
MS210、セイコーインスツルメンツ社製)を用いて
測定)。
EXAMPLES The following semiconductor elements (chips), circuit boards and anisotropic conductive films were prepared. Chip: a silicon chip 11 having an outer shape of 8 mm × 8 mm and a thickness of 300 μm, as shown in FIGS. 3A and 3B, a silicon base layer 15, a 1 μm thick silicon nitride layer 16 on a circuit forming surface, and 3 μm thick polyimide layer 17
Are laminated. The size of the electrode pad 14 is 100 μ
The electrode pad arrangement is mx100 μm, and the electrode pad array is arranged on the periphery of the chip 11 at a pitch of 200 μm. The surface of the pad 14 is subjected to Ni / Au plating and has the same height as the polyimide layer 17. Circuit board: A wiring pattern having a thickness of 15 μm is formed on a polyimide having an outer shape of 40 mm × 40 mm and a thickness of 25 μm, and the surface of the wiring pattern is subjected to Ni / Au plating. Anisotropic conductive film: A conductive path (outer diameter: 0.03 mm copper wire) is formed on a 70 μm thick film base made of polycarbodiimide resin, which is prepared by the method described later, and has a thickness of 50 μm.
8.2mm ×
Solder (Sn) to the end of the copper wire exposed from the film surface of the 8.2 mm anisotropic conductive film by electroless plating.
What formed a layer. Height of protrusion: 3 μm, thickness of solder layer: 2 μm, linear expansion coefficient in the in-plane direction in a temperature range of 30 ° C. to 50 ° C .: 73.3 ppm (Thermo-mechanical analyzer (T
MA / SS100, measured by Seiko Instruments Inc.), in-plane elastic modulus in a temperature range of 25 ° C. to 40 ° C .: 3.4 GPa (dynamic viscoelasticity measuring device (D
MS210, manufactured by Seiko Instruments Inc.).

【0047】〔異方導電性フィルムの製法〕外径30μ
mの銅線の表面にポリカルボジイミド樹脂(軟化点:6
5℃)によって、厚み25μmの被覆層を形成し、総外
径が55μmの絶縁導線を作製した後、該絶縁導線を巻
線装置によって、全長(巻き幅)が210mm、断面形
状が160mm×160mmの正方形の角柱プラスチッ
ク芯材に整列巻きを行い、最密充填して、1層当たりの
平均巻き数が98.5ターン、巻き層数が130層(=
層の厚み:約15mm)の巻線コイルを形成し、次に、
この巻線コイルを約130℃に加熱しながら、0.94
MPaで加圧し、ポリカルボジイミド樹脂を融着させ、
室温まで冷却して、巻き付けた線材が一体化した巻線コ
イルブロックを得た。巻線コイルブロックより芯材を抜
いて角筒状とし、これを80mm×30mm×15mm
の直方体ブロックに切断した。この直方体ブロックを、
線材が同じ向きとなるよう5個重ね合わせた積層物を、
約160℃に加熱しながら1.96MPaで加圧し、8
0mm×30mm×75mmの複合ブロックを得た。こ
のブロックをスライスして、80mm×75mmの大き
さで、0.070mm厚みの異方導電性フィルムを得
た。
[Method of producing anisotropic conductive film] Outer diameter 30 μm
m of polycarbodiimide resin (softening point: 6)
5 [deg.] C.) to form a coating layer having a thickness of 25 [mu] m and producing an insulated wire having a total outer diameter of 55 [mu] m. The insulated wire was wound with a winding device to have a total length (winding width) of 210 mm and a cross-sectional shape of 160 mm * 160 mm. Is wound around the square prism plastic core material in a close-packed manner, and the average number of windings per layer is 98.5 turns and the number of winding layers is 130 (=
Layer thickness: about 15 mm) to form a wound coil,
While heating the wound coil to about 130 ° C, 0.94
Pressurized with MPa to fuse the polycarbodiimide resin,
After cooling to room temperature, a wound coil block in which the wound wire was integrated was obtained. The core material is removed from the wound coil block to make a square tube, which is 80 mm x 30 mm x 15 mm
Cut into rectangular parallelepiped blocks. This cuboid block,
A laminate in which five wires are stacked so that they are in the same direction,
While heating to about 160 ° C., pressurizing at 1.96 MPa, 8
A composite block of 0 mm × 30 mm × 75 mm was obtained. This block was sliced to obtain an anisotropic conductive film having a size of 80 mm × 75 mm and a thickness of 0.070 mm.

【0048】まず上述のような回路基板を、150℃に
加熱されたステージ上に吸着させ、その後、上述のよう
なチップをフリップチップボンダー(渋谷工業製)に吸
着させた。チップと回路基板の位置合わせを行った後、
異方導電性フィルムを回路基板上に配置し、圧力が0.
49MPa、温度が335℃、時間が30秒間の条件で
加熱加圧して接合を行った。
First, the above-mentioned circuit board was adsorbed on a stage heated to 150 ° C., and then the above-mentioned chip was adsorbed on a flip chip bonder (manufactured by Shibuya Kogyo). After aligning the chip and the circuit board,
An anisotropic conductive film is placed on a circuit board, and the pressure is set to 0.
The bonding was performed by heating and pressing under the conditions of 49 MPa, a temperature of 335 ° C., and a time of 30 seconds.

【0049】上記方法により作製した実施例のサンプル
の接合直後の初期接続抵抗値は1.5mΩであった。抵
抗値測定後、このサンプルをプレッシャークッカー装置
内に設置し、装置内温度121℃、湿度100%となる
ように設定し、接続信頼性試験を行ったが、初期状態と
同様に接続抵抗値の変化が殆どなかった。本発明の製造
方法が充分に有用であることが分かった。
The initial connection resistance value of the sample of the embodiment manufactured by the above method immediately after the bonding was 1.5 mΩ. After measuring the resistance value, the sample was set in a pressure cooker, the temperature was set to 121 ° C. and the humidity was set to 100%, and a connection reliability test was performed. There was little change. It has been found that the production method of the present invention is sufficiently useful.

【0050】比較例 実施例と比較するために、半田層の端面がフィルム面か
ら突出していない以外は実施例と同様の異方導電性フィ
ルムを用い、同じ条件で接合を行ったが、初期接続抵抗
値が4mΩであった。この比較例のサンプルを用いて、
実施例と同様にプレッシャークッカー装置を用いた、接
続信頼性試験を行ったが、チップと異方導電性フィルム
との間に剥離が生じ、導通が確認できなかった。
Comparative Example For comparison with the example, the same anisotropic conductive film was used as in the example except that the end face of the solder layer did not protrude from the film surface, and bonding was performed under the same conditions. The resistance value was 4 mΩ. Using the sample of this comparative example,
A connection reliability test was performed using a pressure cooker device in the same manner as in the example, but peeling occurred between the chip and the anisotropic conductive film, and conduction could not be confirmed.

【0051】[0051]

【発明の効果】以上の説明で明らかなように、本発明に
よれば、少なくとも半導体素子との電極間および/また
は回路基板との電極間を高い信頼性にて簡易にかつ強固
に接合でき、しかもこの接合に際しての半導体素子およ
び回路基板へのダメージを可及的に抑制できる異方導電
性フィルムを提供することができる。
As is apparent from the above description, according to the present invention, at least between the electrodes with the semiconductor element and / or between the electrodes with the circuit board can be easily and firmly joined with high reliability. In addition, it is possible to provide an anisotropic conductive film that can minimize damage to the semiconductor element and the circuit board during this bonding.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の好ましい一例の異方導電性フィルム1
を簡略化して示す断面図である。
FIG. 1 shows a preferred example of an anisotropic conductive film 1 of the present invention.
FIG.

【図2】図1に示した本発明の異方導電性フィルム1を
用いた半導体素子11と回路基板12との接合例を簡略
化して示す図である。
FIG. 2 is a simplified diagram showing an example of joining a semiconductor element 11 and a circuit board 12 using the anisotropic conductive film 1 of the present invention shown in FIG.

【図3】本発明の異方導電性フィルム1を使用して回路
基板に接合する半導体素子11の一例を簡略化して示す
図であり、図3(a)は正面図であり、図3(b)は拡
大した断面図である。
FIG. 3 is a simplified diagram showing an example of a semiconductor element 11 bonded to a circuit board using the anisotropic conductive film 1 of the present invention. FIG. 3 (a) is a front view, and FIG. b) is an enlarged sectional view.

【符号の説明】[Explanation of symbols]

1 異方導電性フィルム 2 フィルム基材 3 導通路 4 突出部 5 導通路のフィルム基材内の部分(基材内
導通部) 6 半田層 7 突出導通部分
DESCRIPTION OF SYMBOLS 1 Anisotropic conductive film 2 Film base material 3 Conductive path 4 Projecting part 5 Part of conductive path in film base (conductive part in base material) 6 Solder layer 7 Projecting conductive part

───────────────────────────────────────────────────── フロントページの続き (72)発明者 堀田 祐治 大阪府茨木市下穂積1丁目1番2号 日東 電工株式会社内 Fターム(参考) 5E085 BB08 BB28 DD01 EE15 FF19 GG12 HH01 JJ06 JJ31 JJ35 JJ38 5F044 LL04 LL09 LL13  ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yuji Hotta 1-2-1, Shimohozumi, Ibaraki-shi, Osaka Nitto Denko Corporation F-term (reference) 5E085 BB08 BB28 DD01 EE15 FF19 GG12 HH01 JJ06 JJ31 JJ35 JJ38 5F044 LL04 LL09 LL13

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性材料からなるフィルム基材と、該
フィルム基材内において互いに絶縁され、その軸線方向
が該フィルム基材の厚み方向と略平行に配置されて貫通
する導電性を有する複数の導通路とを備え、 該導通路は、軸線方向の少なくとも一方側にフィルム基
材面から突出する突出部を備え、該突出部がその先端に
薄膜状の半田層を有することを特徴とする異方導電性フ
ィルム。
1. A film base made of an insulating material, and a plurality of conductive bases which are insulated from each other in the film base, are arranged in an axis direction substantially parallel to a thickness direction of the film base, and penetrate therethrough. A conductive path, wherein the conductive path has a protrusion protruding from the film substrate surface on at least one side in the axial direction, and the protrusion has a thin-film solder layer at its tip. Anisotropic conductive film.
【請求項2】 該突出部の平均突出高さが0.1μm〜
7μmであることを特徴とする請求項1に記載の異方導
電性フィルム。
2. The projecting portion has an average projecting height of 0.1 μm or less.
The anisotropic conductive film according to claim 1, wherein the thickness is 7 μm.
【請求項3】 半田層の厚みが0.1μm〜5μmであ
ることを特徴とする請求項1または2に記載の異方導電
性フィルム。
3. The anisotropic conductive film according to claim 1, wherein the thickness of the solder layer is 0.1 μm to 5 μm.
【請求項4】 導通路がフィルム基材の両面から突出す
る突出部を備え、該突出部がその先端に薄膜状の半田層
を有することを特徴とする請求項1〜3に記載の異方導
電性フィルム。
4. The anisotropic conductive member according to claim 1, wherein the conductive path includes a projecting portion projecting from both surfaces of the film substrate, and the projecting portion has a thin-film solder layer at an end thereof. Conductive film.
JP2000342509A 2000-11-09 2000-11-09 Anisotropic conductive film Pending JP2002151549A (en)

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JP2011175970A (en) * 2011-02-07 2011-09-08 Hitachi Chem Co Ltd Circuit connecting material, and manufacturing method of connection structure of circuit member
CN106489195A (en) * 2014-07-11 2017-03-08 富士胶片株式会社 Anisotropic conductive component and multi-layered wiring board
WO2017094874A1 (en) * 2015-12-03 2017-06-08 国立大学法人東北大学 Semiconductor device and method for manufacturing semiconductor device
JPWO2017094874A1 (en) * 2015-12-03 2018-09-13 国立大学法人東北大学 Semiconductor device and manufacturing method of semiconductor device
WO2019065118A1 (en) * 2017-09-29 2019-04-04 富士フイルム株式会社 Semiconductor device manufacturing method and joint member
JPWO2019065118A1 (en) * 2017-09-29 2020-10-15 富士フイルム株式会社 Semiconductor device manufacturing method and joining members

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