JP3611463B2 - Manufacturing method of electronic parts - Google Patents

Manufacturing method of electronic parts Download PDF

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Publication number
JP3611463B2
JP3611463B2 JP30488998A JP30488998A JP3611463B2 JP 3611463 B2 JP3611463 B2 JP 3611463B2 JP 30488998 A JP30488998 A JP 30488998A JP 30488998 A JP30488998 A JP 30488998A JP 3611463 B2 JP3611463 B2 JP 3611463B2
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Japan
Prior art keywords
semiconductor chip
semiconductor chips
substrate
mounting
electronic component
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Expired - Fee Related
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JP30488998A
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Japanese (ja)
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JP2000133658A (en
Inventor
治人 永田
和郎 宮辻
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Priority to JP30488998A priority Critical patent/JP3611463B2/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、複数の半導体チップを装着した集合基板を分割して個片電子部品を製造する電子部品の製造方法に関するものである。
【0002】
【従来の技術】
端面電極用のスルーホールを複数有する集合基板上に半導体チップを実装し封止して個片電子部品を製造する方法の従来例を以下に示す。
【0003】
図6に、第1の製造方法の従来例を示す。集合基板61には端面電極用のスルーホール62が形成されており、各実装位置63に半導体チップ64を実装したあと、個々の半導体チップ64に対して個別に封止樹脂材料65を供給する。この際、スルーホール62内に前記の封止樹脂65が侵入しその表面に付着すると端面電極67のはんだ付け品質に悪影響が及ぶため、スルーホール62には封止樹脂65が入り込まない様に封止樹脂材料の供給量をコントロールする必要がある。このためには、封止樹脂を印刷方式で供給するか、あるいはシリンダに詰め込んだ封止素材をディスペンスにより個別にポッティングするなどの方法がとられる。上記樹脂素材を硬化させた後に点線66に沿ってカットし個片電子部品68のデバイス形態となる。
【0004】
図7に、第2の製造方法の従来例を示す。半導体チップ74を各実装位置73に実装した集合基板71を点線75に沿って個片電子部品76にカットし、カット前はスルーホール72であった箇所が端面電極77となる。封止方法は、カット後の個片電子部品76に金属製の箱型カバー78を取り付けその表面上部を覆い隠す方法、すなわちCAN封止と呼ばれる封止方法である。
【0005】
【発明が解決しようとする課題】
近年の電子機器の小型化が要求され、さらに高品位・高性能化、生産タクトアップ、低コスト化などデバイスの生産性に対する要求も加速的に厳しくなっている。前述の従来例1は、スルーホール内に封止樹脂が入り込まない様に個々の半導体チップに対して個別に封止樹脂を供給する手法であったが、たとえば印刷方法では印刷マスク製作上の限界から半導体チップの実装ピッチすなわちデバイスサイズに制約があり、概ね個片サイズが1cm四方程度もしくはそれ以上のサイズでないと、供給量の安定性が確保できなかった。また、個別ポッティング方式では前記のサイズの制約に加えてタクトが長くなるという問題も有していた。
【0006】
従来例2のCAN封止でも、サイズに対する制約があり、個片が3mm四方サイズ以下の超小型デバイスの製造には不適切でありかつコスト高の課題を残していた。本発明は、半導体チップを集合基板上に実装し樹脂でパッケージ化し、個片電子部品のデバイスサイズが3mm四方以下の超小型電子デバイスを、高品質、低コスト、短いタクトで製造することを目的とする。
【0007】
【課題を解決するための手段】
この課題を解決するために本発明は、複数の導電性を有するスルーホールを備えた集合基板上に、主成分が熱硬化性の樹脂素材であり、導電性の粒子を含有する異方性導電フィルムを貼り付けて前記スルーホールの開口を塞ぎ、次いで前記異方性導電フィルム上に複数の半導体チップを装着した後、上記複数の半導体チップを加熱圧着し、次いで集合基板上に封止樹脂層を形成して半導体チップおよび基板表面を封止した後、前記スルーホールに沿って集合基板を分割して、スルーホール部に端面電極が形成された個片電子部品を製造することを特徴とする。
【0008】
本発明は、異方性導電フィルムにより封止樹脂がスルーホール内に侵入することを防いで、端面電極の保護を図ることができ、加えて生産タクト短縮、生産性向上を図ることができる。
【0009】
【発明の実施の形態】
次に、本発明の実施形態を、図1ないし図5を用いて説明する。
【0010】
図4は、集合基板1の外観および断面を示すものであり、図4(a)は集合基板1の表面の平面図、図4(b)は図4(a)における一点鎖線16での断面図を示す。集合基板1は表面上の配線パターン5およびスルーホール2より構成されており、点線18で示した部分に半導体チップが接合される。配線パターン5は集合基板1の面内で2次元的に同じパターンの繰り返しであり、半導体チップの実装、封止後に点線17上を切断することにより個片電子部品となる。したがって半導体チップの実装工程においては基板は個片どうしが互いにつながった構造のいわゆる集合基板1である。また、集合基板1には、スルーホール2が規則的に形成されており、その内部は中空状態であるが、その内壁は金などの金属メッキ3が施されており半導体チップの接合部と配線パターン5上の電極5aを通じて電気的に導通している。個片となった後は、スルーホール2の内壁の金属メッキ3がデバイスとしてのはんだ付け用電極すなわち端面電極となる。
【0011】
図1は、図4に示した集合基板上への半導体チップ実装から個片分割まで一連のプロセスを示したものである。図1(a)に示した工程は、集合基板1上への接合用樹脂シート4の貼り付け工程である。接合用樹脂シート4として、主成分が熱硬化性の樹脂素材であり、導電性の粒子を含有する異方性導電フィルム(ACF)を用いるのが好ましいが、実装する半導体チップ個数や基板の平坦度によっては導電粒子を含まないタイプの熱硬化性の樹脂素材からなる接合用樹脂シートでも後述のバンプ7と配線パターン5の電極5aとの間の電気的導通は可能である。この際、複数個片に対する配線パターン5ならびにスルーホール2を同時に被覆する状態で接合用樹脂シート4を貼り付ける。接合用樹脂シート4を貼り付けるためには100℃程度の温度で基板に対して接合用樹脂シート4を圧着する。ここで本発明においては、スルーホール2の開口が接合用樹脂シート4によりふさがれているので、後に示す封止材料供給時にスルーホール2内に前記封止樹脂が侵入せず、端面電極3を汚染せず、デバイスの品質を確保できるという利点がある。
【0012】
次に図1(b)で示した工程は半導体チップ6の装着工程であり、専用の装着機を用いる。半導体チップ6の電極に形成されたバンプ7と、それに相対する基板上の電極5aが向き合うように位置決めしながら、かつ、接合用樹脂シート4を貼り付けた領域内の複数の装着位置に対して一つずつ装着する。
【0013】
次に図1(c)に示した工程は加熱圧着の工程であり、その斜視図を図2に示す。表面が平坦でありなおかつ200℃程度に加熱した加熱ツール8により複数個の半導体チップ6の上から同時に荷重10を加え、約20秒間集合基板1に押しつける。これによりバンプ7と配線パターン5の電極5aは接合用樹脂シート4中の導電粒子を介して互いに電気的に導通し、それと同時に接合用樹脂シート4は硬化しバンプ7と前記電極5aは導通したまま固定され、図1(d)に示した状態となる。本発明では2次元的に装着したすべての半導体チップ6を同時に加熱圧着するので、半導体チップ6一個あたりの実装タクトは圧着時間をチップ個数で割った値となり、従来の半導体チップ一個ずつの圧着に比べて非常に短い。たとえば図2に示した10×10=100個同時圧着の場合は、半導体チップ一個あたりに換算すると20秒÷100=0.2秒のタクトになる。また、圧着時には図3に示したようにテフロンなどの弾性シート14を加熱ツール8と半導体チップ6の間に挟み込むのが望ましく、これによりバンプ高さ、基板のパターン厚み、半導体チップ厚みのそれぞれのばらつきを吸収し、接合不良を低減するという効果がある。図3に示したように弾性シート14はツールの両側で巻き取るようにしておくと、シートの使用部分の交換が可能になる。
【0014】
次に図1(e)はパッケージ化および半導体チップ6の保護を目的とした封止の工程である。封止樹脂11は熱硬化タイプのエポキシ系樹脂であり、供給段階においてはペースト状であり、完成後の高さを均一にするためには図5に示したように、マスク19をコンタクトさせスキージ20で封止樹脂11をかきとる印刷方式による供給方法が好ましい。装着した半導体チップ6全ての範囲に一括で同時に供給することになるので、半導体チップ6一個あたりの供給タクトが個別供給に比べて非常に短い。たとえば個別ポッティングの場合は半導体チップ一個あたり約1秒を要していたのに対し、上記一括同時供給の場合は1チップ当たり0.003秒となり、3桁短くなる。この後、硬化炉内で加熱し、上記封止樹脂11を硬化させる。硬化条件としては、例えば、100℃2時間加熱後、150℃1時間加熱する。
【0015】
最後の工程図1(f)に示したように点線12の部分をダイシング装置内でカットし個片に分割する。
【0016】
最終的に図1(g)に示したように、封止樹脂11により半導体チップ6が保護され、封止樹脂11で汚染されない端面電極3を備えた高品質な個片電子部品9が完成する。この個片電子部品9のサイズは1.3mm×1.3mm四方サイズ、厚みは0.5mmであり、従来品と比較してそのサイズは約1/10となり、超小型化が実現できた。又、この小型化により基板の配線長が大幅に短縮でき、従来サイズ(3×3mm□以上)のパッケージと比較して、デバイスとしての電気特性が改善できた。一例として、挿入損失が従来品と比べて、0.5dBから0.4dBに低減できた。
【0017】
図6に示した従来の封止例では、封止樹脂の上面の平坦性や個片電子部品の形態が不均一であるので、個片電子部品を実装する際、吸着エラーなどの不具合が生じ、生産性の問題点があった。一方本発明では個片電子部品上をコートした封止樹脂の上面は平坦であり、個片電子部品の高さも一定であり、形状はそろったものであるので、この個片電子部品を回路基板上に実装する際、実装機での装着率はほぼ100%を達成し、認識エラーや吸着エラーなどによる実装時の不具合は出さないという利点もある。
【0018】
【発明の効果】
以上のように本発明によると、端面電極付きの小型電子部品の製造において、その端面電極を封止樹脂で汚染することなく高品質で製造し、かつ、製造タクトの短縮、生産性の向上といった製造上の有利な効果が得られる。また同時に、個片電子部品の形状が安定しており実装機での装着率が向上できるという利点が得られる。
【図面の簡単な説明】
【図1】本発明の一実施の形態による半導体チップ実装および封止工程を(a)〜(g)に示す断面図。
【図2】加熱圧着工程を示す斜視図。
【図3】弾性シートを挟んだ状態での加熱圧着工程を示す断面図。
【図4】集合基板の構造を示し、(a)はその平面図、(b)はその断面図。
【図5】印刷による封止樹脂供給工程を示す断面図。
【図6】従来の製造工程を示す断面図。
【図7】従来の製造工程を示す断面図。
【符号の説明】
1 集合基板
2 スルーホール
3 端面電極
4 接合用樹脂シート
6 半導体チップ
8 加熱ツール
9 個片電子部品
11 封止樹脂
14 弾性シート
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic component manufacturing method for manufacturing an individual electronic component by dividing an aggregate substrate on which a plurality of semiconductor chips are mounted.
[0002]
[Prior art]
A conventional example of a method of manufacturing an individual electronic component by mounting and sealing a semiconductor chip on an aggregate substrate having a plurality of through holes for end face electrodes is shown below.
[0003]
FIG. 6 shows a conventional example of the first manufacturing method. Through holes 62 for end face electrodes are formed in the collective substrate 61. After the semiconductor chip 64 is mounted at each mounting position 63, the sealing resin material 65 is individually supplied to each semiconductor chip 64. At this time, if the sealing resin 65 enters the through hole 62 and adheres to the surface thereof, the soldering quality of the end face electrode 67 is adversely affected. Therefore, the sealing resin 65 is sealed so that the sealing resin 65 does not enter the through hole 62. It is necessary to control the supply amount of the stopping resin material. For this purpose, a sealing resin is supplied by a printing method, or a sealing material packed in a cylinder is individually potted by dispensing. After the resin material is cured, the resin material is cut along a dotted line 66 to form a device form of the individual electronic component 68.
[0004]
FIG. 7 shows a conventional example of the second manufacturing method. The collective substrate 71 on which the semiconductor chip 74 is mounted at each mounting position 73 is cut into individual electronic components 76 along the dotted line 75, and the portion that was the through hole 72 before the cut becomes the end face electrode 77. The sealing method is a method of attaching a metal box-type cover 78 to the cut individual electronic component 76 and covering the upper surface thereof, that is, a sealing method called CAN sealing.
[0005]
[Problems to be solved by the invention]
In recent years, downsizing of electronic devices has been demanded, and demands for device productivity such as high quality / high performance, production tact increase, and cost reduction have become accelerating. The above-described conventional example 1 is a method of supplying the sealing resin individually to each semiconductor chip so that the sealing resin does not enter into the through hole. Therefore, there is a restriction on the mounting pitch of the semiconductor chip, that is, the device size, and the stability of the supply amount cannot be ensured unless the individual piece size is about 1 cm square or larger. In addition, the individual potting method has a problem that the tact becomes long in addition to the size restriction.
[0006]
Even in the CAN sealing of Conventional Example 2, there is a restriction on the size, which is inappropriate for manufacturing a microminiature device having a piece size of 3 mm square or less, and has left a problem of high cost. An object of the present invention is to mount a semiconductor chip on a collective substrate and package it with a resin, and to manufacture an ultra-small electronic device whose device size of an individual electronic component is 3 mm square or less with high quality, low cost, and short tact. And
[0007]
[Means for Solving the Problems]
In order to solve this problem, the present invention provides an anisotropic conductive material in which a main component is a thermosetting resin material and contains conductive particles on a collective substrate having a plurality of through holes having conductivity. A film is pasted to close the opening of the through hole, and then a plurality of semiconductor chips are mounted on the anisotropic conductive film, and then the plurality of semiconductor chips are thermocompression bonded, and then a sealing resin layer is formed on the collective substrate after sealing the semiconductor chip and the substrate surface to form the Suruho by dividing the aggregate board along the Le, characterized and Turkey to produce the end surface electrode is formed in the through hole portion pieces electronic component And
[0008]
The present invention prevents the sealing resin from penetrating into the through-hole by the anisotropic conductive film, can protect the end face electrode, and can also shorten the production tact and improve the productivity.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of the present invention will be described with reference to FIGS.
[0010]
4 shows the appearance and cross section of the collective substrate 1. FIG. 4 (a) is a plan view of the surface of the collective substrate 1, and FIG. 4 (b) is a cross section taken along the alternate long and short dash line 16 in FIG. 4 (a). The figure is shown. The collective substrate 1 is composed of a wiring pattern 5 and a through hole 2 on the surface, and a semiconductor chip is bonded to a portion indicated by a dotted line 18. The wiring pattern 5 is a two-dimensional repetition of the same pattern in the plane of the collective substrate 1, and becomes an individual electronic component by cutting the dotted line 17 after mounting and sealing a semiconductor chip. Therefore, in the semiconductor chip mounting process, the substrate is a so-called collective substrate 1 having a structure in which the individual pieces are connected to each other. Further, the through-holes 2 are regularly formed in the collective substrate 1 and the inside thereof is hollow, but the inner wall thereof is provided with metal plating 3 such as gold, so that the semiconductor chip joints and wirings are provided. The electrode 5a on the pattern 5 is electrically connected. After being separated into pieces, the metal plating 3 on the inner wall of the through hole 2 becomes a soldering electrode as a device, that is, an end face electrode.
[0011]
FIG. 1 shows a series of processes from mounting of semiconductor chips on the collective substrate shown in FIG. 4 to dividing into individual pieces. The process shown in FIG. 1A is a process of attaching the bonding resin sheet 4 on the collective substrate 1. As the bonding resin sheet 4, it is preferable to use an anisotropic conductive film (ACF) whose main component is a thermosetting resin material and contains conductive particles, but the number of semiconductor chips to be mounted and the flatness of the substrate are preferable. Depending on the degree, even a bonding resin sheet made of a thermosetting resin material that does not contain conductive particles can be electrically connected between the bumps 7 and the electrodes 5a of the wiring pattern 5 described later . At this time, the bonding resin sheet 4 is affixed in a state where the wiring patterns 5 and the through holes 2 for the plurality of pieces are simultaneously covered. In order to affix the bonding resin sheet 4, the bonding resin sheet 4 is pressure-bonded to the substrate at a temperature of about 100 ° C. Here, in the present invention, since the opening of the through hole 2 is blocked by the bonding resin sheet 4, the sealing resin does not enter the through hole 2 when the sealing material is supplied later, and the end face electrode 3 is formed. There is an advantage that the quality of the device can be ensured without contamination.
[0012]
Next, the process shown in FIG. 1B is a process for mounting the semiconductor chip 6, and a dedicated mounting machine is used. The bumps 7 formed on the electrodes of the semiconductor chip 6 and the electrodes 5a on the substrate facing the bumps 7 are positioned so as to face each other, and with respect to a plurality of mounting positions in the region where the bonding resin sheet 4 is attached. Wear one by one.
[0013]
Next, the process shown in FIG. 1C is a thermocompression bonding process, and a perspective view thereof is shown in FIG. A load 10 is simultaneously applied from above the plurality of semiconductor chips 6 by the heating tool 8 having a flat surface and heated to about 200 ° C., and pressed against the collective substrate 1 for about 20 seconds. As a result, the bump 7 and the electrode 5a of the wiring pattern 5 are electrically connected to each other through the conductive particles in the bonding resin sheet 4, and at the same time, the bonding resin sheet 4 is cured and the bump 7 and the electrode 5a are conductive. It is fixed as it is, and it will be in the state shown in FIG.1 (d). In the present invention, since all the semiconductor chips 6 mounted two-dimensionally are heat-bonded at the same time, the mounting tact for each semiconductor chip 6 is a value obtained by dividing the pressure-bonding time by the number of chips. It is very short compared. For example, in the case of 10 × 10 = 100 simultaneous crimping shown in FIG. 2, when converted to one semiconductor chip, the tact time is 20 seconds ÷ 100 = 0.2 seconds. Further, at the time of crimping, it is desirable to sandwich an elastic sheet 14 such as Teflon between the heating tool 8 and the semiconductor chip 6 as shown in FIG. 3, so that each of the bump height, the substrate pattern thickness, and the semiconductor chip thickness can be obtained. There is an effect of absorbing the variation and reducing the bonding failure. As shown in FIG. 3, if the elastic sheet 14 is wound on both sides of the tool, the used part of the sheet can be replaced.
[0014]
Next, FIG. 1E shows a sealing process for the purpose of packaging and protecting the semiconductor chip 6. The sealing resin 11 is a thermosetting epoxy resin and is in the form of a paste at the supply stage. In order to make the finished height uniform, as shown in FIG. A supply method by a printing method in which the sealing resin 11 is scraped off at 20 is preferable. Since all the semiconductor chips 6 that have been mounted are supplied simultaneously in a lump, the supply tact per semiconductor chip 6 is very short compared to individual supply. For example, in the case of individual potting, about 1 second is required for each semiconductor chip, whereas in the case of the collective simultaneous supply, 0.003 seconds per chip, which is 3 digits shorter. Thereafter, the sealing resin 11 is cured by heating in a curing furnace. As a curing condition, for example, after heating at 100 ° C. for 2 hours, heating is performed at 150 ° C. for 1 hour.
[0015]
Last step As shown in FIG. 1 (f), the portion of the dotted line 12 is cut in a dicing apparatus and divided into individual pieces.
[0016]
Finally, as shown in FIG. 1G, the semiconductor chip 6 is protected by the sealing resin 11, and the high-quality individual electronic component 9 including the end surface electrode 3 that is not contaminated by the sealing resin 11 is completed. . The size of the individual electronic component 9 is 1.3 mm × 1.3 mm square and the thickness is 0.5 mm. The size is about 1/10 compared to the conventional product, and the miniaturization can be realized. In addition, this miniaturization can significantly reduce the wiring length of the substrate, and the electrical characteristics as a device can be improved as compared with a package of a conventional size (3 × 3 mm □ or more). As an example, the insertion loss can be reduced from 0.5 dB to 0.4 dB compared to the conventional product.
[0017]
In the conventional sealing example shown in FIG. 6, since the flatness of the top surface of the sealing resin and the form of the individual electronic parts are not uniform, problems such as suction errors occur when mounting the individual electronic parts. There was a productivity problem. On the other hand, in the present invention, the upper surface of the sealing resin coated on the individual electronic component is flat, the height of the individual electronic component is constant, and the shape is uniform. When mounted on top, the mounting rate on the mounting machine is almost 100%, and there is also an advantage that there are no problems during mounting due to recognition errors or suction errors.
[0018]
【The invention's effect】
As described above, according to the present invention, in the manufacture of a small electronic component with an end face electrode, the end face electrode is manufactured with high quality without being contaminated with the sealing resin, and the manufacturing tact time is shortened and the productivity is improved. Advantageous manufacturing effects can be obtained. At the same time, there is an advantage that the shape of the individual electronic component is stable and the mounting rate in the mounting machine can be improved.
[Brief description of the drawings]
1A to 1G are cross-sectional views illustrating a semiconductor chip mounting and sealing process according to an embodiment of the present invention.
FIG. 2 is a perspective view showing a thermocompression bonding process.
FIG. 3 is a cross-sectional view showing a thermocompression bonding process with an elastic sheet sandwiched therebetween.
4A and 4B show a structure of an aggregate substrate, in which FIG. 4A is a plan view and FIG. 4B is a cross-sectional view thereof.
FIG. 5 is a cross-sectional view showing a sealing resin supply step by printing.
FIG. 6 is a cross-sectional view showing a conventional manufacturing process.
FIG. 7 is a cross-sectional view showing a conventional manufacturing process.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Collective substrate 2 Through-hole 3 End face electrode 4 Resin sheet | seat 6 for joining 6 Semiconductor chip 8 Heating tool 9 Piece electronic component 11 Sealing resin 14 Elastic sheet

Claims (3)

複数の導電性を有するスルーホールを備えた集合基板上に、主成分が熱硬化性の樹脂素材であり、導電性の粒子を含有する異方性導電フィルムを貼り付けて前記スルーホールの開口を塞ぎ、次いで前記異方性導電フィルム上に複数の半導体チップを装着した後、上記複数の半導体チップを加熱圧着し、次いで集合基板上に封止樹脂層を形成して半導体チップおよび基板表面を封止した後、前記スルーホールに沿って集合基板を分割して、スルーホール部に端面電極が形成された個片電子部品を製造することを特徴とする電子部品の製造方法。On an aggregate substrate having a plurality of conductive through holes, an anisotropic conductive film whose main component is a thermosetting resin material and containing conductive particles is pasted to open the through holes. Next, after mounting a plurality of semiconductor chips on the anisotropic conductive film, the plurality of semiconductor chips are thermocompression bonded, and then a sealing resin layer is formed on the collective substrate to seal the semiconductor chip and the substrate surface. After stopping, the collective substrate is divided along the through hole, and an individual electronic component having an end face electrode formed in the through hole portion is manufactured. 半導体チップ装着箇所が2次元的に配置され、その周辺に導電性を有するスルーホールを備えた集合基板の表面に、主成分が熱硬化性の樹脂素材であって導電性の粒子を含有する異方性導電フィルムか、あるいは、導電性の粒子を含有しない熱硬化性樹脂単体のフィルムからなる接合用樹脂シートを貼り付け、上記接合用樹脂シート上から所定の実装部分に半導体チップを装着し、上記装着された複数個の半導体チップの上方から加熱ツールで同時に加熱圧着することにより複数個の半導体チップと集合基板との接合および電気的接続を完了し、さらにペースト状の封止樹脂素材を上記接合済みの複数個の半導体チップ上に一括で供給し、この際前記ペースト状封止樹脂素材は半導体チップおよび接合用樹脂シートの表面を被覆し、前記スルーホール内部には侵入せず、前記封止樹脂素材を硬化させた後、個片にカットし個片電子部品を得ることを特徴とする電子部品の製造方法。A semiconductor chip mounting location is two-dimensionally arranged on the surface of a collective substrate having conductive through-holes around it, and the main component is a thermosetting resin material containing conductive particles. Affixing a bonding resin sheet consisting of an anisotropic conductive film or a film of a thermosetting resin alone containing no conductive particles, and mounting a semiconductor chip on a predetermined mounting portion from the bonding resin sheet, The bonding and electrical connection between the plurality of semiconductor chips and the collective substrate are completed by simultaneously heat-pressing the plurality of mounted semiconductor chips from above with a heating tool. Then, the paste-like encapsulating resin material covers the surfaces of the semiconductor chip and the bonding resin sheet, and is supplied to the plurality of bonded semiconductor chips. Does not enter inside the hole, it said after the sealing resin material is cured, method of manufacturing an electronic component, characterized in that to obtain a cut singulated electronic components into individual pieces. 加熱ツールで加熱圧着する際に、加熱ツールと半導体チップの間に弾性シートを挟むことを特徴とする請求項2記載の電子部品の製造方法。3. The method of manufacturing an electronic component according to claim 2, wherein an elastic sheet is sandwiched between the heating tool and the semiconductor chip when heat-pressing with the heating tool.
JP30488998A 1998-10-27 1998-10-27 Manufacturing method of electronic parts Expired - Fee Related JP3611463B2 (en)

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