JPH02103944A - Mounting method of semiconductor chip - Google Patents
Mounting method of semiconductor chipInfo
- Publication number
- JPH02103944A JPH02103944A JP63257568A JP25756888A JPH02103944A JP H02103944 A JPH02103944 A JP H02103944A JP 63257568 A JP63257568 A JP 63257568A JP 25756888 A JP25756888 A JP 25756888A JP H02103944 A JPH02103944 A JP H02103944A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- substrate
- bump
- electrode pattern
- conductive resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 229920005989 resin Polymers 0.000 claims abstract description 21
- 239000011347 resin Substances 0.000 claims abstract description 21
- 239000004840 adhesive resin Substances 0.000 claims description 14
- 229920006223 adhesive resin Polymers 0.000 claims description 14
- 238000007747 plating Methods 0.000 abstract description 4
- 239000000945 filler Substances 0.000 abstract description 3
- 230000004888 barrier function Effects 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract 2
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 13
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000004907 flux Effects 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000006355 external stress Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体チップを基板上にフェースダウンボンデ
ィング方式によりチップサイズで実装する半導体チップ
の実装方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor chip mounting method for mounting a semiconductor chip in chip size on a substrate by a face-down bonding method.
従来の技術
半導体チップを基板上にフェースダウンボンディング方
式によりチップサイズで実装する従来の方法として、第
４図に示すようにＰｂ−８ｎのはんだバンプ１１を用い
たフリップチップ方式が一般に行なわれていた。この方
式は半導体チップ３のＡＩ電極上にはんだバンプ１１を
設け、又接続する基板１側には電極パターン２上にメツ
キによりはんだ１２と電極パターン２の一部にはんだに
濡れない部材ではんだの流出を防止するダム１３を形成
し、前記のようにした半導体チップ３のはんだバンプ１
１とはんだ１２をフラックスを用いて還元雰囲気炉で溶
解して接続を行なっていた。2. Description of the Related Art As a conventional method for mounting a semiconductor chip on a substrate at a chip size using a face-down bonding method, a flip-chip method using Pb-8n solder bumps 11, as shown in FIG. 4, was generally used. . In this method, solder bumps 11 are provided on the AI electrodes of the semiconductor chip 3, and solder 12 is plated on the electrode pattern 2 on the board 1 side to be connected, and a part of the electrode pattern 2 is soldered with a material that does not get wet with solder. A dam 13 is formed to prevent leakage, and the solder bumps 1 of the semiconductor chip 3 are formed as described above.
The connection was made by melting 1 and solder 12 using flux in a reducing atmosphere furnace.
発明が解決しようとする課題 しかし、前述の従来技術には以下の問題がある。Problems that the invention aims to solve However, the above-mentioned conventional technology has the following problems.
第４図に示す方式で半導体チップ３を実装する場合、ま
ず基板１の電極パターン２側に、はんだ接続するための
はんだメツキやフラックス洗浄等の処理が必要であり、
さらにはんだバンプ１１とはんだ１２の溶解のために還
元雰囲気炉という特別の炉を用いるため、工程や装置が
複雑となり、コストアップにつながるという問題があっ
た。When mounting the semiconductor chip 3 using the method shown in FIG. 4, it is first necessary to perform treatments such as solder plating and flux cleaning on the electrode pattern 2 side of the substrate 1 for solder connection.
Furthermore, since a special furnace called a reducing atmosphere furnace is used to melt the solder bumps 11 and the solder 12, the process and equipment become complicated, leading to an increase in costs.
課題を解決するための手段
本発明の半導体チップの実装方法は、半導体チップの接
続電極あるいは基板の電極パターン上にバンプを形成す
るとともに、このバンプ上に導伝性樹脂層を設けて硬化
させ、さらに前記半導体チップの接続電極側の面と前記
基板の電極パターン側の面を対向させ、その対向する二
面間に接着樹脂を充満させることによって、前記半導体
チップを前記基板上に接合することを特徴とする。Means for Solving the Problems The semiconductor chip mounting method of the present invention includes forming bumps on the connection electrodes of the semiconductor chip or on the electrode pattern of the substrate, and providing a conductive resin layer on the bumps and curing them. Furthermore, the semiconductor chip is bonded to the substrate by making the connection electrode side surface of the semiconductor chip and the electrode pattern side surface of the substrate face each other, and filling the space between the two opposing surfaces with an adhesive resin. Features.
また本発明は、導電性樹脂層が硬化状態で弾性を何する
ことを特徴とするものを含む。Further, the present invention includes a conductive resin layer characterized in that the conductive resin layer has some elasticity in a cured state.
作用
本発明によれば、基板の電極パターン上又は半導体チッ
プの接続電極上に、バンプと接合するための処理を施す
必要がなく、また、接着樹脂として室温硬化性のものを
用いれば、硬化のための加熱炉を必要とすることもなく
も、しかも半導体チップの基板への接合を確実に行うこ
とができる。According to the present invention, there is no need to perform any treatment on the electrode pattern of the substrate or the connection electrode of the semiconductor chip for bonding with bumps, and if a room-temperature curable adhesive resin is used, the hardening process can be reduced. Moreover, the semiconductor chip can be reliably bonded to the substrate without the need for a heating furnace.
また導電性樹脂層として硬化状態で弾性を有するものを
用いることにより、半導体チップと基板の熱膨張の違い
により生じるストレスや外部応力の影響等を吸収し、さ
らに確実な接続を得ることができる。Furthermore, by using a conductive resin layer that is elastic in a cured state, it is possible to absorb stress caused by the difference in thermal expansion between the semiconductor chip and the substrate, the influence of external stress, etc., and to obtain a more reliable connection.
実施例
以下、本発明の実施例を第１図〜第３図の図面に基づい
て説明する。第１図は半導体チップ３を基板１上に実装
する時の状態を示す図であり、第２図は実装を完了した
後の図、第３図は第２図のバンプ６近傍の拡大図である
。半導体チップ３の接続電極となるＡｔ電極３ａ上には
絶縁性保護膜４が形成されておらず、この部分はあらか
じめ蒸着とメツキによりバリヤメタル５とバンプ６を形
成し、バンプ６上に転写法又はデイスペンサ等で硬化機
弾性をもつ導電性樹脂層９を設けて硬化させる。又基板
１上には、バンプ６と膨張係数が同程度になるように充
填材８を混在した接着樹脂７を塗布しておき、導電性樹
脂層９と基板１の電極パターン２を対向させて位置合わ
せし、半導体チップ３の加圧面３ｂを加圧した後、接着
樹脂７を硬化して半導体チップ３を基板１上に接合して
、コート材１０を塗布する。この時接着樹脂７の接着力
は弾性をもつ導電性樹脂層９の元に戻る力より強いもの
とする。Embodiments Hereinafter, embodiments of the present invention will be described based on the drawings of FIGS. 1 to 3. FIG. 1 is a diagram showing the state when the semiconductor chip 3 is mounted on the substrate 1, FIG. 2 is a diagram after the mounting is completed, and FIG. 3 is an enlarged diagram of the vicinity of the bump 6 in FIG. 2. be. The insulating protective film 4 is not formed on the At electrode 3a which becomes the connection electrode of the semiconductor chip 3, and a barrier metal 5 and bumps 6 are formed in advance on this part by vapor deposition and plating, and then a transfer method or a bump 6 is formed on the bump 6. A conductive resin layer 9 having curing machine elasticity is provided and cured using a dispenser or the like. Further, on the substrate 1, an adhesive resin 7 mixed with a filler 8 is applied so that the expansion coefficient is about the same as that of the bumps 6, and the conductive resin layer 9 and the electrode pattern 2 of the substrate 1 are made to face each other. After alignment and applying pressure to the pressure surface 3b of the semiconductor chip 3, the adhesive resin 7 is cured to bond the semiconductor chip 3 onto the substrate 1, and the coating material 10 is applied. At this time, the adhesive force of the adhesive resin 7 is made stronger than the returning force of the elastic conductive resin layer 9.
このようにすることにより、従来の実装方法に必要であ
った基板１の電極パターン２上へのはんだメツキやフラ
ックス洗浄等の処理が必要でなくなる。又接続にはんだ
を用いないので溶解のための特別の炉を用いな（でもよ
く、また接着樹脂７として室温硬化の樹脂を使用すれば
、接着樹脂を硬化させるための炉を必要としない。さら
に周囲温度が変化しても、接着樹脂７をバンプ６の膨張
係数と同程度のものとすることによって熱による影響を
少なくすることができ、又バンプ６の先端に硬化した弾
性をもつ導伝性樹脂層９を設けるので、半導体チップ３
と基板１の熱膨張の違いにより生じるストレスや外部応
力の影響等を吸収し、確実な接続を得ることができる。By doing this, processes such as solder plating and flux cleaning on the electrode pattern 2 of the substrate 1, which are necessary in the conventional mounting method, are no longer necessary. Also, since solder is not used for connection, a special furnace for melting is not necessary (and if a resin that hardens at room temperature is used as the adhesive resin 7, a furnace for curing the adhesive resin is not required. Even if the ambient temperature changes, the influence of heat can be reduced by making the adhesive resin 7 have a coefficient of expansion similar to that of the bumps 6. Also, the adhesive resin 7 can be made to have a coefficient of expansion comparable to that of the bumps 6, so that the effect of heat can be reduced. Since the resin layer 9 is provided, the semiconductor chip 3
It is possible to absorb the stress caused by the difference in thermal expansion between the substrate 1 and the substrate 1, the influence of external stress, etc., and obtain a reliable connection.
なお、導電性樹脂Ｂ９は電極パターン２と接続後に硬化
することもでき、接着樹脂７は半導体チップ３側に塗布
してもよい。又接着樹脂７は膨張係数がバンプ６と同程
度のものであれば充填材８を混在しなくてもよい。さら
に接着樹脂７中に仮止め用として紫外線硬化型樹脂を混
在することにより作業性を向上させることができる。Note that the conductive resin B9 may be cured after being connected to the electrode pattern 2, and the adhesive resin 7 may be applied to the semiconductor chip 3 side. Further, as long as the adhesive resin 7 has a coefficient of expansion comparable to that of the bumps 6, the filler 8 may not be mixed therein. Furthermore, workability can be improved by mixing an ultraviolet curing resin in the adhesive resin 7 for temporary fixing.
また、バンプ６を電極パターン２側に印刷等で設けて接
続を行なうことも可能であり、その場合には導電性樹脂
層９をバンプ６とＡＩ電極３Ａの間に形成すればよい。It is also possible to connect by providing the bumps 6 on the electrode pattern 2 side by printing or the like, and in that case, the conductive resin layer 9 may be formed between the bumps 6 and the AI electrode 3A.
発明の効果
以上述べたように本発明によれば、基板の電極パターン
又は半導体チップの接続電極に、バンプを接続するため
の処理を必要とせず、さらに特別の炉を用意しなくて良
いので、工程及び装置構成が簡単になり、低コスト化を
図ることができる。Effects of the Invention As described above, according to the present invention, there is no need for processing for connecting bumps to the electrode pattern of the substrate or the connection electrode of the semiconductor chip, and there is no need to prepare a special furnace. The process and device configuration are simplified, and costs can be reduced.
また、導電性樹脂層の弾性により、熱応力等の影響を吸
収し、さらに確実な接続を行うことができる。In addition, the elasticity of the conductive resin layer allows it to absorb the effects of thermal stress and the like, making it possible to achieve a more reliable connection.
第１図は本発明の一実施例の半導体チップの実装方法に
おける半導体チップを基板に接続する時の状態を示す断
面図、第２図は同実施例において半導体チップを基板に
接続した状態を示す断面図、第３図は第２図の状態にお
けるバンプ箇所を拡大した図、第４図は従来例のはんだ
バンプを用いたフリップチップ方式の実装方法における
接続状態図である。
１・・・基板、２・拳・電極パターン、３・拳・半導体
チップ、３ａ・・・Ａｌ電極（接続電極）、６・争・バ
ンプ、７・拳・接着樹脂、９・・・導伝性樹脂層。
代理人の氏名 弁理士 栗野重孝 はか１８第
図
ｂFIG. 1 is a sectional view showing a state in which a semiconductor chip is connected to a substrate in a semiconductor chip mounting method according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a state in which a semiconductor chip is connected to a substrate in the same embodiment. 3 is an enlarged view of the bump location in the state shown in FIG. 2, and FIG. 4 is a connection state diagram in a conventional flip-chip mounting method using solder bumps. 1...Substrate, 2.Fist/electrode pattern, 3.Fist/semiconductor chip, 3a...Al electrode (connection electrode), 6.War/bump, 7.Fist/adhesive resin, 9...Conduction sexual resin layer. Name of agent: Patent attorney Shigetaka Kurino Haka18 Figure b
Claims (2)
ーン上にバンプ形成するとともに、このバンプ上に導電
性樹脂層を設けて硬化させ、さらに前記半導体チップの
接続電極側の面、と前記基板の電極パターン側の面を対
向させ、その対向する二面間に接着樹脂を充満させるこ
とによって、前記半導体チップを前記基板上に接合する
ことを特徴とする半導体チップの実装方法。(1) Bumps are formed on the connection electrode of the semiconductor chip or the electrode pattern of the substrate, and a conductive resin layer is provided on the bump and cured, and then the surface on the connection electrode side of the semiconductor chip and the electrode of the substrate are formed. 1. A method for mounting a semiconductor chip, comprising: bonding the semiconductor chip onto the substrate by making the pattern-side surfaces face each other and filling the space between the two opposing faces with an adhesive resin.
ことを特徴とする請求項１記載の半導体チップの実装方
法。(2) The semiconductor chip mounting method according to claim 1, wherein the conductive resin has elasticity in a cured state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63257568A JPH02103944A (en) | 1988-10-13 | 1988-10-13 | Mounting method of semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63257568A JPH02103944A (en) | 1988-10-13 | 1988-10-13 | Mounting method of semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02103944A true JPH02103944A (en) | 1990-04-17 |
Family
ID=17308080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63257568A Pending JPH02103944A (en) | 1988-10-13 | 1988-10-13 | Mounting method of semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02103944A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0521523A (en) * | 1991-07-17 | 1993-01-29 | Matsushita Electric Works Ltd | Semiconductor device mounting substrate |
| JPH0661304A (en) * | 1992-08-06 | 1994-03-04 | Nec Corp | Method for bonding semiconductor chip |
| JPH09260431A (en) * | 1996-03-22 | 1997-10-03 | Nec Corp | Connection structure of flip chip mounting |
| US7875807B2 (en) | 2002-07-18 | 2011-01-25 | Ricoh Company, Ltd. | Elastic conductive resin, and electronic device including elastic conductive bumps made of the elastic conductive resin |
-
1988
- 1988-10-13 JP JP63257568A patent/JPH02103944A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0521523A (en) * | 1991-07-17 | 1993-01-29 | Matsushita Electric Works Ltd | Semiconductor device mounting substrate |
| JPH0661304A (en) * | 1992-08-06 | 1994-03-04 | Nec Corp | Method for bonding semiconductor chip |
| JPH09260431A (en) * | 1996-03-22 | 1997-10-03 | Nec Corp | Connection structure of flip chip mounting |
| US7875807B2 (en) | 2002-07-18 | 2011-01-25 | Ricoh Company, Ltd. | Elastic conductive resin, and electronic device including elastic conductive bumps made of the elastic conductive resin |
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