JPH02133936A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH02133936A
JPH02133936A JP28791388A JP28791388A JPH02133936A JP H02133936 A JPH02133936 A JP H02133936A JP 28791388 A JP28791388 A JP 28791388A JP 28791388 A JP28791388 A JP 28791388A JP H02133936 A JPH02133936 A JP H02133936A
Authority
JP
Japan
Prior art keywords
adhesive
semiconductor element
conductive particle
circuit board
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28791388A
Other languages
Japanese (ja)
Inventor
Yasuo Yamazaki
康男 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP28791388A priority Critical patent/JPH02133936A/en
Publication of JPH02133936A publication Critical patent/JPH02133936A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/335—Material
    • H01L2224/33505—Layer connectors having different materials
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    • H01L2224/3351—Function
    • H01L2224/33515—Layer connectors having different functions
    • H01L2224/33517—Layer connectors having different functions including layer connectors providing primarily mechanical support
    • H—ELECTRICITY
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    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
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    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
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    • H01L2224/83986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To sharply enhance reliability of a semiconductor device by a method wherein a gap material is added to an adhesive and particles whose coefficient of thermal expansion and elastic modulus are nearly identical with each other are distributed uniformly in a bonding part of a semiconductor element and a substrate. CONSTITUTION:A terminal 3 formed at a circuit board 2 is coated with an adhesive 5 containing a conductive particle 4. Then, when a semiconductor element 1 is mounted, the adhesive 5 coated in order to prevent the conductive particle 4 from being forced out from the terminal 3 is hardened. After that, the circuit board 2 is coated with an adhesive 6 containing a gap material 7; the semiconductor element 1 is mounted on it after an electrode 8 of the semiconductor element 1 has been aligned with the terminal 3 of the circuit board; the adhesive 6 is hardened by applying proper heat and a proper pressure. In this semiconductor device, a gap material whose coefficient of thermal expansion and elastic modulus are nearly identical to those of the conductive particle is added to a part, between the semiconductor element and the board, where the conductive particle does not exist; an internal stress whose magnitude is identical to that of the conductive particle is generated; thereby, the internal stress is dispersed uniformly over the whole semiconductor element; it is possible to restrain an exfoliation, a displacement, a crack and the like from being caused.

Description

【発明の詳細な説明】 ［産業上の利用分野コ 本発明は、半導体素子をフェースダウンで回路基板に実
装する構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure in which a semiconductor element is mounted face-down on a circuit board.

［従来の技術］ 従来の半導体装置は半導体素子を回路基板上にワイヤー
レスボンディングする場合、第２図に示すように曹記基
板の半導体素子の電極に対応した端子上に導電粒子を含
有した接着剤を選択的に塗布し、半導縁素子の電極と電
気的接続をとり、前記基板と半導体素子とを接着剤で固
定する構造であった。[Prior Art] In conventional semiconductor devices, when a semiconductor element is wirelessly bonded onto a circuit board, an adhesive containing conductive particles is placed on the terminal corresponding to the electrode of the semiconductor element of the Cao Chi substrate, as shown in Fig. 2. The structure was such that an adhesive was selectively applied, an electrical connection was established with the electrodes of the semiconductor edge element, and the substrate and the semiconductor element were fixed with an adhesive.

［発明が解決しようとする課題］ しかし、従来、の構造の半導体装置では、半導体素子と
基板との対向面間に導電粒子と接着剤が混在する部位と
、接着剤のみが存在する部位とがある。接着剤と、導電
粒子では、熱膨張係数や弾性係数が異なる。このため前
記半導体装置に熱応力や機械的応力が負荷された場合、
導電粒子の存在する部位と、接着剤のみが存在する部位
とが生じ、半導体素子中の内部応力にムラが出る。その
結果、半導体素子のはくりやずれ２割れ等が生じるとい
５課題を有する。そこで本発明は、このような課題を解
決するもので、接着剤中の内部応力な均一化し、高い信
頼性の提供を目的とする。[Problems to be Solved by the Invention] However, in a conventional semiconductor device having the structure shown in FIG. be. The adhesive and the conductive particles have different coefficients of thermal expansion and elasticity. Therefore, when thermal stress or mechanical stress is applied to the semiconductor device,
There are regions where conductive particles are present and regions where only adhesive is present, resulting in uneven internal stress within the semiconductor element. As a result, there are five problems such as peeling of the semiconductor element, deviation of the semiconductor element, and cracking in two. The present invention is intended to solve these problems, and aims to equalize the internal stress in the adhesive and provide high reliability.

［課題を解決す今ための手段］ 本発明の半導体装置は、半導体素子の電極と一路基板と
を導電粒子を介して電気的導通をとり、また接着剤を用
いて前記基板と半導体素子とを接着する構造をもつ半導
体装置において、接着剤中にギャップ材を混入する事を
特徴とする。[Means for Solving the Problems] The semiconductor device of the present invention provides electrical continuity between the electrodes of the semiconductor element and the substrate via conductive particles, and also connects the substrate and the semiconductor element using an adhesive. A semiconductor device having a bonding structure is characterized in that a gap material is mixed into the adhesive.

［実施例］ 第１図は本発明の実施例における断面図である１は半導
体素子で能動面を回路基板２に対向させる。回路基板゛
２は用途によりガラエボ基板やガラス基板を用いる。端
子３は回路基板２上に金属蒸着により形成する。４は樹
脂製の微粒子にＮ１メツキ等を施した導電粒子で、半導
体素子１の能動面にある電極８と回路基板・２の端子６
との間の電気的導通な、とっている。導電粒子４を含む
接着剤α５とギャップ材７を含む接着剤ｂ６は、半導体
素子１の電極８と回路基板２の端子３との位置がずれな
いように固定する役割をもつ。また、接着剤α５と接着
剤ｈ６には、同じ接着剤を用いる事によって、接着剤の
違いによる内部応力の位置による差が生じる事を防ぐ。[Embodiment] FIG. 1 is a cross-sectional view of an embodiment of the present invention. Reference numeral 1 denotes a semiconductor element whose active surface faces a circuit board 2. In FIG. As the circuit board 2, a glass board or a glass board is used depending on the purpose. The terminals 3 are formed on the circuit board 2 by metal vapor deposition. 4 is a conductive particle made of fine resin particles coated with N1 plating, etc., which connects the electrode 8 on the active surface of the semiconductor element 1 and the terminal 6 of the circuit board 2.
There is electrical continuity between the The adhesive α5 containing the conductive particles 4 and the adhesive b6 containing the gap material 7 have the role of fixing the electrodes 8 of the semiconductor element 1 and the terminals 3 of the circuit board 2 so that their positions do not shift. Furthermore, by using the same adhesive for the adhesive α5 and the adhesive h6, it is possible to prevent differences in internal stress depending on the position due to different adhesives.

７はギャップ材であり球形、楕円形２円筒形等の形状を
している。材質は、導電粒子４と同じ樹脂で作られてお
り、熱膨張係数や弾性係数は、導電粒子とほぼ同じであ
る。7 is a gap material having a spherical, elliptical, bicylindrical, etc. shape. The material is made of the same resin as the conductive particles 4, and the thermal expansion coefficient and elastic modulus are almost the same as the conductive particles.

まず、回路基板２に形成した端子５上に導電粒子４を含
んだ接着剤５を塗布する。次に半導体素子１を搭載する
時に、導電粒子４が端子３上からはみ出すことを防止す
るために塗布した接着剤５を硬化させる。その後、回路
基板２上にギャップ材７を含有した接着剤６を塗布し、
その上に半導体素子１を半導体素子１の電極８と回路基
板の端子３を位置合せして搭載し、適度な熱と圧力を加
え接着剤７を硬化させる。この方法により構成した半導
体装置においては、半導体、素子と基板との間の導電粒
子の存在しない部位に熱膨張係数や弾性係数が導電粒子
とほぼ同じであるギャップ材を混入し、導電粒子と同じ
大きさの内部応力を生じさせる事によって、半導体素子
全面にわたり内部応力が一様な半導体装置を構成するこ
とができるこの結果、熱や機械的応力が半導体装置に加
わった場合、第゛２図に示した従来の半導体装置のよう
な導電粒子の存在する部位と存在しない部位での接着剤
の内部応力の太き、な差は著しく小さくすることができ
、内部応力が、半導体素子全体に均一に分散され、ばく
りゃずれ２割れなどの発生を押さえることができる。First, adhesive 5 containing conductive particles 4 is applied onto terminals 5 formed on circuit board 2 . Next, when mounting the semiconductor element 1, the applied adhesive 5 is cured in order to prevent the conductive particles 4 from protruding from the terminals 3. After that, an adhesive 6 containing a gap material 7 is applied on the circuit board 2,
The semiconductor element 1 is mounted thereon with the electrodes 8 of the semiconductor element 1 and the terminals 3 of the circuit board aligned, and appropriate heat and pressure are applied to harden the adhesive 7. In a semiconductor device constructed using this method, a gap material whose coefficient of thermal expansion and elasticity is almost the same as that of the conductive particles is mixed into a region between the semiconductor, element, and substrate where there are no conductive particles. By generating an internal stress of a certain magnitude, it is possible to construct a semiconductor device in which the internal stress is uniform over the entire surface of the semiconductor element.As a result, when heat or mechanical stress is applied to the semiconductor device, the The large difference in the internal stress of the adhesive between areas where conductive particles are present and areas where conductive particles are not present, as in the conventional semiconductor device shown, can be significantly reduced, and the internal stress can be uniformly applied to the entire semiconductor element. It can be dispersed and prevent the occurrence of cracking and cracking in two.

［発明の効果］ ・本発明は、以上説明したように、接着剤中にギャップ
材を混入し、半導体素子と基板との接着部分に熱膨張係
数や弾性係数のほぼ同じ粒子を一様に分布することによ
って、内部応力の位置による偏差を小さくすることが可
能となり、半導体装置の信頼性を大幅に向上させること
ができる。[Effects of the Invention] - As explained above, the present invention mixes a gap material into the adhesive, and uniformly distributes particles with substantially the same coefficient of thermal expansion and elasticity in the bonded area between the semiconductor element and the substrate. By doing so, it becomes possible to reduce the deviation of internal stress depending on the position, and the reliability of the semiconductor device can be greatly improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明の一実施例の断面図を示す回層２図は
、従来の半導体装置の断面図を示す図・・・・・・・・
・半導体素子 ・・・・・・・・・回路基板 ・・・・・・・・・端　子 ・・・・・・・・・導電粒子 ・・・・・・・・・接着剤α ・・・・・・・・・接着剤ｂ ・・・・・・・・・ギャップ材 ・・・・・・・・・電極 以上Figure 1 shows a cross-sectional view of an embodiment of the present invention. Figure 2 shows a cross-sectional view of a conventional semiconductor device.
・Semiconductor element...Circuit board...Terminal...Conductive particles...Adhesive α...・・・・・・Adhesive b ・・・・・・Gap material・・・・・・More than electrode

Claims (1)

【特許請求の範囲】[Claims] 半導体素子の電極と回路基板とを導電粒子を介して電気
的導通をとり、また接着剤を用いて前記基板と半導体素
子とを接着する構造をもつ半導体装置において、接着剤
中にギャップ材を混入した事を特徴とする半導体装置。In a semiconductor device having a structure in which an electrode of a semiconductor element and a circuit board are electrically connected through conductive particles, and the substrate and the semiconductor element are bonded using an adhesive, a gap material is mixed into the adhesive. A semiconductor device characterized by:
JP28791388A 1988-11-15 1988-11-15 Semiconductor device Pending JPH02133936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28791388A JPH02133936A (en) 1988-11-15 1988-11-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28791388A JPH02133936A (en) 1988-11-15 1988-11-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02133936A true JPH02133936A (en) 1990-05-23

Family

ID=17723348

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28791388A Pending JPH02133936A (en) 1988-11-15 1988-11-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02133936A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998010465A1 (en) * 1996-09-05 1998-03-12 Seiko Epson Corporation Connecting structure of semiconductor element, liquid crystal display device using the structure, and electronic equipment using the display device
US5804882A (en) * 1995-05-22 1998-09-08 Hitachi Chemical Company, Ltd. Semiconductor device having a semiconductor chip electrically connected to a wiring substrate
EP1029346A1 (en) * 1997-08-22 2000-08-23 Vertical Circuits, Inc. Vertical interconnect process for silicon segments with thermally conductive epoxy preform
US6134118A (en) * 1995-01-19 2000-10-17 Cubic Memory Inc. Conductive epoxy flip-chip package and method
JP2006108523A (en) * 2004-10-08 2006-04-20 Hitachi Chem Co Ltd Method of connecting electrical component using anisotropic conductive film
US7215018B2 (en) 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
US7245021B2 (en) 2004-04-13 2007-07-17 Vertical Circuits, Inc. Micropede stacked die component assembly
US20120291454A1 (en) * 2011-05-20 2012-11-22 Baker Hughes Incorporated Thermoelectric Devices Using Sintered Bonding

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6134118A (en) * 1995-01-19 2000-10-17 Cubic Memory Inc. Conductive epoxy flip-chip package and method
US5804882A (en) * 1995-05-22 1998-09-08 Hitachi Chemical Company, Ltd. Semiconductor device having a semiconductor chip electrically connected to a wiring substrate
WO1998010465A1 (en) * 1996-09-05 1998-03-12 Seiko Epson Corporation Connecting structure of semiconductor element, liquid crystal display device using the structure, and electronic equipment using the display device
US6940180B1 (en) 1996-09-05 2005-09-06 Seiko Epson Corporation Semiconductor device connecting structure, liquid crystal display unit based on the same connecting structure, and electronic apparatus using the same display unit
US7084517B2 (en) 1996-09-05 2006-08-01 Seiko Epson Corporation Semiconductor device connecting structure, liquid crystal display unit based on the same connecting structure, and electronic apparatus using the same display unit
EP1029346A1 (en) * 1997-08-22 2000-08-23 Vertical Circuits, Inc. Vertical interconnect process for silicon segments with thermally conductive epoxy preform
EP1029346A4 (en) * 1997-08-22 2006-01-18 Vertical Circuits Inc Vertical interconnect process for silicon segments with thermally conductive epoxy preform
US7215018B2 (en) 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
US7245021B2 (en) 2004-04-13 2007-07-17 Vertical Circuits, Inc. Micropede stacked die component assembly
US7535109B2 (en) 2004-04-13 2009-05-19 Vertical Circuits, Inc. Die assembly having electrical interconnect
JP2006108523A (en) * 2004-10-08 2006-04-20 Hitachi Chem Co Ltd Method of connecting electrical component using anisotropic conductive film
US20120291454A1 (en) * 2011-05-20 2012-11-22 Baker Hughes Incorporated Thermoelectric Devices Using Sintered Bonding

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