JPH02135763A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02135763A JPH02135763A JP63290780A JP29078088A JPH02135763A JP H02135763 A JPH02135763 A JP H02135763A JP 63290780 A JP63290780 A JP 63290780A JP 29078088 A JP29078088 A JP 29078088A JP H02135763 A JPH02135763 A JP H02135763A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor element
- bumps
- cap
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000007789 sealing Methods 0.000 claims abstract description 23
- 239000004020 conductor Substances 0.000 claims abstract description 20
- 239000000853 adhesive Substances 0.000 claims abstract description 16
- 230000001070 adhesive effect Effects 0.000 claims abstract description 16
- 230000017525 heat dissipation Effects 0.000 abstract description 13
- 238000000034 method Methods 0.000 description 6
- 238000001723 curing Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000016 photochemical curing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/14181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野１
本発明は、ギヤングボンディング法により実装される半
導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a semiconductor device that is mounted by a gigantic bonding method.
［従来の技術］
バンプを介して半導体素子と基板を接合するギヤングボ
ンディング法は、半導体素子の片面から電極を取る構造
になっており、素子側に形成されるバンプのボンディン
グ面積に技術的な限界があり、これ以上の多ピン化は望
めないのが実情であった。また、半導体素子からの放熱
がバンプを介して行われるため、放熱性が従来のワイヤ
ーボンディング法による実装法に比べ劣るという欠点が
ある。この為、ギヤングボンディング後、素子の裏面に
放熱板を接着したり、バネにより封止用キャップを圧接
し、放熱性の向上を図っている。[Prior art] The gigantic bonding method, which connects a semiconductor element and a substrate through bumps, has a structure in which electrodes are taken from one side of the semiconductor element, and there are technical limitations on the bonding area of the bumps formed on the element side. The reality is that there are limits and it is impossible to increase the number of pins even further. Furthermore, since heat is dissipated from the semiconductor element through the bumps, there is a drawback that the heat dissipation performance is inferior to that of the conventional wire bonding mounting method. For this reason, after the gigantic bonding, a heat dissipation plate is adhered to the back surface of the element, or a sealing cap is pressed against the element using a spring to improve heat dissipation.
第２図及び第３図はかかる従来の封止構造を示すもので
、第２図はキャップ封止の場合、第３図は樹脂封止の場
合を示す。第２ｔｑｃおいて、■は基板、２は基板ｌ上
に形成された導体パターン、３は半導体素子、４はバン
プ、５は放熱用ヒートシンク、６は封止用キャップで、
キャップ６は接着剤７により基板１に接着されている。FIGS. 2 and 3 show such conventional sealing structures, with FIG. 2 showing the case of cap sealing and FIG. 3 showing the case of resin sealing. In the second tqc, ■ is a substrate, 2 is a conductor pattern formed on the substrate l, 3 is a semiconductor element, 4 is a bump, 5 is a heat sink for heat dissipation, 6 is a sealing cap,
The cap 6 is bonded to the substrate 1 with an adhesive 7.
また、第３図において、８は封止樹脂である。Moreover, in FIG. 3, 8 is a sealing resin.
［発明が解決しようとする課題Ｊ
しかしながら、上述の如き従来例においては、バンプ４
と半導体素子３及びバンプ４と導体パターン２はそれぞ
れ金属的に結合されているため、基板１と半導体素子３
の膨張差による応力を吸収できず、従って、ヒートサイ
クルのような熱ストレスによりクラック等が入り信頼性
に欠けるという欠点があった。また、キャップ封止構造
のものでは、放熱性の向上を図るために放熱用ヒートシ
ンク５を必要とするため、半導体素子の両面に電極を形
成することはできなかった。さらに、従来のギヤングボ
ンディング法は、半導体素子の片面からしか電気的接合
ができなく、両面構造の半導体素子の実装ができないと
いう欠点があった。[Problem to be solved by the invention J However, in the conventional example as described above, the bump 4
, the semiconductor element 3 and the bumps 4 and the conductor pattern 2 are each metallically bonded, so that the substrate 1 and the semiconductor element 3 are bonded to each other metallically.
It is not possible to absorb the stress caused by the difference in expansion between the two, and as a result, cracks occur due to thermal stress such as a heat cycle, resulting in a lack of reliability. Further, in the cap-sealed structure, a heat sink 5 for heat dissipation is required in order to improve heat dissipation, and therefore electrodes cannot be formed on both sides of the semiconductor element. Furthermore, the conventional gigantic bonding method has the disadvantage that electrical bonding can only be performed from one side of a semiconductor element, and it is not possible to mount a semiconductor element with a double-sided structure.
本発明は上記欠点に鑑みなされたもので、その目的とす
るところは、ギヤングボンディングされた両面構造の半
導体素子の放熱の向上が図れ、かつ多ピン化が可能で、
しかも、信頼性の高い半導体装置を提供するにある。The present invention has been made in view of the above-mentioned drawbacks, and its purpose is to improve the heat dissipation of a semiconductor element with a double-sided structure that is subjected to giant bonding, and to increase the number of pins.
Furthermore, it is possible to provide a highly reliable semiconductor device.
［課題を解決するための手段］
本発明は上記課題を解決するため、表面に導体パターン
が形成された基板と、該基板上に搭載される両面構造の
半導体素子と、該半導体素子上に被せられ内面に導体パ
ターンが形成された封止用キャップとを、前記半導体素
子の両面に配されるそれぞれのバンプを介して接合して
成る半導体装置であって、前記それぞれのバンプを前記
各導体パターンの所定位置若しくは半導体素子の所定位
置に当接すると共に、前記封止用キャップの開目端を前
記基板に収縮性の高い接着剤で接着したことを特徴とす
る。[Means for Solving the Problems] In order to solve the above problems, the present invention provides a substrate on which a conductive pattern is formed, a semiconductor element with a double-sided structure mounted on the substrate, and a semiconductor element with a double-sided structure mounted on the substrate. and a sealing cap having a conductive pattern formed on the inner surface thereof, the semiconductor device is bonded to a sealing cap via respective bumps arranged on both sides of the semiconductor element, wherein each of the bumps is connected to each of the conductive patterns. or a predetermined position of the semiconductor element, and the open end of the sealing cap is bonded to the substrate with a highly shrinkable adhesive.
［作 用］
上記構成により、接着剤の硬化時の収縮力により半導体
素子は基板に圧接され、両面構造の半導体素子と封止用
キャップと基板間に電気的接合が（写られる。また、半
導体素子の表面からバンプを介して封止用キャップに放
熱が行われる。さらに、半導体素子と基板及び半導体素
子と封止用キャップとはバンプを介して圧接結合されて
いるため、半導体素子と基板または封止用キャップの膨
張差による応力の影響を受けない。[Function] With the above configuration, the semiconductor element is pressed against the substrate by the contraction force when the adhesive hardens, and an electrical connection is formed between the double-sided semiconductor element, the sealing cap, and the substrate. Heat is radiated from the surface of the element to the sealing cap via the bumps.Furthermore, since the semiconductor element and the substrate and the semiconductor element and the sealing cap are pressure bonded via the bumps, the semiconductor element and the substrate or Not affected by stress due to differential expansion of the sealing cap.
［実施例］
第１図は本発明の一実施例を示すもので、１は表面に導
体パターン２ａが形成された基板、３は両面にバンプ４
ａ、４ｂを有する半導体素子で、前記導体パターン２の
所定位置に一方のバンプ４ａが位置するように載置され
ている。６は内面に導体パターン２ｂが形成された気密
性を有する封止用キャップで、その開口端は収縮性の高
い接着剤９により基板１に接着されている。なお、キャ
ップ６内面に形成された導体パターン２ｂと、基板１上
に形成された導体パターン２ａとの電気的コンタクトは
、周知のバネ式接点、ソケット式、バンプ接合等により
行なう。[Embodiment] FIG. 1 shows an embodiment of the present invention, in which 1 is a substrate having a conductor pattern 2a formed on its surface, and 3 is a substrate having bumps 4 on both sides.
The semiconductor element has bumps a and 4b, and is placed on the conductor pattern 2 so that one bump 4a is located at a predetermined position. Reference numeral 6 denotes an airtight sealing cap having a conductive pattern 2b formed on its inner surface, and its open end is adhered to the substrate 1 with a highly shrinkable adhesive 9. The electrical contact between the conductor pattern 2b formed on the inner surface of the cap 6 and the conductor pattern 2a formed on the substrate 1 is made by a well-known spring type contact, socket type, bump bonding, or the like.
次に、本実施例の実装方法を説明する。まず、パターン
ニングされた基板１上に、両面にバンプ４ａ、４ｂを有
する半導体素子３を位置決めして搭載し、この上から内
面にパターンニングされた封止用キャップ６を被せる。Next, the implementation method of this embodiment will be explained. First, a semiconductor element 3 having bumps 4a and 4b on both sides is positioned and mounted on a patterned substrate 1, and a sealing cap 6 whose inner surface is patterned is placed over the semiconductor element 3.
そして、このキャップ６を収縮性の高い接着剤９により
基板１に接着する。接着剤９は収縮性の高いものが選択
されているので、硬化時の収縮力により半導体素子３は
基板ｌに圧接され、基板１の導体パターン２ａバンプ４
ａ−半導体素子３−バンプ４ｂ−キャンプ６の導体パタ
ーン２ｂの電気的コンタクトを得る。Then, this cap 6 is adhered to the substrate 1 using a highly shrinkable adhesive 9. Since the adhesive 9 is selected to have a high shrinkage property, the semiconductor element 3 is pressed against the substrate 1 by the shrinkage force during curing, and the conductor pattern 2a of the substrate 1 is bonded to the bump 4.
a-Semiconductor element 3-bump 4b-conductor pattern 2b of camp 6 electrical contact is obtained.
ここで、キャップ６の凹部の凹み寸法Ｈを半導体素子３
の厚みｔとほぼ同じになるようにしておく。このように
して半導体素子３の上にキャップ６を被せると、半導体
素子３の両面のバンプ４ａ４ｂの高さの和の分だけキャ
ップ６は基板１より浮くことになり、この浮いた部分に
前述の硬化時に収縮する接着剤９を塗布し、半導体素子
３に硬化時に荷重が加わるようにする。Here, the concave dimension H of the concave portion of the cap 6 is defined as the concave dimension H of the concave portion of the cap 6
The thickness should be approximately the same as the thickness t. When the cap 6 is placed over the semiconductor element 3 in this manner, the cap 6 is lifted from the substrate 1 by the sum of the heights of the bumps 4a4b on both sides of the semiconductor element 3, and this floating portion is covered with the above-mentioned An adhesive 9 that shrinks when cured is applied so that a load is applied to the semiconductor element 3 when cured.
このように構成することにより、下記のような効果を奏
する。With this configuration, the following effects can be achieved.
■ 半導体素子３のｈ！１．熱が、バンプ４ａ、４ｂと
キャップ６を通して半導体素子３の両面から行われ、前
述のギヤングボンディングの欠点が解決される。■ h of semiconductor element 3! 1. Heat is applied from both sides of the semiconductor element 3 through the bumps 4a, 4b and the cap 6, thus solving the drawbacks of gigantic bonding described above.
■ 半導体素子３の接合と封止が同時に行え、工程の合
理化が図れる。(2) Bonding and sealing of the semiconductor element 3 can be performed at the same time, streamlining the process.
■ 通常、半導体素子３を基板１に接合する際、金バン
プの場合は５００℃程度、半田バンプの場合でも２５０
〜３００℃の加熱工程を必要とするが、本実施例では接
着剤９の硬化温度（１５０〜２００℃程度）でよく、熱
によるダメージを素子３及び基板１に与えずに実装でき
る。■ Normally, when bonding the semiconductor element 3 to the substrate 1, the temperature is about 500°C for gold bumps, and 250°C for solder bumps.
Although a heating step of ~300° C. is required, in this embodiment, the curing temperature of the adhesive 9 (about 150° C. to 200° C.) is sufficient, and the device 3 and the substrate 1 can be mounted without causing damage due to heat.
接着剤９に光硬化性樹脂を採用した場合は、加熱工程は
不要である。この場合、キャップ６と基板１間にバンプ
を設けて電気的接合を得るようにしてもよい。If a photocurable resin is used as the adhesive 9, the heating step is not necessary. In this case, a bump may be provided between the cap 6 and the substrate 1 to obtain electrical connection.
■ キャップ６と基８５ｉ１に金属的な接点をバネまた
はソケットで形成するには、キャップ６の方に接点を作
っておくか、または半導体素子３を搭載する前に基板１
に形成しておけば、素子３にダメージを与えることはな
い。■ To form a metal contact between the cap 6 and the base 85i1 using a spring or a socket, the contact must be made on the cap 6 or the base 85i1 must be connected to the base 85i1 before the semiconductor element 3 is mounted.
If it is formed in this way, the element 3 will not be damaged.
■ 導体パターン２ｂを有するキャップ６とバンプ４ｂ
及びバンプ４ａと導体パターン２ａを有する基板１との
間は圧接されている為、ヒートサイクルのような熱スト
レスによる半導体素子３と基板１またはキャップ６の膨
張差により、バンプ４ａ、４ｂが基板１またはキャップ
６の導体パターン２上を摺動し、基板ｌや素子３に応力
がかからない構造となり、信頼性の向上が図れる。■ Cap 6 and bump 4b having conductor pattern 2b
Since the bumps 4a and the substrate 1 having the conductor pattern 2a are in pressure contact with each other, the bumps 4a and 4b are caused by the difference in expansion between the semiconductor element 3 and the substrate 1 or the cap 6 due to thermal stress such as a heat cycle. Alternatively, it slides on the conductor pattern 2 of the cap 6, resulting in a structure in which no stress is applied to the substrate 1 or the element 3, thereby improving reliability.
■ 両面構造の半導体素子の実装が可能となり、バンプ
のボンディング面積を従来の約２倍にとれることで多ピ
ン化が図れる。■ It becomes possible to mount semiconductor elements with a double-sided structure, and the bump bonding area can be approximately doubled compared to conventional technology, allowing for a larger number of pins.
また、両面構造の半導体素子の実装が可能となったので
半導体素子自体の集積化が図れる。Furthermore, since it has become possible to mount semiconductor elements with a double-sided structure, the semiconductor elements themselves can be integrated.
これにより、高速化、高築積化した両面構造の半導体素
子の両面実装ができるようになったことで、製造コスト
の低減が図れる。This makes it possible to perform double-sided mounting of semiconductor elements with a double-sided structure at higher speeds and higher stack-up rates, thereby reducing manufacturing costs.
■ 両面構造の半導体素子３の両面にバンプ４ａ、４ｂ
を形成することにより、放熱伝路を増やすことができ、
放熱特性を向上させることができる。■ Bumps 4a and 4b on both sides of the double-sided semiconductor element 3
By forming, the heat dissipation path can be increased.
Heat dissipation characteristics can be improved.
なお、上記実施例では、バンプ４ａ、４ｂは半導体素子
３に形成されているが、基板Ｉの導体パターン２ａ上ま
たは封止用キャップ６の導体パターン２ｂ上に形成して
もよい。また、バンプ４の材料は、酸化しない金が適当
であるが、バンプ全体が金である必要はなく、中心が銅
で表面がニッケルメッキまたは金メツキというように、
多層のバンプでもよい。さらに、キャップ６と基板１の
接合用の接着剤９は収縮性が高く、半導体素子３とバン
プ４に硬化時に荷重が加わるようなものであればよく、
例えば、エポキシ樹脂やアクリル樹脂が適当である。硬
化方法も熱硬化性でもよいし、光硬化性のものでもよい
。In the above embodiment, the bumps 4a and 4b are formed on the semiconductor element 3, but they may be formed on the conductor pattern 2a of the substrate I or the conductor pattern 2b of the sealing cap 6. In addition, the appropriate material for the bump 4 is gold that does not oxidize, but it is not necessary that the entire bump be made of gold; for example, the center is copper and the surface is nickel plated or gold plated.
A multilayer bump may also be used. Furthermore, the adhesive 9 for bonding the cap 6 and the substrate 1 may be of any type as long as it has high shrinkage and applies a load to the semiconductor element 3 and bumps 4 during curing.
For example, epoxy resin or acrylic resin is suitable. The curing method may be thermosetting or photocuring.
［発明の効果］
本発明は上記のように、表面に導体パターンが形成され
た基板と、該基板上に搭載される両面構造の半導体素子
と、該半導体素子上に被せられ内面に導体パターンが形
成された封止用キャップとを、前記半導体素子の両面に
配されるそれぞれのバンプを介して接合して成る半導体
装置であって、前記それぞれのバンプを前記各導体パタ
ーンの所定位置若しくは半導体素子の所定位置に当接す
ると共に、前記封止用キャップの開口端を前記基板に収
縮性の高い接着剤で接着したことを特徴とするので、ギ
ヤングボンディングされた両面構造の半導体素子の放熱
の向上が図れ、かつ多ピン化が可能で、しかも、信頼性
の高い半導体装置を提供することができる。[Effects of the Invention] As described above, the present invention includes a substrate having a conductive pattern formed on its surface, a semiconductor element with a double-sided structure mounted on the substrate, and a semiconductor element placed on the semiconductor element and having a conductive pattern formed on its inner surface. a formed sealing cap via respective bumps arranged on both sides of the semiconductor element, the respective bumps being connected to predetermined positions of each of the conductor patterns or to the semiconductor element. In addition, the opening end of the sealing cap is bonded to the substrate with a highly shrinkable adhesive, thereby improving heat dissipation of a semiconductor element having a double-sided structure that is subjected to giant bonding. Accordingly, it is possible to provide a semiconductor device that can achieve high reliability, can have a large number of pins, and has high reliability.
第１図は本発明の一実施例を示す断面図、第２図及び第
３図はそれぞれ従来例を示す断面図である。
■・・・基板、２ａ、 ２ｂ・・・導体パターン、３
・・・半導体素子、４ａ、４ｂ・・・バンプ、６・・・
封止用キャップ、９・・・接着剤。FIG. 1 is a sectional view showing one embodiment of the present invention, and FIGS. 2 and 3 are sectional views showing conventional examples, respectively. ■...Substrate, 2a, 2b...Conductor pattern, 3
...Semiconductor element, 4a, 4b...Bump, 6...
Sealing cap, 9...adhesive.
Claims (1)
上に搭載される両面構造の半導体素子と、該半導体素子
上に被せられ内面に導体パターンが形成された封止用キ
ャップとを、前記半導体素子の両面に配されるそれぞれ
のバンプを介して接合して成る半導体装置であって、前
記それぞれのバンプを前記各導体パターンの所定位置若
しくは半導体素子の所定位置に当接すると共に、前記封
止用キャップの開口端を前記基板に収縮性の高い接着剤
で接着したことを特徴とする半導体装置。(1) A substrate with a conductor pattern formed on its surface, a semiconductor element with a double-sided structure mounted on the substrate, and a sealing cap placed over the semiconductor element and with a conductor pattern formed on its inner surface, A semiconductor device in which the semiconductor element is bonded via respective bumps arranged on both sides of the semiconductor element, wherein each of the bumps is brought into contact with a predetermined position of each of the conductor patterns or a predetermined position of the semiconductor element, and the seal is 1. A semiconductor device, wherein an open end of a stopper cap is bonded to the substrate using a highly shrinkable adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63290780A JPH02135763A (en) | 1988-11-16 | 1988-11-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63290780A JPH02135763A (en) | 1988-11-16 | 1988-11-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02135763A true JPH02135763A (en) | 1990-05-24 |
| JPH0583187B2 JPH0583187B2 (en) | 1993-11-25 |
Family
ID=17760414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63290780A Granted JPH02135763A (en) | 1988-11-16 | 1988-11-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02135763A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000067315A1 (en) * | 1999-05-03 | 2000-11-09 | Stmicroelectronics S.A. | Semiconductor chip package |
| US6294408B1 (en) * | 1999-01-06 | 2001-09-25 | International Business Machines Corporation | Method for controlling thermal interface gap distance |
| JP2017059774A (en) * | 2015-09-18 | 2017-03-23 | セイコーインスツル株式会社 | Electronic part |
| JP2017126645A (en) * | 2016-01-13 | 2017-07-20 | セイコーインスツル株式会社 | Electronic component |
-
1988
- 1988-11-16 JP JP63290780A patent/JPH02135763A/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6294408B1 (en) * | 1999-01-06 | 2001-09-25 | International Business Machines Corporation | Method for controlling thermal interface gap distance |
| WO2000067315A1 (en) * | 1999-05-03 | 2000-11-09 | Stmicroelectronics S.A. | Semiconductor chip package |
| JP2017059774A (en) * | 2015-09-18 | 2017-03-23 | セイコーインスツル株式会社 | Electronic part |
| JP2017126645A (en) * | 2016-01-13 | 2017-07-20 | セイコーインスツル株式会社 | Electronic component |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0583187B2 (en) | 1993-11-25 |
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|---|---|---|---|
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