WO2000067315A1 - Semiconductor chip package - Google Patents

Semiconductor chip package Download PDF

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Publication number
WO2000067315A1
WO2000067315A1 PCT/FR2000/001192 FR0001192W WO0067315A1 WO 2000067315 A1 WO2000067315 A1 WO 2000067315A1 FR 0001192 W FR0001192 W FR 0001192W WO 0067315 A1 WO0067315 A1 WO 0067315A1
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WO
WIPO (PCT)
Prior art keywords
chip
cover
printed circuit
face
plate
Prior art date
Application number
PCT/FR2000/001192
Other languages
French (fr)
Inventor
Jean-Luc Morand
Original Assignee
Stmicroelectronics S.A.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stmicroelectronics S.A. filed Critical Stmicroelectronics S.A.
Publication of WO2000067315A1 publication Critical patent/WO2000067315A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/37001—Core members of the connector
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    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/37147—Copper [Cu] as principal constituent
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    • H01L2224/3754—Coating
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    • H01L2224/4005—Shape
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    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
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Definitions

  • the present invention relates to protective housings for semiconductor chips which are to be mounted on a printed circuit board.
  • the invention relates as well to chip protection boxes constituting individual electronic components as to boxes intended for integrated circuit chips.
  • connection grid is used on a central area from which is attached, by welding, a face, said to be arbitrarily lower, of the semiconductor chip.
  • connection balls are affixed directly on the underside of the chip which includes contact points in this regard.
  • the latter technique goes in the direction of increased miniaturization insofar as the overall dimensions of the housing approximate that of the chip.
  • the present invention relates to a new solution which overcomes the drawbacks of known packages and which promotes the limitation of the size of the surface of an electronic component or an integrated circuit.
  • the invention aims, in particular, to propose a new solution for protecting semiconductor chips.
  • the present invention also aims to propose a solution which is particularly simple to implement.
  • the present invention also aims to propose a solution which is compatible with a need for contact recovery on both sides of a semiconductor chip.
  • the invention further aims to propose a solution compatible with the need for a heat dissipation element.
  • the present invention provides a housing for a semiconductor chip, consisting of a rigid cover suitable for being attached to a first face of the chip and comprising at least one plate for covering the chip and a base suitable for be fixed directly to a printed circuit board, the base and the plate being connected by a connecting wall.
  • the cover constitutes a heat sink for the chip.
  • the cover is, at least partially, made of an electrically conductive material for transferring at least one contact from the first face of the chip to at least one conductive track of the printed circuit.
  • the cover has, in section, a step shape, the connecting wall being inscribed in a plane approximately perpendicular ring with two planes approximately parallel to each other and in which the plate and the base are inscribed respectively.
  • the cover further comprises side walls surrounding the side edges of the chip, the height of the side walls being preferably less than the height of the connecting wall.
  • the plate comprises at least one redent directed towards the first face of the chip.
  • the cover comprises several rigid conductive sections, isolated from each other to resume several contacts on the first face of the chip.
  • the height of the connecting wall is adapted so that a second face of the chip can be attached to the printed circuit board.
  • the height of the connecting wall is adapted so that a second face of the chip can be attached to the plate of another case containing another chip and constituting a common contact between the two chips.
  • FIG. 1 partially represents, very schematically and in section, an embodiment of a housing for electronic component according to the present invention, mounted on a printed circuit board
  • Figure 2 is a schematic perspective view of a housing according to the invention, associated with a semiconductor chip
  • FIG. 3 is a sectional view of an alternative embodiment of a housing according to the present invention, - and Figure 4 partially shows, very schematically and in section, a housing according to the invention for protecting an integrated circuit, mounted on a printed circuit board.
  • the same elements have been designated by the same references in the different figures.
  • the cover 3 comprises at least one first portion 4 approximately flat and forming a plate capable of covering the upper face of the chip 2, that is to say the face opposite to that intended to be welded or glued on the wafer 1.
  • the surface of the cover plate 4 corresponds approximately to the surface of the chip 2 so as to protect it correctly.
  • the rigid cover 3 of the invention rests on the printed circuit board 1 by means of a base 5, connected to the plate 4 by means of a connecting wall 6, preferably vertical.
  • the wall 6 preferably connects an edge of the plate 4 to an edge of the base 5 so as to form a step.
  • the plate 4, the base 5 and the wall 6 have substantially rectangular shapes. However, other shapes may be provided depending on the shape of the chip 2. In particular, it will be possible to provide a plate 4 of hexagonal or other shape depending on the shape of the chip. In this case, the size of the base 5 and of the wall 6 is preferably adapted to the dimension of at least one edge of the plate 4.
  • the height of the wall 6 is a function of the thickness of the chip 2.
  • the base 5 is intended to be glued or soldered directly to the printed circuit board.
  • a first electrode (not shown) of the chip 2 is connected to a first track 7 of the printed circuit 1 by a solder layer 8 of the chip 2 on the circuit 1.
  • a second electrode (not shown) of the chip 2 is provided in the opposite face of the latter.
  • the cover 3 is at least partially made of a conductive material so as to ensure contact transfer between the upper face of the chip 2 and the printed circuit.
  • the second electrode of the chip 2 provided on the upper face is connected to the plate 4 by means of a layer of solder or conductive glue 9.
  • the base 5 of the cover 3 is welded or glued by a conductive material 8 'to a second track 10 of the printed circuit.
  • connection portion of the plate 4 in contact with the chip 2 is preferably defined by a central recess 12 in the direction of the chip 2, the periphery of the plate 4 being thus spaced from the upper face of the chip 2.
  • the rigid cover 3 of the invention constitutes this heat sink.
  • the cover is preferably made of a conductive material both electrically and thermally. It will preferably be copper or a copper-containing alloy, optionally treated or coated (for example, eta ed), or any other material having these properties, such as for example aluminum, or even l 'gold.
  • the rigid cover 3 is adapted to include several conductive sections isolated from each other allowing a resumption of the contacts of the upper face of the chip.
  • a cover 3 is then provided comprising several rigid alternating conductive and insulating strips respectively having, in profile, the shape illustrated in FIG. 2, that is to say a step shape making it possible to carry over individually each contact on the upper face of the printed circuit 1.
  • FIG. 3 illustrates an alternative embodiment of a rigid cover 3 'according to the invention.
  • This figure is a sectional view of the cover 3 'taken in isolation.
  • the cover 3 ′ has, on each side, a side wall 13, 14 in addition to the connecting wall 6.
  • the height of the additional side walls 13 and 14 is preferably such that there remains a slight gap between their free end and the surface of the printed circuit when the housing is mounted therein. So the respective ends side walls are not likely to come into contact with other tracks of the printed circuit than those for which this effect is sought and which are in contact via the base 5.
  • An advantage of the variant of the figure 3 is that it protects the chip laterally and from all sides.
  • FIG. 4 represents a cover 3, according to the present invention, for protecting an integrated circuit chip 2 ′ provided with several contacts on the lower face.
  • the contacts on the underside of the chip 2 ' are individually connected to tracks 7' of the printed circuit 1 by means of conventional conductive balls or pads, generally fusible.
  • the chip 2 ' is glued or welded (9') to the redent 12 of the plate 4 of the rigid cover 3.
  • the base 5 of the cover 3 is itself glued to the printed circuit 1 or, as shown , soldered (8 ') to a conductive track 10' in the case of a need for electrical contact transfer from the upper face of the chip 2 '.
  • an optional side wall 13 has been shown in dotted lines.
  • the dimensions of the redent 12 in the plate 4 depend on the size of the chip and, more particularly, on the contact surface of the upper face of the chip which must be welded in the case where a contact transfer electric is required.
  • the dimensions of the wall 6 and any additional side walls depend on 1 thickness of the bare chip taking into account the different thicknesses of adhesive or solder required.
  • the dimensions of the cover and in particular the interval between the connecting wall 6 and the chip will be adapted to the needs of isolation in the air to avoid the formation of arcs between the different contacts or contact resumptions. .
  • An advantage of the present invention is that it allows, very simply, the production of a protective cover for a chip of semiconductor component or integrated circuit.
  • the present invention does not require any recourse to an encapsulation process. Consequently, the invention makes it possible to considerably reduce the space requirement on the surface of a package for an integrated component or circuit.
  • the size of a chip associated with a box according to the invention is similar to that of a bare chip, the only increase in surface area required being linked to the size of the base. However, this space requirement can be minimized insofar as, as the cover rests on the chip, the base 5 does not need to form a counterweight to the plate 4.
  • Another advantage of the present invention is that it minimizes the necessary thickness taken up by the housing. In fact, it is no longer necessary to use conductive wires to transfer contacts from the upper face to the printed circuit. Consequently, the overall height is reduced. This reduction in overall height also comes from the elimination of the encapsulation resin and the connection grid.
  • the rigid cover is conductive is not a problem in almost all cases. Indeed, the isolation of an electronic product is carried out more and more often at the end of manufacture by the affixing of a varnish on the entire printed circuit, which makes it less critical, as was the case. case in the past, the absence of individual isolation of the various integrated circuits to be mounted on the printed circuit boards.
  • Another advantage of the present invention is that the mounting and protection of an integrated circuit chip or discrete component is greatly simplified. Indeed, it is now sufficient to associate the chip with a cover of suitable dimensions, and then to bring the chip thus in a housing on a printed circuit with interposition of suitable solder pads, in particular that of the base 5 of the cover.
  • covers are dimensioned to allow a superposition of several components, for example several dipoles, to be associated in series.
  • a first chip is associated with a first cover of the type described in relation to FIG. 1 and a second chip is associated with a second cover whose height or thickness (fixed by the height of its connecting wall 6) takes into account the thickness of the first housing (fixed by the height or thickness of the first cover).
  • the second housing can be attached to the first housing while ensuring that the respective bases do not overlap.
  • the present invention is susceptible of various variants and modifications which will appear to those skilled in the art.
  • the respective dimensions of the plate and of the base can be modified as a function of the applications and, in particular, as a function of the size of the chip, and of the desire to use side walls or not.
  • this step is optional and can, in particular if a postponement of contact is not necessary, be omitted.
  • other materials than those indicated above by way of example may be used to produce a housing of the invention, provided that these materials are compatible with the production of a rigid cover which is, preferably, electrically conductive and / or thermal.
  • the connecting wall 6 and the optional additional side walls are preferably vertical (in planes perpendicular to the base and to the plate which are in planes parallel to each other), inclined walls may also be provided. .

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Casings For Electric Apparatus (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention concerns a package for a semiconductor chip (2), consisting of a rigid cap (3) capable of being directly mounted on a first surface of the chip and comprising at least a plate (4) covering the chip and a base (5) designed to be fixed to a printed circuit wafer, the base and the plate being linked by a connecting wall (6).

Description

PROTECTION D'UNE PUCE SEMICONDUCTRICE PROTECTION OF A SEMICONDUCTOR CHIP
La présente invention concerne les boîtiers de protection des puces semiconductrices qui doivent être montées sur une plaquette de circuit imprimé. L'invention se rapporte aussi bien à des boîtiers de protection de puces constituant des composants électroniques individuels qu'à des boîtiers destinés à des puces de circuit intégré.The present invention relates to protective housings for semiconductor chips which are to be mounted on a printed circuit board. The invention relates as well to chip protection boxes constituting individual electronic components as to boxes intended for integrated circuit chips.
On connaît de nombreux boîtiers pour protéger des puces en matériaux semiconducteurs. Ces boîtiers ont tous pour caractéristique commune de prévoir une encapsulation au moins partielle de la puce dans une résine ou analogue, cette résine servant à maintenir des fils de contact entre des plots de la puce et des pattes de raccordement du boîtier et/ou à protéger la puce contre des chocs éventuels.Numerous packages are known for protecting chips of semiconductor materials. These boxes all have the common characteristic of providing at least partial encapsulation of the chip in a resin or the like, this resin serving to maintain contact wires between the studs of the chip and the connection tabs of the box and / or to protect the chip against possible shocks.
La miniaturisation des produits électroniques entraîne une recherche de miniaturisation des boîtiers. Par conséquent, on cherche de plus en plus à ce que la surface du boîtier dépassant de la puce (l'emprise du boîtier sur la plaquette de circuit imprimé) soit la plus réduite possible.The miniaturization of electronic products leads to a search for miniaturization of housings. Consequently, it is increasingly sought so that the surface of the housing projecting from the chip (the grip of the housing on the printed circuit board) is as small as possible.
Le plus souvent, on utilise une grille de connexion sur une zone centrale de laquelle est rapportée, par soudure, une face, dite arbitrairement inférieure, de la puce semiconductrice.Most often, a connection grid is used on a central area from which is attached, by welding, a face, said to be arbitrarily lower, of the semiconductor chip.
Puis, on encapsule l'ensemble dans de la résine avant d'indivi- dualiser les pattes de connexion vers l'extérieur du boîtier. Dans cette technique, des plots conducteurs en face supérieure de la puce sont reliés aux pattes de connexion individuelles par 1 ' intermédiaire de fils encapsulés dans la résine. Une autre technique connue consiste à utiliser des boîtiers dits à réseau de billes ou de bossages conducteurs (BGA.) . Ces boîtiers sont pourvus, en guise de pattes de connexion vers l'extérieur du boîtier, d'un réseau de billes ou bossages conducteurs destinés à être soudés sur des plots correspondants d'un circuit imprimé de réception du boîtier. Dans cette technique, on trouve des boîtiers contenant une plaquette de réception de la puce et de définition du réseau de bossages conducteurs en face inférieure. Cette plaquette est alors encapsulée avec la puce dont les plots conducteurs en face supérieure sont reliés indivi- duellement à des plots correspondants de la plaquette encapsulée soit par fils soit par via. On trouve aussi des boîtiers dans lesquels des billes de raccordement sont apposées directement en face inférieure de la puce qui comporte des prises de contact à cet égard. Cette dernière technique va dans le sens d'une minia- turisation accrue dans la mesure où l'encombrement global du boîtier se rapproche de celui de la puce. Mais, il est quand même nécessaire de prévoir un matériau d'encapsulation qui accroît l'encombrement en surface du boîtier.Then, the whole is encapsulated in resin before indivi- dual the connection lugs towards the outside of the housing. In this technique, conductive pads on the upper face of the chip are connected to the individual connection tabs by means of wires encapsulated in the resin. Another known technique consists in using so-called boxes with a network of balls or conductive bosses (BGA.). These boxes are provided, by way of connection tabs to the outside of the box, with a network of conductive balls or bosses intended to be soldered on corresponding pads of a printed circuit for receiving the box. In this technique, there are housings containing a plate for receiving the chip and defining the network of conductive bosses on the underside. This plate is then encapsulated with the chip, the conductive pads of which on the upper face are individually connected to corresponding pads of the encapsulated plate either by wires or via. There are also housings in which connection balls are affixed directly on the underside of the chip which includes contact points in this regard. The latter technique goes in the direction of increased miniaturization insofar as the overall dimensions of the housing approximate that of the chip. However, it is still necessary to provide an encapsulation material which increases the bulk on the surface of the housing.
Un problème supplémentaire se pose lorsque le composant ou le circuit sous forme de puce doit être associé à un moyen de dissipation thermique. Dans ce cas, l'élément de dissipation thermique doit être en contact le plus direct possible avec la puce et, le plus souvent, avec un élément dissipateur externe au boîtier. Il est alors nécessaire d'encapsuler également, au moins partiellement, le dissipateur ce qui nuit à la miniaturisation du circuit .An additional problem arises when the component or circuit in the form of a chip must be associated with a means of heat dissipation. In this case, the heat dissipation element must be in as direct contact as possible with the chip and, more often than not, with a dissipating element external to the housing. It is then necessary to also encapsulate, at least partially, the dissipator, which harms the miniaturization of the circuit.
Dans le cas des composants de puissance qui nécessitent généralement un élément de dissipation, on a en outre un problème de reprise de contact sur les deux faces de la puce. En effet, ce type de composants est généralement réalisé dans l'épaisseur de la tranche de silicium pour des raisons de tenue en tension. Il en découle la présence de contacts des deux côtés de la puce qu'il est alors nécessaire de reprendre dans un boîtier de protection. Ces reprises de contact conduisent généralement à une augmentation sensible de l'encombrement en surface du boîtier.In the case of power components which generally require a dissipation element, there is also a problem of resumption of contact on the two faces of the chip. Indeed, this type of component is generally made in the thickness of the silicon wafer for reasons of withstand voltage. This results in the presence of contacts on both sides of the chip which it is then necessary to take up in a protective case. These re-contacts generally lead to a significant increase in the size of the surface of the housing.
La présente invention a pour objet une nouvelle solution qui pallie les inconvénients des boîtiers connus et qui favorise la limitation de l'encombrement en surface d'un composant électronique ou d'un circuit intégré. L'invention vise, en particulier, à proposer une nouvelle solution pour protéger des puces semiconductrices .The present invention relates to a new solution which overcomes the drawbacks of known packages and which promotes the limitation of the size of the surface of an electronic component or an integrated circuit. The invention aims, in particular, to propose a new solution for protecting semiconductor chips.
La présente invention vise également à proposer une solution qui soit particulièrement simple à mettre en oeuvre.The present invention also aims to propose a solution which is particularly simple to implement.
La présente invention vise également à proposer une solution qui soit compatible avec un besoin de reprise de contact sur les deux faces d'une puce semiconductrice.The present invention also aims to propose a solution which is compatible with a need for contact recovery on both sides of a semiconductor chip.
L'invention vise en outre à proposer une solution compatible avec le besoin d'un élément de dissipation thermique.The invention further aims to propose a solution compatible with the need for a heat dissipation element.
Pour atteindre ces objets, la présente invention pré- voit un boîtier pour puce semiconductrice, constitué d'un capot rigide propre à être rapporté sur une première face de la puce et comprenant au moins une platine de recouvrement de la puce et une embase propre à être fixée directement à une plaquette de circuit imprimé, l'embase et la platine étant reliées par une paroi de liaison.To achieve these objects, the present invention provides a housing for a semiconductor chip, consisting of a rigid cover suitable for being attached to a first face of the chip and comprising at least one plate for covering the chip and a base suitable for be fixed directly to a printed circuit board, the base and the plate being connected by a connecting wall.
Selon un mode de réalisation de la présente invention, le capot constitue un dissipateur thermique pour la puce.According to an embodiment of the present invention, the cover constitutes a heat sink for the chip.
Selon un mode de réalisation de la présente invention, le capot est, au moins partiellement, en un matériau électrique- ment conducteur pour reporter au moins un contact depuis la première face de la puce jusqu'au moins une piste conductrice du circuit imprimé.According to an embodiment of the present invention, the cover is, at least partially, made of an electrically conductive material for transferring at least one contact from the first face of the chip to at least one conductive track of the printed circuit.
Selon un mode de réalisation de la présente invention, le capot présente, en section, une forme de marche, la paroi de liaison s 'inscrivant dans un plan approximativement perpendi- culaire à deux plans approximativement parallèles entre eux et dans lesquels s'inscrivent respectivement la platine et l'embase.According to one embodiment of the present invention, the cover has, in section, a step shape, the connecting wall being inscribed in a plane approximately perpendicular ring with two planes approximately parallel to each other and in which the plate and the base are inscribed respectively.
Selon un mode de réalisation de la présente invention, le capot comprend en outre des parois latérales entourant les bords latéraux de la puce, la hauteur des parois latérales étant, de préférence, inférieure à la hauteur de la paroi de liaison.According to an embodiment of the present invention, the cover further comprises side walls surrounding the side edges of the chip, the height of the side walls being preferably less than the height of the connecting wall.
Selon un mode de réalisation de la présente invention, la platine comprend au moins un redent dirigé vers la première face de la puce. Selon un mode de réalisation de la présente invention, le capot comprend plusieurs tronçons rigides conducteurs, isolés les uns des autres pour reprendre plusieurs contacts en première face de la puce.According to an embodiment of the present invention, the plate comprises at least one redent directed towards the first face of the chip. According to one embodiment of the present invention, the cover comprises several rigid conductive sections, isolated from each other to resume several contacts on the first face of the chip.
Selon un mode de réalisation de la présente invention, la hauteur de la paroi de liaison est adaptée pour qu'une deuxième face de la puce puisse être rapportée sur la plaquette de circuit imprimé.According to an embodiment of the present invention, the height of the connecting wall is adapted so that a second face of the chip can be attached to the printed circuit board.
Selon un mode de réalisation de la présente invention, la hauteur de la paroi de liaison est adaptée pour qu'une deuxième face de la puce puisse être rapportée sur la platine d'un autre boîtier contenant une autre puce et constituant un contact commun entre les deux puces.According to one embodiment of the present invention, the height of the connecting wall is adapted so that a second face of the chip can be attached to the plate of another case containing another chip and constituting a common contact between the two chips.
Ces objets, caractéristiques et avantages, ainsi que d'autres de la présente invention seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi lesquelles : la figure 1 représente partiellement, de façon très schématique et en coupe, un mode de réalisation d'un boîtier pour composant électronique selon la présente invention, monté sur une plaquette de circuit imprimé ; la figure 2 est une vue en perspective schématique d'un boîtier selon l'invention, associé à une puce semiconductrice ; la figure 3 est une vue en coupe d'une variante de réa- lisation d'un boîtier selon la présente invention ,- et la figure 4 représente partiellement, de façon très schématique et en coupe, un boîtier selon l'invention de protection d'un circuit intégré, monté sur une plaquette de circuit imprimé . Les mêmes éléments ont été désignés par des mêmes références aux différentes figures. Pour des raisons de clarté, seuls les éléments qui sont nécessaires à la compréhension de 1 ' invention ont été représentés aux figures et seront décrits par la suite. En particulier, les détails constitutifs des puces n'ont pas été représentés et ne font pas l'objet de la présente invention. On notera simplement que l'invention peut s'appliquer à des puces pourvues de contacts sur les deux faces.These objects, characteristics and advantages, as well as others of the present invention will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: FIG. 1 partially represents, very schematically and in section, an embodiment of a housing for electronic component according to the present invention, mounted on a printed circuit board; Figure 2 is a schematic perspective view of a housing according to the invention, associated with a semiconductor chip; FIG. 3 is a sectional view of an alternative embodiment of a housing according to the present invention, - and Figure 4 partially shows, very schematically and in section, a housing according to the invention for protecting an integrated circuit, mounted on a printed circuit board. The same elements have been designated by the same references in the different figures. For reasons of clarity, only the elements which are necessary for understanding the invention have been shown in the figures and will be described later. In particular, the details constituting the chips have not been shown and are not the subject of the present invention. It will simply be noted that the invention can be applied to chips provided with contacts on both sides.
Une caractéristique de la présente invention est de prévoir un boîtier constitué d'un capot rigide comprenant au moins une partie sensiblement plane destinée à recouvrir la puce et une partie de liaison de la platine à une plaquette de circuit imprimé. Cette deuxième partie forme une marche permettant de relier la première partie sensiblement plane à la plaquette de circuit imprimé par 1 ' intermédiaire d'une embase . La figure 1 représente, par une vue en coupe d'une plaquette 1 de circuit imprimé sur laquelle est montée une puce 2 d'un composant électronique, un mode de réalisation d'un capot 3 selon la présente invention. Le capot 3 sera également décrit en relation avec la figure 2 qui représente une vue agrandie en perspective dans laquelle seule la puce 2 et le capot 3 ont été représentés .A feature of the present invention is to provide a housing consisting of a rigid cover comprising at least one substantially flat part intended to cover the chip and a part for connecting the plate to a printed circuit board. This second part forms a step making it possible to connect the first substantially planar part to the printed circuit board by means of a base. Figure 1 shows, in a sectional view of a printed circuit board 1 on which is mounted a chip 2 of an electronic component, an embodiment of a cover 3 according to the present invention. The cover 3 will also be described in relation to FIG. 2 which represents an enlarged perspective view in which only the chip 2 and the cover 3 have been represented.
Selon l'invention, le capot 3 comprend au moins une première partie 4 approximativement plane et formant une platine propre à recouvrir la face supérieure de la puce 2, c'est-à-dire la face opposée à celle destinée à être soudée ou collée sur la plaquette 1. De préférence, la surface de la platine de recouvrement 4 correspond approximativement à la surface de la puce 2 de façon à la protéger correctement. Le capot rigide 3 de l'invention repose sur la plaquette de circuit imprimé 1 par l'inter- médiaire d'une embase 5, reliée à la platine 4 au moyen d'une paroi de liaison 6, de préférence verticale. La paroi 6 relie, de préférence, un bord de la platine 4 à un bord de l'embase 5 de façon à former une marche. Dans le mode de réalisation préféré de la figure 2, la platine 4, l'embase 5 et la paroi 6 ont des for- mes sensiblement rectangulaires. Toutefois, d'autres formes pourront être prévues en fonction de la forme de la puce 2. En particulier, on pourra prévoir une platine 4 de forme hexagonale ou autre selon la forme de la puce. Dans ce cas, la taille de l'embase 5 et de la paroi 6 est, de préférence, adaptée à la dimen- sion d'au moins un bord de la platine 4.According to the invention, the cover 3 comprises at least one first portion 4 approximately flat and forming a plate capable of covering the upper face of the chip 2, that is to say the face opposite to that intended to be welded or glued on the wafer 1. Preferably, the surface of the cover plate 4 corresponds approximately to the surface of the chip 2 so as to protect it correctly. The rigid cover 3 of the invention rests on the printed circuit board 1 by means of a base 5, connected to the plate 4 by means of a connecting wall 6, preferably vertical. The wall 6 preferably connects an edge of the plate 4 to an edge of the base 5 so as to form a step. In the preferred embodiment of FIG. 2, the plate 4, the base 5 and the wall 6 have substantially rectangular shapes. However, other shapes may be provided depending on the shape of the chip 2. In particular, it will be possible to provide a plate 4 of hexagonal or other shape depending on the shape of the chip. In this case, the size of the base 5 and of the wall 6 is preferably adapted to the dimension of at least one edge of the plate 4.
La hauteur de la paroi 6 est fonction de l'épaisseur de la puce 2. En effet, selon la présente invention, l'embase 5 est destinée à être collée ou soudée directement à la plaquette de circuit imprimé. Dans l'exemple de la figure 1 qui se réfère à un composant électronique de puissance, une première électrode (non représentée) de la puce 2 est reliée à une première piste 7 du circuit imprimé 1 par une couche de soudure 8 de la puce 2 sur le circuit 1. Une deuxième électrode (non représentée) de la puce 2 est prévue dans la face opposée de cette dernière. Dans ce cas et selon une caractéristique préférée de la présente invention, le capot 3 est au moins partiellement en un matériau conducteur de façon à assurer un report de contact entre la face supérieure de la puce 2 et le circuit imprimé. Ainsi, dans le mode de réalisation illustré par la figure 1, la deuxième électrode de la puce 2 prévue en face supérieure est reliée à la platine 4 par l'intermédiaire d'une couche de soudure ou de colle conductrice 9. L'embase 5 du capot 3 est soudée ou collée par un matériau conducteur 8 ' à une deuxième piste 10 du circuit imprimé. Comme l'illustrent les figures 1 etThe height of the wall 6 is a function of the thickness of the chip 2. In fact, according to the present invention, the base 5 is intended to be glued or soldered directly to the printed circuit board. In the example of FIG. 1 which refers to a power electronic component, a first electrode (not shown) of the chip 2 is connected to a first track 7 of the printed circuit 1 by a solder layer 8 of the chip 2 on the circuit 1. A second electrode (not shown) of the chip 2 is provided in the opposite face of the latter. In this case and according to a preferred characteristic of the present invention, the cover 3 is at least partially made of a conductive material so as to ensure contact transfer between the upper face of the chip 2 and the printed circuit. Thus, in the embodiment illustrated in FIG. 1, the second electrode of the chip 2 provided on the upper face is connected to the plate 4 by means of a layer of solder or conductive glue 9. The base 5 of the cover 3 is welded or glued by a conductive material 8 'to a second track 10 of the printed circuit. As illustrated in Figures 1 and
2, la portion de raccordement de la platine 4 au contact de la puce 2 est, de préférence, définie par un redent central 12 en direction de la puce 2, la périphérie de la platine 4 étant ainsi écartée de la face supérieure de la puce 2. Selon un mode de réalisation préféré de 1 ' invention, plus particulièrement destiné aux composants de puissance ou à des circuits ayant besoin d'être associés à un dissipateur thermique, le capot rigide 3 de l'invention constitue ce dissipateur thermique. Dans ce cas, le capot est, de préférence, en un matériau conducteur à la fois électriquement et thermiquement . Il s'agira, de préférence, de cuivre ou d'un alliage contenant du cuivre, éventuellement traité ou revêtu (par exemple, éta é) , ou de tout autre matériau ayant ces propriétés, comme par exemple, l'aluminium, voire l'or.2, the connection portion of the plate 4 in contact with the chip 2 is preferably defined by a central recess 12 in the direction of the chip 2, the periphery of the plate 4 being thus spaced from the upper face of the chip 2. According to a preferred embodiment of the invention, more particularly intended for power components or circuits needing to be associated with a heat sink, the rigid cover 3 of the invention constitutes this heat sink. In this case, the cover is preferably made of a conductive material both electrically and thermally. It will preferably be copper or a copper-containing alloy, optionally treated or coated (for example, eta ed), or any other material having these properties, such as for example aluminum, or even l 'gold.
Un avantage d'un tel mode de réalisation est que les trois fonctions de reprise de contact sur la face de la puce opposée au circuit imprimé, de dissipateur thermique et de protection mécanique sont remplies par un même élément. Selon un autre mode de réalisation (non représenté) , dans lequel la puce 2 comporte plusieurs contacts en face supérieure qui doivent être ramenés individuellement sur le circuit imprimé 1, le capot rigide 3 est adapté pour comprendre plusieurs tronçons conducteurs isolés les uns des autres permettant une reprise des contacts de la face supérieure de la puce. Selon un mode préféré de réalisation, on prévoit alors un capot 3 comprenant plusieurs bandes rigides alternées respectivement conductrices et isolantes ayant, en profil, la forme illustrée par la figure 2, c'est-à-dire une forme de marche permettant de reporter individuellement chaque contact sur la face supérieure du circuit imprimé 1.An advantage of such an embodiment is that the three functions of contact resumption on the face of the chip opposite to the printed circuit, of heat sink and of mechanical protection are fulfilled by the same element. According to another embodiment (not shown), in which the chip 2 comprises several contacts on the upper face which must be brought back individually to the printed circuit 1, the rigid cover 3 is adapted to include several conductive sections isolated from each other allowing a resumption of the contacts of the upper face of the chip. According to a preferred embodiment, a cover 3 is then provided comprising several rigid alternating conductive and insulating strips respectively having, in profile, the shape illustrated in FIG. 2, that is to say a step shape making it possible to carry over individually each contact on the upper face of the printed circuit 1.
La figure 3 illustre une variante de réalisation d'un capot rigide 3' selon l'invention. Cette figure est une vue en coupe du capot 3 ' pris isolément . Selon cette variante, le capot 3' comporte, de chaque côté, une paroi latérale 13, 14 en plus de la paroi de liaison 6. Selon cette variante, la hauteur des parois latérales 13 et 14 supplémentaires est, de préférence, telle qu'il subsiste un léger écart entre leur extrémité libre et la surface du circuit imprimé lorsque le boîtier y est monté. Ainsi, les extrémités respectives des parois latérales ne risquent pas d'entrer en contact avec d'autres pistes du circuit imprimé que celles pour lesquelles cet effet est recherché et qui sont en contact par l'intermédiaire de l'embase 5. Un avantage de la variante de la figure 3 est qu'elle protège la puce latéralement et de tous les côtés.FIG. 3 illustrates an alternative embodiment of a rigid cover 3 'according to the invention. This figure is a sectional view of the cover 3 'taken in isolation. According to this variant, the cover 3 ′ has, on each side, a side wall 13, 14 in addition to the connecting wall 6. According to this variant, the height of the additional side walls 13 and 14 is preferably such that there remains a slight gap between their free end and the surface of the printed circuit when the housing is mounted therein. So the respective ends side walls are not likely to come into contact with other tracks of the printed circuit than those for which this effect is sought and which are in contact via the base 5. An advantage of the variant of the figure 3 is that it protects the chip laterally and from all sides.
Bien que l'invention ait été décrite ci-dessus en relation avec une puce comprenant un contact en face inférieure et un ou plusieurs contacts en face supérieure, on notera que l'inven- tion s'applique également au cas où la puce 2 comporte plusieurs contacts en face inférieure. Dans ce cas, la puce est collée ou soudée sur la plaquette de circuit imprimé dont les pistes conductrices 7 sont apposées selon un motif permettant de relier les contacts de la puce 2 en face inférieure. La figure 4 représente un capot 3, selon la présente invention, de protection d'une puce 2' de circuit intégré pourvue de plusieurs contacts en face inférieure. Selon le mode de réalisation de la figure 4, les contacts en face inférieure de la puce 2 ' sont reliés individuellement à des pistes 7 ' du circuit imprimé 1 au moyen de billes ou plots conducteurs classiques, généralement fusibles. En face supérieure, la puce 2' est collée ou soudée (9 ' ) au redent 12 de la platine 4 du capot rigide 3. L'embase 5 du capot 3 est elle-même collée au circuit imprimé 1 ou, comme cela est représenté, soudée (8') à une piste conduc- trice 10' dans le cas d'un besoin de report de contact électrique de la face supérieure de la puce 2' . En figure 4, une paroi latérale 13 optionnelle a été représentée en pointillés.Although the invention has been described above in relation to a chip comprising a contact on the lower face and one or more contacts on the upper face, it will be noted that the invention also applies to the case where the chip 2 comprises several contacts on the underside. In this case, the chip is glued or soldered to the printed circuit board, the conductive tracks 7 of which are affixed in a pattern enabling the contacts of the chip 2 to be connected on the underside. FIG. 4 represents a cover 3, according to the present invention, for protecting an integrated circuit chip 2 ′ provided with several contacts on the lower face. According to the embodiment of Figure 4, the contacts on the underside of the chip 2 'are individually connected to tracks 7' of the printed circuit 1 by means of conventional conductive balls or pads, generally fusible. On the upper face, the chip 2 'is glued or welded (9') to the redent 12 of the plate 4 of the rigid cover 3. The base 5 of the cover 3 is itself glued to the printed circuit 1 or, as shown , soldered (8 ') to a conductive track 10' in the case of a need for electrical contact transfer from the upper face of the chip 2 '. In Figure 4, an optional side wall 13 has been shown in dotted lines.
On notera que les dimensions du redent 12 dans la platine 4 dépendent de la taille de la puce et, plus particulière- ment, de la surface du contact de la face supérieure de la puce qui doit être soudée dans le cas où un report de contact électrique est nécessaire.It will be noted that the dimensions of the redent 12 in the plate 4 depend on the size of the chip and, more particularly, on the contact surface of the upper face of the chip which must be welded in the case where a contact transfer electric is required.
On notera également que les dimensions de la paroi 6 et des parois latérales supplémentaires éventuelles dépendent de 1 ' épaisseur de la puce nue en tenant compte des différentes épaisseurs nécessaires de colle ou de soudure.It will also be noted that the dimensions of the wall 6 and any additional side walls depend on 1 thickness of the bare chip taking into account the different thicknesses of adhesive or solder required.
On notera en outre que les dimensions du capot et en particulier l'intervalle entre la paroi de liaison 6 et la puce seront adaptés aux besoins d'isolement dans l'air pour éviter la formation d'arcs entre les différents contacts ou reprises de contact .It will also be noted that the dimensions of the cover and in particular the interval between the connecting wall 6 and the chip will be adapted to the needs of isolation in the air to avoid the formation of arcs between the different contacts or contact resumptions. .
Un avantage de la présente invention est qu'elle permet, de façon très simple, la réalisation d'un capot de protec- tion d'une puce de composant semiconducteur ou de circuit intégré. En particulier, la présente invention ne nécessite aucun recours à un procédé d'encapsulâtion. Par conséquent, l'invention permet de réduire considérablement l'encombrement en surface d'un boîtier pour composant ou circuit intégré. L'encombrement d'une puce associée à un boîtier selon l'invention se rapproche de celui d'une puce nue, la seule augmentation de surface nécessaire étant liée à l'encombrement de l'embase. Or, cet encombrement peut être minimisé dans la mesure où, comme le capot repose sur la puce, l'embase 5 n'a pas besoin de former un contrepoids à la platine 4.An advantage of the present invention is that it allows, very simply, the production of a protective cover for a chip of semiconductor component or integrated circuit. In particular, the present invention does not require any recourse to an encapsulation process. Consequently, the invention makes it possible to considerably reduce the space requirement on the surface of a package for an integrated component or circuit. The size of a chip associated with a box according to the invention is similar to that of a bare chip, the only increase in surface area required being linked to the size of the base. However, this space requirement can be minimized insofar as, as the cover rests on the chip, the base 5 does not need to form a counterweight to the plate 4.
Un autre avantage de la présente invention est qu'elle minimise l'épaisseur nécessaire prise par le boîtier. En effet, il n'est désormais plus nécessaire d'utiliser de fils conducteurs pour reporter des contacts de la face supérieure vers le circuit imprimé. Par conséquent, l'encombrement en hauteur est réduit. Cette réduction d'encombrement en hauteur provient également de la suppression de la résine d'encapsulâtion et de la grille de connexion.Another advantage of the present invention is that it minimizes the necessary thickness taken up by the housing. In fact, it is no longer necessary to use conductive wires to transfer contacts from the upper face to the printed circuit. Consequently, the overall height is reduced. This reduction in overall height also comes from the elimination of the encapsulation resin and the connection grid.
Le fait que le capot rigide soit conducteur n'est pas gênant dans la quasi-totalité des cas. En effet, l'isolement d'un produit électronique s'effectue de plus en plus souvent en fin de fabrication par l'apposition d'un vernis sur l'ensemble du circuit imprimé, ce qui rend moins critique, comme c'était le cas par le passé, l'absence d'isolement individuel des différents circuits intégrés à monter sur les plaquettes de circuit imprimé. Un autre avantage de la présente invention est que le montage et la protection d'une puce de circuit intégré ou de composant discret est grandement simplifié. En effet, il suffit désormais d'associer la puce à un capot de dimensions adaptées, puis de ramener la puce ainsi en boîtier sur un circuit imprimé avec interposition des plots de soudure adaptés, notamment celui de l' embase 5 du capot. A titre de variante, on pourra commencer par ramener la puce nue sur le circuit imprimé avec interposition des plots de soudure adaptés, puis, souder un capot de dimensions adaptées sur la face supérieure de la puce et, par l'embase 5, sur la plaquette de circuit imprimé. Bien entendu, on veillera à ce que les températures de soudure, de brasure, et/ou de collage soient adaptées au mode d'assemblage choisi pour éviter qu'un cycle thermique endommage une liaison effectuée antérieurement. Un autre avantage de l'invention est que la simplicité structurelle du boîtier le rend particulièrement adaptable à différentes tailles de puce. En particulier, le processus de montage et de protection d'une puce semiconductrice n'est aucunement modifié en cas de changement des dimensions de la puce. Il suffit de prévoir un capot de taille différente, et ce dernier est appliqué de la même façon.The fact that the rigid cover is conductive is not a problem in almost all cases. Indeed, the isolation of an electronic product is carried out more and more often at the end of manufacture by the affixing of a varnish on the entire printed circuit, which makes it less critical, as was the case. case in the past, the absence of individual isolation of the various integrated circuits to be mounted on the printed circuit boards. Another advantage of the present invention is that the mounting and protection of an integrated circuit chip or discrete component is greatly simplified. Indeed, it is now sufficient to associate the chip with a cover of suitable dimensions, and then to bring the chip thus in a housing on a printed circuit with interposition of suitable solder pads, in particular that of the base 5 of the cover. Alternatively, we can start by bringing the bare chip on the printed circuit with the interposition of suitable solder pads, then weld a cover of suitable dimensions on the upper face of the chip and, by the base 5, on the printed circuit board. Of course, it will be ensured that the soldering, brazing, and / or bonding temperatures are adapted to the method of assembly chosen to prevent a thermal cycle damaging a bond made previously. Another advantage of the invention is that the structural simplicity of the housing makes it particularly adaptable to different chip sizes. In particular, the process of mounting and protecting a semiconductor chip is in no way modified in the event of a change in the dimensions of the chip. It suffices to provide a cover of different size, and the latter is applied in the same way.
Selon un autre mode de réalisation non représenté, des capots sont dimensionnés pour autoriser une superposition de plusieurs composants, par exemple plusieurs dipôles, devant être associés en série. Par exettple, une première puce est associée à un premier capot du type de celui décrit en relation avec la figure 1 et une deuxième puce est associée à un deuxième capot dont la hauteur ou épaisseur (fixée par la hauteur de sa paroi de liaison 6) tient compte de l'épaisseur du premier boîtier (fixée par la hauteur ou épaisseur du premier capot) . Ainsi, le deuxième boîtier peut être rapporté sur le premier boîtier en veillant à ce que les embases respectives ne se chevauchent pas. On dispose alors de deux reports de contact, dont un report du point milieu de l'association en série des deux composants qui correspond au premier capot sur lequel la deuxième puce est soudée. Bien entendu, la présente invention est susceptible de diverses variantes et modifications qui apparaîtront à l'homme de l'art. En particulier, les dimensionnements respectifs de la platine et de l'embase pourront être modifiés en fonction des appli- cations et, en particulier, en fonction de la taille de la puce, et du souhait de recourir à des parois latérales ou non. De plus, bien que l'invention ait été décrite ci-dessus en relation avec un capot pourvu d'un redent d'appui sur la face supérieure de la puce, on notera que ce redent est optionnel et peut, en parti- culier si un report de contact n'est pas nécessaire, être omis. En outre, d'autres matériaux que ceux indiqués ci-dessus à titre d'exemple pourront être utilisés pour réaliser un boîtier de l'invention, pourvu que ces matériaux soient compatibles avec la réalisation d'un capot rigide qui soit, de préférence, conducteur électriquement et/ou thermiquettient. Enfin, si la paroi de liaison 6 et les parois latérales supplémentaires éventuelles sont, de préférence, verticales (dans des plans perpendiculaires à l'embase et à la platine qui sont dans des plans parallèles entre eux) , on pourra également prévoir des parois inclinées . According to another embodiment not shown, covers are dimensioned to allow a superposition of several components, for example several dipoles, to be associated in series. For example, a first chip is associated with a first cover of the type described in relation to FIG. 1 and a second chip is associated with a second cover whose height or thickness (fixed by the height of its connecting wall 6) takes into account the thickness of the first housing (fixed by the height or thickness of the first cover). Thus, the second housing can be attached to the first housing while ensuring that the respective bases do not overlap. There are then two contact carryovers, including a carryover from the midpoint of the series association of the two components which corresponds to the first cover on which the second chip is soldered. Of course, the present invention is susceptible of various variants and modifications which will appear to those skilled in the art. In particular, the respective dimensions of the plate and of the base can be modified as a function of the applications and, in particular, as a function of the size of the chip, and of the desire to use side walls or not. In addition, although the invention has been described above in relation to a cover provided with a support step on the upper face of the chip, it will be noted that this step is optional and can, in particular if a postponement of contact is not necessary, be omitted. In addition, other materials than those indicated above by way of example may be used to produce a housing of the invention, provided that these materials are compatible with the production of a rigid cover which is, preferably, electrically conductive and / or thermal. Finally, if the connecting wall 6 and the optional additional side walls are preferably vertical (in planes perpendicular to the base and to the plate which are in planes parallel to each other), inclined walls may also be provided. .

Claims

REVENDICATIONS
1. Boîtier pour puce semiconductrice (2, 2') constitué d'un capot rigide (3, 3') propre à être rapporté sur une première face de la puce et comprenant au moins une platine (4) de recouvrement de la puce et une embase (5) propre à être fixée directe- ment à une plaquette de circuit imprimé, l'embase et la platine étant reliées par une paroi de liaison (6) , caractérisé en ce que le capot comprend des parois latérales (13, 14) entourant les bords latéraux de la puce et de hauteur inférieure à la hauteur de ladite paroi de liaison (6) . 1. Housing for semiconductor chip (2, 2 ') consisting of a rigid cover (3, 3') suitable for being attached to a first face of the chip and comprising at least one plate (4) covering the chip and a base (5) suitable for being fixed directly to a printed circuit board, the base and the plate being connected by a connecting wall (6), characterized in that the cover comprises side walls (13, 14 ) surrounding the lateral edges of the chip and of height less than the height of said connecting wall (6).
2. Boîtier selon la revendication 1, caractérisé en ce que le capot cαtprend plusieurs tronçons rigides conducteurs, isolés les uns des autres pour reprendre plusieurs contacts en première face de la puce.2. Housing according to claim 1, characterized in that the cover cαtprend several rigid conductive sections, isolated from each other to resume several contacts on the first face of the chip.
3. Boîtier selon la revendication 1 ou 2, caractérisé en ce que le capot (3, 3') est, au moins partiellement, en un matériau électriquement conducteur pour reporter au moins un contact depuis la première face de la puce (2, 2') jusqu'au moins une piste conductrice (10, 10') du circuit imprimé (1).3. Housing according to claim 1 or 2, characterized in that the cover (3, 3 ') is, at least partially, made of an electrically conductive material for transferring at least one contact from the first face of the chip (2, 2 ') up to at least one conductive track (10, 10') of the printed circuit (1).
4. Boîtier selon l'une quelconque des revendications 1 à 3, caractérisé en ce que la hauteur de la paroi de liaison (6) est adaptée pour qu'une deuxième face de la puce (2) puisse être rapportée sur la platine d'un autre boîtier contenant une autre puce et constituant un contact commun entre les deux puces.4. Housing according to any one of claims 1 to 3, characterized in that the height of the connecting wall (6) is adapted so that a second face of the chip (2) can be attached to the plate another box containing another chip and constituting a common contact between the two chips.
5. Boîtier selon l'une quelconque des revendications 1 à 4, caractérisé en ce que la platine (4) comprend au moins un redent (12) dirigé vers la première face de la puce (2, 2') .5. Housing according to any one of claims 1 to 4, characterized in that the plate (4) comprises at least one step (12) directed towards the first face of the chip (2, 2 ').
6. Boîtier selon l'une quelconque des revendications 1 à 5, caractérisé en ce que la hauteur de la paroi de liaison (6) est adaptée pour qu'une deuxième face de la puce (2, 2') puisse être rapportée sur la plaquette (1) de circuit imprimé.6. Housing according to any one of claims 1 to 5, characterized in that the height of the connecting wall (6) is adapted so that a second face of the chip (2, 2 ') can be attached to the printed circuit board (1).
7. Boîtier selon l'une quelconque des revendications 1 à 6, caractérisé en ce que le capot (3, 3') constitue un dissipateur thermique pour la puce (2, 2') . 7. Housing according to any one of claims 1 to 6, characterized in that the cover (3, 3 ') constitutes a heat sink for the chip (2, 2').
PCT/FR2000/001192 1999-05-03 2000-05-03 Semiconductor chip package WO2000067315A1 (en)

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FR9905730A FR2793350B1 (en) 1999-05-03 1999-05-03 PROTECTION OF A SEMICONDUCTOR CHIP
FR99/05730 1999-05-03

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