JP2748776B2 - LSI package - Google Patents

LSI package

Info

Publication number
JP2748776B2
JP2748776B2 JP4156620A JP15662092A JP2748776B2 JP 2748776 B2 JP2748776 B2 JP 2748776B2 JP 4156620 A JP4156620 A JP 4156620A JP 15662092 A JP15662092 A JP 15662092A JP 2748776 B2 JP2748776 B2 JP 2748776B2
Authority
JP
Japan
Prior art keywords
chip
lsi
external connection
shaped external
connection terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP4156620A
Other languages
Japanese (ja)
Other versions
JPH065655A (en
Inventor
正義 三好
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP4156620A priority Critical patent/JP2748776B2/en
Publication of JPH065655A publication Critical patent/JPH065655A/en
Application granted granted Critical
Publication of JP2748776B2 publication Critical patent/JP2748776B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明はＬＳＩチップをフェイス
ダウンで実装するＬＳＩチップ実装体に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI chip mounting body for mounting an LSI chip face down.

【０００２】[0002]

【従来の技術】図６は、ＩＥＩＣＥＴ ＴＲＡＮＳＡＣ
ＴＩＯＮＳ．（ＶＯＬ．Ｅ ７４，Ｎｏ．８， Ｐ．２
３３３ ＡＵＧＵＳＴ１９９１）に記載されている従来
のこの種のＬＳＩチップ実装体の例を示す。本例におい
ては、ＬＳＩチップ８をフェイスダウンで配線基板上に
接続し、熱伝導性の良好なキャップ１３にて気密封止さ
れている。気密封止にはシーム溶接が用いられている。
実装されているＬＳＩチップ８はその周辺に電極を形成
し、その電極に接続されたリードによって外部との接続
がなされている。2. Description of the Related Art FIG. 6 shows an IEICET TRANSAC.
TIONS. (VOL.E 74, No. 8, P.2
333 (AUGUST 1991) shows an example of this type of conventional LSI chip mounted body. In this example, the LSI chip 8 is connected face-down on the wiring board, and hermetically sealed with a cap 13 having good thermal conductivity. Seam welding is used for hermetic sealing.
The mounted LSI chip 8 has electrodes formed around it, and is connected to the outside by leads connected to the electrodes.

【０００３】図７は、第４１回ＥＣＴＣ論文集１９９１
年、（Ｐ．７０４）に掲載されている従来のこの種のＬ
ＳＩチップ実装体の他の例を示す。本例においては、Ｌ
ＳＩチップ８は回路面に形成された半田バンプにより配
線基板上に設けられた薄膜上のパッドに接続されてお
り、キャップ１３を半田付けすることにより気密封止し
ている。このようなフリップ実装による接続方法では、
ＬＳＩチップの回路面にバンプを形成し、ＬＳＩチップ
回路面全体を接続の領域とすることから、多端子化には
有利である。FIG. 7 shows the 41st ECTC Transactions 1991
Year, a conventional L of this kind described in (P.704)
5 shows another example of an SI chip mounted body. In this example, L
The SI chip 8 is connected to pads on a thin film provided on a wiring board by solder bumps formed on a circuit surface, and hermetically sealed by soldering a cap 13. In such a connection method by flip mounting,
Since bumps are formed on the circuit surface of the LSI chip and the entire circuit surface of the LSI chip is used as a connection region, it is advantageous for increasing the number of terminals.

【０００４】[0004]

【発明が解決しようとする課題】上述した従来の第１の
ＬＳＩ実装体では、ＬＳＩチップの周辺で接続をとるた
め、ＬＳＩチップ内からその周辺までの引き出しの線長
が長く端子が細分化するので、信号の遅れや電源供給に
おける電圧降下が生じてしまう。また、第２のＬＳＩ実
装体では、ＬＳＩチップの回路面全体にバンプを形成し
基板に接続するため、チップキャリア基板との熱膨張率
の差によるストレスが生じ、接合部の信頼性に問題が生
じるなどの欠点がある。In the above-mentioned first conventional LSI mounted body, since the connection is made around the LSI chip, the line length of the lead from inside the LSI chip to the periphery is long and the terminals are subdivided. Therefore, a signal delay or a voltage drop in power supply occurs. Also, in the second LSI mounted body, since a bump is formed on the entire circuit surface of the LSI chip and connected to the substrate, stress is generated due to a difference in coefficient of thermal expansion with the chip carrier substrate, and there is a problem in the reliability of the joint. There are disadvantages such as occurrence.

【０００５】[0005]

【０００６】本発明のＬＳＩチップ実装体は、表面にＬ
ＳＩ接続用パッドを有し、裏面に微細なピン状外部接続
端子を有するチップキャリア基板上に、回路面全体に微
細なピン状外部接続端子を有するＬＳＩチップをフェイ
スダウンで実装した実装体を、入出力ピンを有する多層
配線基板上に更に実装したことを特徴とする。The LSI chip mounted body of the present invention has
On a chip carrier substrate having SI connection pads and having fine pin-shaped external connection terminals on the back surface, a mounting body in which an LSI chip having fine pin-shaped external connection terminals is mounted face down on the entire circuit surface, The semiconductor device is further mounted on a multilayer wiring board having input / output pins.

【０００７】[0007]

【実施例】次に本発明の実施例について図面を参照して
説明する。Next, an embodiment of the present invention will be described with reference to the drawings.

【０００８】図１は本発明が適用されるＬＳＩ実装体の
断面を示し、図２はその詳細を示す。FIG. 1 shows a cross section of an LSI package to which the present invention is applied, and FIG. 2 shows details thereof.

【０００９】チップキャリア基板１は、内部にタングス
テン（Ｗ）、銀パラジウム（Ａg −Ｐd ）などの導体配
線２を有している。チップキャリア基板１の表面は、Ｌ
ＳＩチップ８に電気的に接続されるＬＳＩ接続用パッド
３を具備していて、回路面全体に微細なピン状外部接続
端子９を有するＬＳＩチップ８が半田４（例えば９６．
５Ｓn −３．５Ａg 半田、融点２２１°Ｃ）によって半
田付けされている。[0009] chip carrier substrate 1 has a tungsten (W), silver-palladium (A g -P d) conductive wiring 2, such as the interior. The surface of the chip carrier substrate 1 is L
The LSI chip 8 having the LSI connection pads 3 electrically connected to the SI chip 8 and having fine pin-shaped external connection terminals 9 on the entire circuit surface is connected to the solder 4 (for example, 96.
5S n -3.5A g solder is soldered by melting 221 ° C).

【００１０】チップキャリア基板１の裏面には、微細な
ピン状外部接続端子５を具備している。この微細なピン
状外部接続端子５は、チップキャリア基板裏面に設けら
れた電極部６（例えばチタンタングステン（Ｔi −Ｗ）
と白金（Ｐt ）等の薄膜）に、半田７（半田４よりも融
点が高い半田、例えば８０Ａu ／２０Ｓn 半田、融点２
８０度Ｃ）により半田付されている。On the back surface of the chip carrier substrate 1, there are provided fine pin-shaped external connection terminals 5. The fine pin-shaped external connection terminal 5, the electrode portion 6 provided on the chip carrier substrate back surface (for example, titanium tungsten (T i -W)
And platinum (P t) thin film and the like), the solder melting point higher than the solder 7 (solder 4, for example 80A u / 20S n solder, melting point 2
80 ° C).

【００１１】ＬＳＩチップ８の回路面は、シリコン酸化
膜（Ｓi Ｏ2 ）やポリイミド（ＰＩ）などのパッシベー
ション膜１０によりパッシベーションされ、電極部以外
は絶縁されている。チップキャリア裏面と同様に、ＬＳ
Ｉチップ８の回路面の電極部１１（例えば、チタンタン
グステン（Ｔi −Ｗ）と金（Ａu ）などの薄膜で形成さ
れている）には微細なピン状外部接続端子９が半田１２
（半田４より融点が高い半田で、半田７の融点との関係
は問わないので、例えば、半田７の例と同じ８０Ａu ／
２０Ｓn 半田、融点２８０°Ｃ）により半田付けされて
いる。[0011] circuit surface of the LSI chip 8 is passivated by a silicon oxide film (S i O 2) and a passivation film 10 such as polyimide (PI), other than the electrode portions are insulated. As with the back of the chip carrier, LS
Circuit surface of the electrode portion 11 of the I chip 8 (e.g., titanium-tungsten (T i -W) gold (A u) are formed by a thin film such as) a fine pin into shaped outside connection terminal 9 is solder 12
(Since the melting point of solder 7 is higher than that of solder 4 and its relationship with the melting point of solder 7 does not matter, for example, 80 A u /
20S n solder is soldered by melting 280 ° C).

【００１２】チップキャリア基板１のピン状外部接続端
子５及びＬＳＩチップ８のピン状外部接続端子９の材質
としては、銅合金、コバール（鉄ニッケルコバルト合
金）等が考えられ、これの表面に金（Ａu ）メッキを施
したもの等が用いれられる。大きさは、例えば、長さｌ
が１．０ｍｍ程度、ピン計ａはφ０．１ｍｍ程度のもの
が使用されている。ここで用いられるチップキャリア基
板１のピン状外部接続端子５及びＬＳＩチップ８のピン
状外部接続端子９の２つは、材質、寸法、形状等は同じ
である必要はない。As the material of the pin-shaped external connection terminals 5 of the chip carrier substrate 1 and the pin-shaped external connection terminals 9 of the LSI chip 8, copper alloy, Kovar (iron-nickel-cobalt alloy) or the like can be considered. (A u ) Plated or the like is used. The size is, for example, length l
Is about 1.0 mm, and the pin gauge a is about 0.1 mm. The pin-shaped external connection terminals 5 of the chip carrier substrate 1 and the pin-shaped external connection terminals 9 of the LSI chip 8 used here need not be the same in material, size, shape and the like.

【００１３】このＬＳＩ実行構造では、ＬＳＩチップ８
の回路面全体に微細なピン状外部接続端子９を形成する
ことにより、多端子化及び高速化に有利となる。また、
ＬＳＩチップ８のピン状外部接続端子９を介してチップ
キャリア基板１と接続することにより、ＬＳＩチップ８
（例えばＳi で熱膨張係数３ｐｐｍ／°Ｃ）とチップキ
ャリア基板１（例えばＡｌ2 Ｏ3 で熱膨張係数６．７ｐ
ｐｍ／°Ｃ）の熱膨張率の差により生じるストレスを前
記ピン状外部接続端子９によって吸収することにより、
接続部の信頼性の問題を解決している。In this LSI execution structure, the LSI chip 8
By forming the fine pin-shaped external connection terminals 9 over the entire circuit surface, it is advantageous to increase the number of terminals and increase the speed. Also,
By connecting to the chip carrier substrate 1 via the pin-shaped external connection terminals 9 of the LSI chip 8, the LSI chip 8
(E.g. thermal expansion coefficient 3ppm at S i / ° C) and thermal expansion coefficient 6.7p chip carrier substrate 1 (for example, Al 2 O 3,
pm / ° C.) by absorbing the stress caused by the difference in the coefficient of thermal expansion by the pin-shaped external connection terminal 9,
Solves the problem of connection reliability.

【００１４】図３は本発明が適用されるＬＳＩ実装体の
うちキャップに係る部分の断面を示す。FIG. 3 shows a cross section of a portion related to a cap in an LSI mounted body to which the present invention is applied.

【００１５】図３においても、図１におけるのと同様
に、微細なピン状外部接続端子５を裏面に有したチップ
キャリア基板１の表面に、微細なピン状外部接続端子９
を有したＬＳＩチップ８がフェイスダウンで接続され、
更にＬＳＩチップ８は熱伝導性が良好で熱膨張係数がＬ
ＳＩチップ８に近い材料、例えばＬＳＩチップ８をシリ
コン（Ｓi ）とすると銅タングステン（Ｃu ／Ｗ）ある
いは窒化アルミ（ＡｌＮ）等で製作されたキャップ１３
で気密封止されている。In FIG. 3, similarly to FIG. 1, fine pin-shaped external connection terminals 9 are provided on the surface of chip carrier substrate 1 having fine pin-shaped external connection terminals 5 on the back surface.
LSI chip 8 having a face-down connection
Further, the LSI chip 8 has good thermal conductivity and a thermal expansion coefficient of L.
If the material close to the SI chip 8, for example, the LSI chip 8 is silicon (Si), a cap 13 made of copper tungsten (Cu / W) or aluminum nitride (AlN) or the like.
And hermetically sealed.

【００１６】チップキャリア基板１とキャップ１３の気
密封止は、シーム溶接、レーザー溶接、あるいは半田
（例えば６３Ｓn ／３７Ｐb 半田、融点１８３°Ｃ）等
により気密封止される。また、ＬＳＩチップ８の裏面と
キャップ１３の内側は、熱伝導性の良好な接着剤１４
（例えば気密封止時に使用された６３Ｓn ／３７Ｐb 半
田、融点１８３°Ｃ）で直接ダイボンディングされてい
る。つまり、気密封止とダイボンディングが同時におこ
なうことも可能である。The hermetic sealing of the chip carrier substrate 1 and the cap 13, seam welding, laser welding, or soldering (e.g. 63S n / 37P b solder, melting point 183 ° C) it is hermetically sealed by such. Further, the back surface of the LSI chip 8 and the inside of the cap 13 are bonded to an adhesive 14 having good heat conductivity.
(E.g. hermetic seal 63S n / 37P b solder used during, mp 183 ° C) is directly die-bonded in. That is, hermetic sealing and die bonding can be performed simultaneously.

【００１７】このように、微細なピン状外部接続端子９
を有するＬＳＩチップ８全体がキャップ１３にて気密封
止され、更にＬＳＩチップ８の裏面に熱伝導性の良好な
キャップ１３が接合されることにより、熱膨張率の差に
よる接続信頼性の低下をさせることなく、多端子化・高
速化に有利、且つ放熱効率を向上させたＬＳＩ実装構造
を提供できる。As described above, the fine pin-shaped external connection terminals 9
The entire LSI chip 8 having the above is hermetically sealed by the cap 13 and the cap 13 having good thermal conductivity is bonded to the back surface of the LSI chip 8 to reduce the connection reliability due to the difference in the coefficient of thermal expansion. It is possible to provide an LSI mounting structure that is advantageous for increasing the number of terminals and increasing the speed and improving the heat radiation efficiency without causing the problem.

【００１８】次に、本発明の第１の実施例について図４
を用いて説明する。表面のチップキャリア接続用パッド
１６と裏面の入出力用ピン１８が内部導体配線１９で電
気的に接続されている多層配線基板１５上に、第１の実
施例および第２の実施例と同様な微細なピン状外部接続
端子９を有するＬＳＩチップ８を実装した多数のチップ
キャリア基板１が微細なピン状外部接続端子５を介して
半田１７（半田４、半田７及び半田１２より融点が低い
半田、例えばインジウム〈Ｉｎ〉系あるいはビスマス
〈Ｂｉ〉系の低融点半田）により半田付けされている。Next, a first embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. The same as in the first and second embodiments, on a multilayer wiring board 15 in which chip carrier connection pads 16 on the front surface and input / output pins 18 on the back surface are electrically connected by internal conductor wiring 19. A large number of chip carrier substrates 1 on which LSI chips 8 having fine pin-shaped external connection terminals 9 are mounted are connected to the solder 17 (solder 4, solder 7, and solder 12 having a lower melting point than the solder 12) via the fine pin-shaped external connection terminals 5. For example, indium <In> -based or bismuth <Bi> -based low melting point solder) is used for soldering.

【００１９】ここで使用されている多層配線基板１５と
してはポリイミド・セラミック基板などが考えられる。
この場合、ベース基板にアルミナセラミック基板を使用
し、内部に電源とグランド配線層を形成、基板の裏面に
は入出力ピン１８が格子状に鑞付けされている。表面に
はポリイミドを絶縁層とする薄膜多層配線が形成され、
ポリイミド表面に形成されたチップキャリア接続用パッ
ド１６上にチップキャリア基板１が微細なピン状外部接
続端子５を介して接続、実装されている。As the multilayer wiring board 15 used here, a polyimide ceramic substrate or the like can be considered.
In this case, an alumina ceramic substrate is used as a base substrate, a power supply and a ground wiring layer are formed inside, and input / output pins 18 are brazed in a grid pattern on the back surface of the substrate. Thin-film multilayer wiring with polyimide as the insulating layer is formed on the surface,
The chip carrier substrate 1 is connected and mounted via fine pin-shaped external connection terminals 5 on chip carrier connection pads 16 formed on the polyimide surface.

【００２０】このチップキャリア基板１のピン状外部接
続端子５を介して多層配線基板１５と接続することによ
り、ＬＳＩチップ８とチップキャリア基板１間の場所と
同様に、チップキャリア基板１と多層配線基板１５の熱
膨張率の差により生じるストレスをピン状外部接続端子
５によって吸収することができる。このような実装構造
をとることにより、超高速で信頼性の高いマルチチップ
モジュール（マルチチップパッケージ）を提供できる。By connecting to the multilayer wiring board 15 via the pin-shaped external connection terminals 5 of the chip carrier substrate 1, the chip carrier substrate 1 and the multilayer wiring The stress caused by the difference in the coefficient of thermal expansion of the substrate 15 can be absorbed by the pin-shaped external connection terminals 5. By adopting such a mounting structure, a multichip module (multichip package) with high speed and high reliability can be provided.

【００２１】図５は、上述の第１の実施例に対して、図
３に示したように、接続材１４によりキャップ１３を取
り付けた本発明の第２の実施例の断面図を示す。FIG. 5 is a cross-sectional view of the second embodiment of the present invention in which the cap 13 is attached by the connecting member 14 as shown in FIG.

【００２２】[0022]

【発明の効果】以上説明したように、本発明は裏面に微
細なピン状外部接続端子を有するチップキャリア基板
に、微細なピン状外部接続端子を回路面全体に有するＬ
ＳＩチップを実装することにより、多端子化及び高速化
に有利で、ＬＳＩチップの大型化に対しても、熱膨張係
数の差により発生するストレスをピン状外部接続端子で
吸収し、接続信頼性の低下を防止した信頼性高いチップ
キャリアが可能となる。またＬＳＩチップを実装するチ
ップキャリア基板の材料、及び、チップキャリア基板を
実装する多層配線基板の材料の選択の幅が広がる等のメ
リットがある。As described above, according to the present invention, a chip carrier substrate having fine pin-shaped external connection terminals on the back surface is provided with an L pin having fine pin-shaped external connection terminals on the entire circuit surface.
By mounting the SI chip, it is advantageous for increasing the number of terminals and increasing the speed, and even when the size of the LSI chip is increased, the stress generated due to the difference in thermal expansion coefficient is absorbed by the pin-shaped external connection terminal, and the connection reliability is improved. And a highly reliable chip carrier in which a decrease in the temperature is prevented can be realized. Further, there is an advantage that the range of selection of the material of the chip carrier substrate on which the LSI chip is mounted and the material of the multilayer wiring substrate on which the chip carrier substrate is mounted is widened.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明が適用されるＬＳＩ実装体の断面図であ
る。FIG. 1 is a sectional view of an LSI package to which the present invention is applied.

【図２】図１に示したＬＳＩ実装体の詳細図である。FIG. 2 is a detailed view of the LSI mounted body shown in FIG.

【図３】本発明が適用されるＬＳＩ実装体のうちのキャ
ップに係る部分の断面図である。FIG. 3 is a sectional view of a portion related to a cap in an LSI mounted body to which the present invention is applied;

【図４】本発明の第１の実施例の断面図である。FIG. 4 is a cross-sectional view of the first embodiment of the present invention.

【図５】本発明の第２の実施例の断面図である。FIG. 5 is a sectional view of a second embodiment of the present invention.

【図６】従来のＬＳＩチップ実装体の一例を示す図であ
る。FIG. 6 is a diagram showing an example of a conventional LSI chip mounted body.

【図７】従来のＬＳＩチップ実装体の他の例を示す図で
ある。FIG. 7 is a diagram showing another example of a conventional LSI chip mounted body.

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 表面にＬＳＩ接続用パッドを有し、裏面
に微細なピン状外部接続端子を有するチップキャリア基
板上に、回路面全体に微細なピン状外部接続端子を有す
るＬＳＩチップをフェイスダウンで実装した実装体を、
入出力ピンを有する多層配線基板上に更に実装したこと
を特徴とするＬＳＩチップ実装体。1. An LSI chip having fine pin-shaped external connection terminals on the entire circuit surface is face-down on a chip carrier substrate having LSI connection pads on the front surface and fine pin-shaped external connection terminals on the back surface. The implementation body implemented in
An LSI chip mounted body further mounted on a multilayer wiring board having input / output pins. 【請求項２】 前記ＬＳＩチップを実装後にキャップに
て気密封止したことを特徴とする請求項１記載のＬＳＩ
チップ実装体。2. The LSI according to claim 1, wherein said LSI chip is hermetically sealed with a cap after mounting.
Chip mounting body.
JP4156620A 1992-06-16 1992-06-16 LSI package Expired - Lifetime JP2748776B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4156620A JP2748776B2 (en) 1992-06-16 1992-06-16 LSI package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4156620A JP2748776B2 (en) 1992-06-16 1992-06-16 LSI package

Publications (2)

Publication Number Publication Date
JPH065655A JPH065655A (en) 1994-01-14
JP2748776B2 true JP2748776B2 (en) 1998-05-13

Family

ID=15631698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4156620A Expired - Lifetime JP2748776B2 (en) 1992-06-16 1992-06-16 LSI package

Country Status (1)

Country Link
JP (1) JP2748776B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3314741B2 (en) * 1998-11-27 2002-08-12 日本電気株式会社 Semiconductor package assembly and method of assembling the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6151838A (en) * 1984-08-22 1986-03-14 Hitachi Ltd Semiconductor device
JPH02168640A (en) * 1987-11-04 1990-06-28 Nec Corp Connection structure between different substrates

Also Published As

Publication number Publication date
JPH065655A (en) 1994-01-14

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