JPH05326625A - Lsi mounting structure - Google Patents

Abstract

PURPOSE:To realize hermetic sealing of LSI and relaxation of thermal stress by filling the gap between the LSI and a carrier board with sealant. CONSTITUTION:Sealant 4 is filled in the gap between an LSI 8 and a carrier board 5, between all bumps A15, and at the side face of the LSI 8 thus hermetically sealing the circuit surface of the LSI 8. A silicon based resin having alpharay blocking effect is employed as the filler 4. The filler 4 relaxes thermal stress caused by repeated operation of the device, thus preventing failure of the device due to crack. A heat spreader 1 is die bonded through an adhesive 2 entirely to the rear surface of the LSI 8. Since the adhesive 2 has high thermal conductivity, heat transferred to the rear of the LSI 8 spreads sufficiently resulting in high heat dissipation effect to the outside of carrier.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI packaging structure.

[0002]

2. Description of the Related Art FIG. 3 is a sectional view showing a first conventional example. (40th ELECTRONIC COMPON
ENT & TECHNOLOGY CONFEREN
CE (see ECTC: PP. 613-619, 1990) In this technique, an LS having bumps 16 on the entire surface is used.
The structure is that I8 is soldered face down on the wiring substrate 13. The heat generated on the surface of the LSI8 is
After being transmitted to the piston 18 that is in direct contact with the back side, heat is exhausted to the outside of the cooling member. The chip power supply and signal input / output are performed by connecting the bumps 16 to the outside of the device via the wiring board 13. The height of the piston 18 can be adjusted in consideration of the inclination of the LSI 8 and the height variation among the LSIs 8.

FIG. 4 is a sectional view showing a second conventional example. (41th ECTC: PP.693-703,1
991) LSI having solder bumps B25 on the circuit surface
The chip 19 is mounted face down on the base substrate 21. The cap 22 is the solder D23 and the LSI chip 1
The back surface of 9 is bonded to the base substrate with solder C20. As a result, the LSI chip can be hermetically sealed. The heat generated in the LSI chip 19 is L
Heat is transmitted to the outside of the carrier from the cap 22 on the back surface through the SI chip 19 itself.

[0004]

DISCLOSURE OF THE INVENTION The conventional LSI described above
There are the following problems in the chip mounting structure.

In FIG. 3, since the amount of heat generated by the LSI 8 has increased, it has become difficult to exhaust sufficient heat to the outside of the device by the conventional technique. Further, since the bumps 16 are exposed, there is a problem that the reliability of the LSI is low, such as lack of moisture resistance and airtightness.

Further, in the technique of FIG. 4, soldering is very much, which is very complicated in terms of material and assembly, and the cost is high. Further, when the cap 22 is attached to the LSI chip 19, if the LSI chip 19 is tilted, the gap between the cap 22 and the LSI chip 19 is widened, and good thermal resistance cannot be obtained. Also,
When the LSI chip 19 and the cap 22 are in contact with each other, the LSI
Stable assembly could not be performed because the chip 19 was destroyed.

Further, the thermal stress due to the operation and non-operation of the device strongly acts on the solder bump B25 portion, causing a defect. Further, in order to alleviate this thermal stress, it is necessary to select a base substrate that has almost no difference in the coefficient of thermal expansion from the LSI chip 19, and there is a drawback that the material is limited.

[0008]

In order to solve the above problems, in the LSI mounting structure according to the present invention, the gap between the carrier substrate and the LSI chip is filled with a sealant, and the back surface of the LSI chip is filled. The structure is equipped with a heat spreader.

[0009]

The present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a first embodiment of the present invention. Bumps A15 are installed as external connection terminals on the circuit surface of the LSI8. By bonding the bumps A15 to the pads A9 arranged one-to-one with the bumps A15 on the carrier substrate 5 by the solder A3, the LSIs 8 and the carrier The substrate 5 is electrically connected. Wiring 6 is provided in the carrier substrate 5.
A bump B7 as a connection terminal to the outside of the carrier is provided in a portion reaching the surface on which the LSI is not mounted. Therefore, since the LSI 8 and the bump B7 provided on the back surface of the carrier substrate 5 are connected to each other, the electric signal of the device can be input / output to / from the outside of the carrier substrate 5.
For the carrier substrate 5, a material that can be co-fired with the in-carrier wiring 6 and has a low dielectric constant and a thermal expansion coefficient close to that of the LSI 8 (for example, mullite, alumina, AlN, etc.) is used.

On the other hand, the gap between the LSI 8 and the carrier substrate 5, the space between all the bumps A15, and the side surface of the LSI 8 are filled with the sealant 4, and the circuit surface of the LSI 8 is completely hermetically sealed. The heat spreader 1 is die-bonded with the bonding agent 2 on the entire back surface of the LSI 8. As a method of assembling this carrier, first, LS
I8 is soldered to the carrier substrate 5 with solder A3, then the sealant 4 is filled, and finally the heat spreader 1 is attached. At this time, the sealant 4,
It is necessary to take care so that the bonding agent 2 does not contain bubbles.

For the filler 4, for example, a silicone resin is used. If a silicone resin having an effect of protecting α rays which causes malfunction of the LSI 8 is used, reliability against α rays can also be obtained. Moreover, since the LSI 8 requires very large power consumption,
Non-operation causes a considerable temperature difference within the device.
Therefore, a large thermal stress is generated due to the difference in the coefficient of thermal expansion between the LSI 8, the bump A15, and the carrier substrate 5, and L
SI8 has a risk of causing cracks in the solder A3 and the carrier substrate 5, and cutting or short-circuiting the carrier substrate wiring 6 and the wiring in the LSI 8. However, by filling the sealant 4 with no gaps between the LSI 8 and the carrier substrate 5 and all the bumps A15, the filler 4 alleviates the thermal stress caused by the operation and non-operation of the device, so that the device may be damaged by cracks or the like. The failure does not occur, and the reliability of the device can be significantly improved. In addition, since the circuit surface of the LSI 8 is not exposed to the outside by filling the sealing agent 4, it is possible to protect the circuit surface of the LSI 8 from dew condensation, dust, external contact, and the like.

The heat generated from the circuit surface of the LSI 8 is LS
After reaching the I8 itself, it reaches the back side of the LSI8. At this time, since the heat spreader 1 is die-bonded to the back surface of the LSI 8 with the bonding agent 2 having good heat conduction, the heat reaching the back surface of the LSI 8 can be sufficiently spread, and a high heat dissipation effect to the outside of the carrier can be obtained. Will be Further, since the heat spreader 1 is attached to the LSI 8, it is possible to reduce mechanical impact on the LSI 8 when the cooling member is installed on the back surface side of the LSI 8. The heat spreader 1 has a large thermal conductivity and is close to the thermal expansion coefficient of the LSI chip (for example, SiC, AlN,
Cu / W) is used. Further, by using a material having high thermal conductivity for the bonding agent 2 (eg, epoxy adhesive containing Ag, epoxy adhesive containing diamond, solder alloy, etc.), the thermal resistance of the device can be greatly reduced. Is.

FIG. 2 is a sectional view showing a second embodiment of the present invention. The wiring board 13 has an I / O pin 14 for making a connection for electrically connecting the pad B11 and the I / O pin 14 provided on the surface with the same pitch as the bump 7, and the pad B11 and the I / O pin 14 for connection. And an in-layer wiring 12 for electrically connecting and. The carrier substrate 5 and the wiring substrate 3 are electrically connected to each other by joining the pads B11 and the bumps B7 arranged on the wiring substrate 13 at the same pitch as the bumps B7 with the solder B10. At this time, the solder B10 used is lower than the melting point of the solder A3 used for connecting the carrier substrate 5 and the LSI 8. For example, when Au / Sn solder (80/20 WT%) is used for the solder A3, Sn / Pb solder (63
/ 37WT%). As the wiring board 13, a material having excellent electric characteristics, a thermal expansion coefficient close to that of the carrier board 5, and a material capable of being co-fired with the conductor is selected.
For example, AlN, Cu, Ag and Au are used.

A plurality of carriers 17 shown in FIG. 1 are mounted on the strip 13 of the wiring board. At the time of mounting, by narrowing the space between the carriers 17 and increasing the density of mounting the carriers, it is possible to shorten the connection wiring length of the LSI 8, thus improving the processing capability of the device. You can

[0016]

As described above, by filling the gap between the LSI and the carrier substrate with the sealant, the LSI can be hermetically sealed and the thermal stress can be relaxed, and the reliability of the device can be improved. Moreover, there is no limitation in selecting the material of the carrier substrate. Further, since it is not necessary to consider the height variation of the LSI and the number of kinds of solder is reduced, a carrier having excellent assembling ability and low manufacturing cost can be obtained. Furthermore, the effect of mounting the heat spreader has the effect of significantly reducing the thermal resistance of the device.

Further, by mounting the device on the wiring board, a device having a high packing density can be obtained, so that the information processing capability of the device can be remarkably enhanced.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a first conventional example.

FIG. 4 is a sectional view showing a second conventional example.

[Explanation of symbols]

 1 Heat Spreader 2 Bonding Material 3 Solder A 4 Sealant 5 Carrier Substrate 6 Carrier Internal Wiring 7 Bump B 8 LSI 9 Pad A 10 Solder B 11 Pad B 12 Layer Internal Wiring 13 Wiring Board 14 I / O Pin 15 Bump A 16 Bump 17 Carrier 18 Piston 19 LSI Chip 20 Solder C 21 Base Substrate 22 Cap 23 Solder D 24 Solder Bump A 25 Solder Bump B

Claims (2)

[Claims] 1. An LSI mounting structure of a semiconductor device comprising an LSI chip having connection terminals on the entire circuit surface and a chip carrier substrate on which the LSI chip is mounted face down, and a heat spreader is provided on the back surface side of the LSI chip. An LSI mounting structure is characterized in that a gap between the LSI chip and the chip carrier substrate is filled with a sealant to seal the LSI chip. 2. The LSI mounting structure according to claim 1, wherein the chip carrier is mounted on a wiring board.