CA2093409A1 - Integrated circuit chip carrier and its packaging - Google Patents
Integrated circuit chip carrier and its packagingInfo
- Publication number
- CA2093409A1 CA2093409A1 CA 2093409 CA2093409A CA2093409A1 CA 2093409 A1 CA2093409 A1 CA 2093409A1 CA 2093409 CA2093409 CA 2093409 CA 2093409 A CA2093409 A CA 2093409A CA 2093409 A1 CA2093409 A1 CA 2093409A1
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- Prior art keywords
- integrated circuit
- chip carrier
- circuit chip
- lsi chip
- set forth
- Prior art date
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
An LSI chip 8 having bumps 15, which serve as a connecting terminal, on its circuit surface, is loaded on a carrier sub-strate 5, with its face down. A sealing agent 4 is filled within a gap between the LSI chip 8 and the carrier substrate 5 to seal the circuit surface of the LSI chip 8. Further, a heat spreader 1 is joined on the surface opposite to the circuit surface of the LSI chip 8 so that the thermal stress caused by the differ-ence between the thermal expansion coefficient of the LSI chip 8 and that of the carrier substrate 5 can be alleviated and an LSI packaged structure having a further excellent cooling efficiency can be obtained.
An LSI chip 8 having bumps 15, which serve as a connecting terminal, on its circuit surface, is loaded on a carrier sub-strate 5, with its face down. A sealing agent 4 is filled within a gap between the LSI chip 8 and the carrier substrate 5 to seal the circuit surface of the LSI chip 8. Further, a heat spreader 1 is joined on the surface opposite to the circuit surface of the LSI chip 8 so that the thermal stress caused by the differ-ence between the thermal expansion coefficient of the LSI chip 8 and that of the carrier substrate 5 can be alleviated and an LSI packaged structure having a further excellent cooling efficiency can be obtained.
Description
~3~S~`3 INTEGRATED CIRCUIT CHIP CARRIER AND ITS PACKAGING
FIEL.D OF THE INVENTION
The present invention relates to a chip carrier of the LSI
integrated circuit or the like and ~ packaging achieved by load-ing the chip carrier on a circuit board, which are used in an electronic apparatus such as, for example, a data processing unit.
BACKGROUND OF THE INVENTION
In recen-t years, the integration of the integrated circuit which is used in the data processing apparatus or the like has been more and more increased. Accordingly, an LSI has been used as the integrated circuit, and its number of terminals and power consumption have been increased, which in turn has called for an LSI packaged structure which is high in packaging density as well as highly reliable and excellent in cooling efficiency.
Fig. 1 is a cross-sectional view of a specific embodiment of a prior LSI chip packaged structure which is described within "40th ELECTRONIC COMPONENT & TECHNOLOGY CONFERENCE (ECTC)", pp.
613 through 619, 1990, in which an LSI chip 8 having bumps 16 on the entire surface (circuit surface) is soldered on a circuit board 13 with its face down. Heat evolving on the circuit face of the LSI chip 8, after transmitted to a piston 18 which is pressed by a spring 26 so as to come directly in contact with the rear surface of the chip, is emitted through a housing 27 to a cooling member 28. In addition, power supply to the LSI chip and the signal input/output theretc and therefrom are achieved by connecting the bumps 16 through the circuit board 13 to the outside of the apparatus. Taking the inclination of - 2 - ~0~31~
the LST chip 8 and the var;ation of the height between each LSI into account, -the piston is so arranged that its height can be adjusted.
Fig. 2 is a cross-sectional view of a specific embodiment of a conventional LSI chip package which is described within "41th ECTC", pp. 693 through 703, 1991. In this technique, an LSI chip 19 having solder bumps 25 on -the circuit surface is attached to a base substra-te 21 with its face down. Cap 22 is connected to the rear surface of -the LSI chip 19 by solder 23, and to a base substrate 21 by solder 20, respectively. Thus, the heat evolving at the LSI chip 19 is delivered through the LSI chip per se and the cap 22 to the outside. The LSI chip carrier is composed of the above-mentioned components.
However, the foregoing conventional LSI chip packaging has suffered the following problems.
That is, in the conventional embodiment of Fig. 1, if the heat evolving amount of the LSI chip 8 becomes large, then it becomes difficult to deliver the heat to the outside of the apparatus and, because of the exposed bump 16, its moisture-proof and airtightness are low, and the reliability of the LSIis low.
Further, in the conven-tional embodiment of Fig. 2, the soldered positions are numerous, selection of the materials and their assembly become very complicated and the cost is also increased. Further, if, when the cap 22 is a-ttached to the LSI
chip 19, the LSI chip 19 is inclined, then the gap between the cap 22 and the LSI chip 19 is widened to make it impossible to achieve an excellent thermal resistance or to cause the LSI
chip 19 and the cap 22 to come into contact with each other to break the LSI chip 19, which cannot assure a stable assembly.
FIEL.D OF THE INVENTION
The present invention relates to a chip carrier of the LSI
integrated circuit or the like and ~ packaging achieved by load-ing the chip carrier on a circuit board, which are used in an electronic apparatus such as, for example, a data processing unit.
BACKGROUND OF THE INVENTION
In recen-t years, the integration of the integrated circuit which is used in the data processing apparatus or the like has been more and more increased. Accordingly, an LSI has been used as the integrated circuit, and its number of terminals and power consumption have been increased, which in turn has called for an LSI packaged structure which is high in packaging density as well as highly reliable and excellent in cooling efficiency.
Fig. 1 is a cross-sectional view of a specific embodiment of a prior LSI chip packaged structure which is described within "40th ELECTRONIC COMPONENT & TECHNOLOGY CONFERENCE (ECTC)", pp.
613 through 619, 1990, in which an LSI chip 8 having bumps 16 on the entire surface (circuit surface) is soldered on a circuit board 13 with its face down. Heat evolving on the circuit face of the LSI chip 8, after transmitted to a piston 18 which is pressed by a spring 26 so as to come directly in contact with the rear surface of the chip, is emitted through a housing 27 to a cooling member 28. In addition, power supply to the LSI chip and the signal input/output theretc and therefrom are achieved by connecting the bumps 16 through the circuit board 13 to the outside of the apparatus. Taking the inclination of - 2 - ~0~31~
the LST chip 8 and the var;ation of the height between each LSI into account, -the piston is so arranged that its height can be adjusted.
Fig. 2 is a cross-sectional view of a specific embodiment of a conventional LSI chip package which is described within "41th ECTC", pp. 693 through 703, 1991. In this technique, an LSI chip 19 having solder bumps 25 on -the circuit surface is attached to a base substra-te 21 with its face down. Cap 22 is connected to the rear surface of -the LSI chip 19 by solder 23, and to a base substrate 21 by solder 20, respectively. Thus, the heat evolving at the LSI chip 19 is delivered through the LSI chip per se and the cap 22 to the outside. The LSI chip carrier is composed of the above-mentioned components.
However, the foregoing conventional LSI chip packaging has suffered the following problems.
That is, in the conventional embodiment of Fig. 1, if the heat evolving amount of the LSI chip 8 becomes large, then it becomes difficult to deliver the heat to the outside of the apparatus and, because of the exposed bump 16, its moisture-proof and airtightness are low, and the reliability of the LSIis low.
Further, in the conven-tional embodiment of Fig. 2, the soldered positions are numerous, selection of the materials and their assembly become very complicated and the cost is also increased. Further, if, when the cap 22 is a-ttached to the LSI
chip 19, the LSI chip 19 is inclined, then the gap between the cap 22 and the LSI chip 19 is widened to make it impossible to achieve an excellent thermal resistance or to cause the LSI
chip 19 and the cap 22 to come into contact with each other to break the LSI chip 19, which cannot assure a stable assembly.
- 3 - 2~
Still further, the thermal stress caused by -the operating or non--operating apparatus is exerted intensively on the solder bump 25, which creates a cause of breakdown. In addition, in order to alleviate this thermal stress, it is necessary to select a base substrate which does not practically suffer a difference in thermal expansion coefficient between the same and the LSI chip 19, which restricts the scope of selection of the materials.
SUMMARY OF THE INVENTIO~
In view of the foregoing circumstances, an object of the present invention is to provide a packaged structure of an integrated circuit chip and a chip carrier used therein which allow the reliability of the apparatus to be improved by alle-viating thermal s-tress.
Another object of the presen-t invention is to provide a packaged structure of the integrated circuit and a chip carrier used therein which suffers a minor restriction in selecting the material of the carrier substrate.
According to the present invention, in order to achieve the forgoing end, there is provided a chip carrier in which an integrated circuit chip having a group of connecting terminals on the circuit surface is loaded on a chip carrier substrate having a group of first connecting terminals on either one surface thereof with its face down to electrically connect the connecting -terminal of the integrated circuit chip and the first connecting terminal of the chip carrier substrate, a sealing agent being filled within a gap formed between the integrated circuit chip and the chip carrier substrate to seal the circuit surface of the integrated circuit chip.
Still further, the thermal stress caused by -the operating or non--operating apparatus is exerted intensively on the solder bump 25, which creates a cause of breakdown. In addition, in order to alleviate this thermal stress, it is necessary to select a base substrate which does not practically suffer a difference in thermal expansion coefficient between the same and the LSI chip 19, which restricts the scope of selection of the materials.
SUMMARY OF THE INVENTIO~
In view of the foregoing circumstances, an object of the present invention is to provide a packaged structure of an integrated circuit chip and a chip carrier used therein which allow the reliability of the apparatus to be improved by alle-viating thermal s-tress.
Another object of the presen-t invention is to provide a packaged structure of the integrated circuit and a chip carrier used therein which suffers a minor restriction in selecting the material of the carrier substrate.
According to the present invention, in order to achieve the forgoing end, there is provided a chip carrier in which an integrated circuit chip having a group of connecting terminals on the circuit surface is loaded on a chip carrier substrate having a group of first connecting terminals on either one surface thereof with its face down to electrically connect the connecting -terminal of the integrated circuit chip and the first connecting terminal of the chip carrier substrate, a sealing agent being filled within a gap formed between the integrated circuit chip and the chip carrier substrate to seal the circuit surface of the integrated circuit chip.
4 2 ~ 9 ~, 1J ~
In one embodiment of the present invention, a heat spreader is ~jointed to the surface of the integrated circui-t chip oppo-site to the circui-t surface.
Further, according to the present invention, in order to achieve the forgoing end, there is provided a packaged structure of the integrated circuit chip carrier in which the foregoing chip carrier is loaded on a circuit board.
According to the present invention, the sealing agent is filled between the integrated circuit chip and the carrier substrate to allow the integrated circuit chip -to be airtightly sealed and the thermal stress to be alleviated thus improving the reliability of the apparatus. Further, the restrictions posed on the selection of the carrier substrate material may also be reduced. Further, since the height variation of the integrated circuit chip is not necessary to take into consider-ation, a carrier which is excellent in assembling performance and low in manufacturing cost can be obtained. Still further, because of the attached heat spreader, a drastic reduction of the thermal stress o~ the apparatus can be achieved. In addi-tion, when it is loaded on the circuit board, an apparatus high in packaging density can be obtained, and the data processing capability can significantly be increased.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a cross-sectional view of a specific embodiment of a conventional LSI chip packaged structure;
Fig. 2 is a cross-sectional view of a specific embodiment of a conventional LSI chip packaged structure;
Fig. 3 is a cross-sectional view of a first embodiment of an LSI chip carrier according to the present invention;
In one embodiment of the present invention, a heat spreader is ~jointed to the surface of the integrated circui-t chip oppo-site to the circui-t surface.
Further, according to the present invention, in order to achieve the forgoing end, there is provided a packaged structure of the integrated circuit chip carrier in which the foregoing chip carrier is loaded on a circuit board.
According to the present invention, the sealing agent is filled between the integrated circuit chip and the carrier substrate to allow the integrated circuit chip -to be airtightly sealed and the thermal stress to be alleviated thus improving the reliability of the apparatus. Further, the restrictions posed on the selection of the carrier substrate material may also be reduced. Further, since the height variation of the integrated circuit chip is not necessary to take into consider-ation, a carrier which is excellent in assembling performance and low in manufacturing cost can be obtained. Still further, because of the attached heat spreader, a drastic reduction of the thermal stress o~ the apparatus can be achieved. In addi-tion, when it is loaded on the circuit board, an apparatus high in packaging density can be obtained, and the data processing capability can significantly be increased.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a cross-sectional view of a specific embodiment of a conventional LSI chip packaged structure;
Fig. 2 is a cross-sectional view of a specific embodiment of a conventional LSI chip packaged structure;
Fig. 3 is a cross-sectional view of a first embodiment of an LSI chip carrier according to the present invention;
- 5 - 2~ ~ 3 ~ ~ ~
Fig. ~ is a cross-sectiona] view of a first embodiment of the packaged structure of the LSI chip carrier according to the present invention;
Fig. 5 is a cross-sectional view of a second embodiment of the LSI chip carrier according to the present invention;
Fig. 6 is a cross-sectional view of a third embodiment of the LSI chip carrier according to the present invention;
Fig. 7 is a cross-sectionaI view of a second embodiment of the packaged structure of the l.SI chip carrier according to the present invention; and Fig. 8 is a cross-sectional view of a third embodiment of the packaged structure of the LSI chip carrier according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Several embodiments of the present invention are herein-after described with reference to the accompanying drawings.
Fig. 3 is a cross-sectional view of a first embodiment of the LSI chip carrier according to the present invention, in which bumps 15 are each provided on the circuit surface of an LSI chip 8 as the external connecting terminal. These bumps are joined in one-to-one relationship to pads 9 disposed on either one surface of a carrier substrate 5 by means of a solder 3 to electrically connect the LSI chip 8 and the carrier sub-strate 5. Within the carrier substrate 5, an interconnection6 is applied, and the portion where this interconnection reaches the other surface of the carrier substrate 5 (the surface where the LSI chip 8 is not loaded) is provided with bumps 7 which each serve as a connecting terminal leading to the outside of the carrier. As described above, since the LSI chip 8 and the - 6- 2()a3'~39 bumps 7 provided on the rear surface of the carrier subs-trate 5 are interconnected, i-t is possible to enter the electrical signal from the LSI chip 8 to the outside o-~ the carrier sub-strate 5 and vise versa. As the carrier substrate 5, a material which can be fired simultaneol~sly with the internal connection 6 and which is low in dielectric constant and close to the LSI
chip 8 in -thermal expansion coefficient, such as glass ceramic, mullite, alumina, silicon nitride, AlN or the like, may be used.
On the other hand, a sealing agent ~ is filled within a gap between the LSI chip 8 and the carrier substrate 5, between the bumps 15 and on the lateral surface of the LSI chip 8, and the circuit surface of the LSI chip 8 is completely airtightly sealed. Further, on the entire rear surface of the LSI chip 8, a heat spreader 1 is die bonded by a bonding agen-t 2.
In the above-described manner, an LSI chip carrier 17 is arranged. When this carrier is assembled, first, the LSI chip 8 is soldered on the carrier substrate 5 by the solder 3 and, thereafter, the sealing agent 4 is filled and, lastly, the heat spreader 1 is mounted. At this time, care should be taken so that any air bubbles may not be included within the sealing agent 4 and the bonding agent 2.
As the sealing agent 4, for example, silicone resins or epoxy resins may be used. If, as the resin sealing agent 4, one having the effect of protecting against a ray, which causes error operation of the LSI, then the reliability of the a ray-proof can also be obtained.
The LSI chip 8, which calls for a great amount of power consumption, can cause a considerable temperature difference within the apparatus depending on whether the apparatus is operating or not. Therefore, if no sealing agent 4 is present, ~ 7 - 2 0 9 ~ f.~
a great tllermal stress can be genera-ted based on the difference in thermal expansion coefficient between the LSI chip 8, bump 15 and the carrier substrate 5, which in turn can cause a crack on the LSI chip 8, solder 3 or carrier substrate 5, or cut off or short-circuit the internal connection 6 of the carrier sub-strate or the connection within the LSI chip 8.
However, in the foregoing embodiment according to the present invention, since the sealing agent 4 is filled between the LSI chip 8 and the carrier substrate 5 and between each of the bumps 15 without any gap, the sealing agent can alleviate the thermal stress caused depending on the operation or non-operation of the apparatus. As a result, the breakdown of the apparatus due to the generating of crack becomes unlikely thus increasing the reliability of the apparatus remarkably. Further, since the circuit surface of the LSI chip 8 cannot be exposed to the outside by filling the sealing agent 4, it becomes possible to protect the circuit surface of the LSI chip 8 from dew, dust and its contact with the outside.
The heat evolving from the circuit surface of the LSI chip 8 reaches the rear surface through the LSI chip per se. At this time, since the heat spreader 1 is die bonded to the rear surface of the LSI chip 8 with a bonding agent 2 having an excellent thermal conductivity, the heat which has reached the rear surface of the LSI chip 8 can extensively spread, and a high heat radiating effect can be obtained to the outside of the carrier. Further, since the heat spreader 1 is mounted to the LSI chip 8, it is possible to alleviate a possible mechanical impact applied on the LSI chip 8 when the cooling member is disposed on the rear surface side of the LSI chip 8.
As the heat spreader 1, a material which has a large thermal conductivity and which is close to the LSI chip 8 in thermal expansion coefficien-t (for example, SiC, AlN or the like) may be used. Further, if the bonding agent 2 is made of a material having a high thermal conductivity (for example, an epoxy adhesive agent including Ag, epoxy adhesive agent includ-ing diamond, solder alloy or the like), then it is possible to greatly reduce the thermal resistance of the apparatus.
Further, when the thermal expansion coefficient of the carrier substrate 5 deviates from that of the LSI chip 8, if the heat spreader 1 is made of a material having the thermal expansion coefficient close to that of the carrier substrate 5 (for example, if the carrier substrate 5 is made of alumina, then Cu/W is used as -the ma-terial for the heat spreader l), then the stress applied to the LSI chip 8 can be balanced to prevent generation of the cracks. Incidentally, in order to achieve this balance between stresses, if need be, the stress caused by the sealing agent 4 or bonding agent 2 should be taken into account.
Fig. 4 is a cross-sectional view of a first embodiment of the packaged structure of the LSI chip carrier according to the present invention. This embodiment is achieved by loading the LSI chip carrier of the Fig. 3 embodiment on the circuit board.
The circuit board 13 has pads 11 provided with the same pitch as that of the bumps 7 on either one of its surfaces, I/O pins 14 adapted to connect to the outside on the other surface and an internal connection 12 adapted to be electrically connected to the pads 11 and the I/O pins 14 therein. The carrier substrate 5 and the circuit board 13 are electrically connected by ioining the bumps 7 and the pads 11 each disposed - 9 - 20~
with the same pitch as tha-t of the bumps 7 on the circuit board 13 by -the solder lO. For the solder 10, one having a lower melting point than that of -the solder 3 used for connecting the carrier substrate 5 and the LSI chip 8 should be used.
For example, i~ Au/Sn solder (80/20 weight %) is used for the solder 3, then Sn/Pb solder (63/37 weight %) is used as the solder 10.
For the circui-t board 13, a material excellent in electri-cal characteristic, close to the carrier substrate 5 in thermal expansion coefficient and, further, which can be fired simul-taneously with the conductor adapted for internal connection, such as AlN, mullite, glass ceramic or the like may be used.
Further, as the conductor, W, Gu, Ag, Au or the like may be used.
On the circuit board 13, a plurality of LSI chip carriers 17, as shown in Fig. 3, is loaded. During loading, if the gap between the adjacent carriers 17 is narrowed to improve the loading density of the carrier, -then -the interconnecting length for the LSI chip 8 can be shortened to thereby allow the pro-cessing ability of the apparatus to be improved.
Fig. 5 is a cross-sectional view of a second embodiment of the LSI chip carrier according to the present invention, in which members each having a similar function as in Figs. 3 and 4 are each assigned with the same sign.
Reference sign 7a denotes a micropin. That is, the carrier substrate 5 according to this embodiment uses the micropin 7a in place of the bump 7 of the carrier substrate 5 which is used in the Fig. 3 embodiment. The micropin is about 0.1 mm in diameter, and 1 mm in length.
Also in this embodiment, since the sealing agent 4 is 2 ~
filled within the gap between the LSI chip 8 and -the carrier substrate 5 and between each of the bumps 15 without any gap, it can alleviate the thermal stress caused depending on the operation and non-operation of the apparatus. Because of this, the breakdown of the apparatus which can be caused by the generating of cracks becomes unlikely, and the reliability o-~the apparatus can be remarkably increased. In addition, since the circuit surface of the LSI chip 8 cannot be exposed to the outside by the filled sealing agent 4, it becomes possible to protect the circuit surface of the LSI chip 8 from dew, dust, contact with the outside or the like.
As a modified embodiment of this embodiment, bump may be used in place of the micropin 7a.
Fig. 6 is a cross-sectional view of a third embodiment of the LSI chip carrier according to the present invention, in which the same sign is assigned to the member having a similar function as in Figs. 3 through 5.
This embodiment uses a micropin 7a in place of the bump 7 of the carrier substrate 5 -for the LSI chip carrier of Fig. 3 embodiment. This embodiment displays a similar effect as in the Fig. 3 embodiment.
Fig. 7 is a cross-sectional view of a second embodiment of the packaged structure of the LSI chip carrier according to the present invention, in which the same sign is assigned to the member having a similar function as in Figs. 3 through 6.
This embodiment is achieved by loading the LSI chip carrier according to the Fig. 5 embodiment on the circuit board.
On the circuit board 13, a plurality of LSI chip carriers 17 shown in Fig. 5 is loaded. During the loading, if the gap between the adjacent carriers 17 is narrowed to improve the - 11 - 2~3~
loading dens;ty of the carrier, then ;t becomes possible to shorten the interconnecting length for the LSI chip 8 to thereby improve the processing spéed of the apparatus.
In this embodiment, since the stress alleviating e~fect can be obtained by using a soft material such as Cu or the like for the micropin 7a, one which is not close to the carrier substrate 5 in thermal expansion coefficient, such as alumina, may be used for the circuit board 13.
Alternatively, in place of the micropin 7a, bump may be used.
Fig. 8 is a cross-sectional view of a -third embodiment of the packaged structure of the LSI chip carrier according to the present invention, in which the same sign is assigned to the member having a similar function as in Figs. 3 through 7.
This embodiment is achieved by loading the LSI chip carrier according to the Fig. 6 embodiment on the circuit board.
This embodiment is also achieved by joining the heat spreader 1 to the LSI chip 8 for the LSI chip carrier 17 of the Fig. 7 embodiment. In this embodiment, the joining of the LSI chip carrier 17 and the circuit board 13 and its effect are substantially the same as in the Fig. 7 embodiment.
The present invention is not necessarily restricted to the foregoing embodiments, but various changes and modifications may be made within the scope and spirit of the appended claims.
Fig. ~ is a cross-sectiona] view of a first embodiment of the packaged structure of the LSI chip carrier according to the present invention;
Fig. 5 is a cross-sectional view of a second embodiment of the LSI chip carrier according to the present invention;
Fig. 6 is a cross-sectional view of a third embodiment of the LSI chip carrier according to the present invention;
Fig. 7 is a cross-sectionaI view of a second embodiment of the packaged structure of the l.SI chip carrier according to the present invention; and Fig. 8 is a cross-sectional view of a third embodiment of the packaged structure of the LSI chip carrier according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Several embodiments of the present invention are herein-after described with reference to the accompanying drawings.
Fig. 3 is a cross-sectional view of a first embodiment of the LSI chip carrier according to the present invention, in which bumps 15 are each provided on the circuit surface of an LSI chip 8 as the external connecting terminal. These bumps are joined in one-to-one relationship to pads 9 disposed on either one surface of a carrier substrate 5 by means of a solder 3 to electrically connect the LSI chip 8 and the carrier sub-strate 5. Within the carrier substrate 5, an interconnection6 is applied, and the portion where this interconnection reaches the other surface of the carrier substrate 5 (the surface where the LSI chip 8 is not loaded) is provided with bumps 7 which each serve as a connecting terminal leading to the outside of the carrier. As described above, since the LSI chip 8 and the - 6- 2()a3'~39 bumps 7 provided on the rear surface of the carrier subs-trate 5 are interconnected, i-t is possible to enter the electrical signal from the LSI chip 8 to the outside o-~ the carrier sub-strate 5 and vise versa. As the carrier substrate 5, a material which can be fired simultaneol~sly with the internal connection 6 and which is low in dielectric constant and close to the LSI
chip 8 in -thermal expansion coefficient, such as glass ceramic, mullite, alumina, silicon nitride, AlN or the like, may be used.
On the other hand, a sealing agent ~ is filled within a gap between the LSI chip 8 and the carrier substrate 5, between the bumps 15 and on the lateral surface of the LSI chip 8, and the circuit surface of the LSI chip 8 is completely airtightly sealed. Further, on the entire rear surface of the LSI chip 8, a heat spreader 1 is die bonded by a bonding agen-t 2.
In the above-described manner, an LSI chip carrier 17 is arranged. When this carrier is assembled, first, the LSI chip 8 is soldered on the carrier substrate 5 by the solder 3 and, thereafter, the sealing agent 4 is filled and, lastly, the heat spreader 1 is mounted. At this time, care should be taken so that any air bubbles may not be included within the sealing agent 4 and the bonding agent 2.
As the sealing agent 4, for example, silicone resins or epoxy resins may be used. If, as the resin sealing agent 4, one having the effect of protecting against a ray, which causes error operation of the LSI, then the reliability of the a ray-proof can also be obtained.
The LSI chip 8, which calls for a great amount of power consumption, can cause a considerable temperature difference within the apparatus depending on whether the apparatus is operating or not. Therefore, if no sealing agent 4 is present, ~ 7 - 2 0 9 ~ f.~
a great tllermal stress can be genera-ted based on the difference in thermal expansion coefficient between the LSI chip 8, bump 15 and the carrier substrate 5, which in turn can cause a crack on the LSI chip 8, solder 3 or carrier substrate 5, or cut off or short-circuit the internal connection 6 of the carrier sub-strate or the connection within the LSI chip 8.
However, in the foregoing embodiment according to the present invention, since the sealing agent 4 is filled between the LSI chip 8 and the carrier substrate 5 and between each of the bumps 15 without any gap, the sealing agent can alleviate the thermal stress caused depending on the operation or non-operation of the apparatus. As a result, the breakdown of the apparatus due to the generating of crack becomes unlikely thus increasing the reliability of the apparatus remarkably. Further, since the circuit surface of the LSI chip 8 cannot be exposed to the outside by filling the sealing agent 4, it becomes possible to protect the circuit surface of the LSI chip 8 from dew, dust and its contact with the outside.
The heat evolving from the circuit surface of the LSI chip 8 reaches the rear surface through the LSI chip per se. At this time, since the heat spreader 1 is die bonded to the rear surface of the LSI chip 8 with a bonding agent 2 having an excellent thermal conductivity, the heat which has reached the rear surface of the LSI chip 8 can extensively spread, and a high heat radiating effect can be obtained to the outside of the carrier. Further, since the heat spreader 1 is mounted to the LSI chip 8, it is possible to alleviate a possible mechanical impact applied on the LSI chip 8 when the cooling member is disposed on the rear surface side of the LSI chip 8.
As the heat spreader 1, a material which has a large thermal conductivity and which is close to the LSI chip 8 in thermal expansion coefficien-t (for example, SiC, AlN or the like) may be used. Further, if the bonding agent 2 is made of a material having a high thermal conductivity (for example, an epoxy adhesive agent including Ag, epoxy adhesive agent includ-ing diamond, solder alloy or the like), then it is possible to greatly reduce the thermal resistance of the apparatus.
Further, when the thermal expansion coefficient of the carrier substrate 5 deviates from that of the LSI chip 8, if the heat spreader 1 is made of a material having the thermal expansion coefficient close to that of the carrier substrate 5 (for example, if the carrier substrate 5 is made of alumina, then Cu/W is used as -the ma-terial for the heat spreader l), then the stress applied to the LSI chip 8 can be balanced to prevent generation of the cracks. Incidentally, in order to achieve this balance between stresses, if need be, the stress caused by the sealing agent 4 or bonding agent 2 should be taken into account.
Fig. 4 is a cross-sectional view of a first embodiment of the packaged structure of the LSI chip carrier according to the present invention. This embodiment is achieved by loading the LSI chip carrier of the Fig. 3 embodiment on the circuit board.
The circuit board 13 has pads 11 provided with the same pitch as that of the bumps 7 on either one of its surfaces, I/O pins 14 adapted to connect to the outside on the other surface and an internal connection 12 adapted to be electrically connected to the pads 11 and the I/O pins 14 therein. The carrier substrate 5 and the circuit board 13 are electrically connected by ioining the bumps 7 and the pads 11 each disposed - 9 - 20~
with the same pitch as tha-t of the bumps 7 on the circuit board 13 by -the solder lO. For the solder 10, one having a lower melting point than that of -the solder 3 used for connecting the carrier substrate 5 and the LSI chip 8 should be used.
For example, i~ Au/Sn solder (80/20 weight %) is used for the solder 3, then Sn/Pb solder (63/37 weight %) is used as the solder 10.
For the circui-t board 13, a material excellent in electri-cal characteristic, close to the carrier substrate 5 in thermal expansion coefficient and, further, which can be fired simul-taneously with the conductor adapted for internal connection, such as AlN, mullite, glass ceramic or the like may be used.
Further, as the conductor, W, Gu, Ag, Au or the like may be used.
On the circuit board 13, a plurality of LSI chip carriers 17, as shown in Fig. 3, is loaded. During loading, if the gap between the adjacent carriers 17 is narrowed to improve the loading density of the carrier, -then -the interconnecting length for the LSI chip 8 can be shortened to thereby allow the pro-cessing ability of the apparatus to be improved.
Fig. 5 is a cross-sectional view of a second embodiment of the LSI chip carrier according to the present invention, in which members each having a similar function as in Figs. 3 and 4 are each assigned with the same sign.
Reference sign 7a denotes a micropin. That is, the carrier substrate 5 according to this embodiment uses the micropin 7a in place of the bump 7 of the carrier substrate 5 which is used in the Fig. 3 embodiment. The micropin is about 0.1 mm in diameter, and 1 mm in length.
Also in this embodiment, since the sealing agent 4 is 2 ~
filled within the gap between the LSI chip 8 and -the carrier substrate 5 and between each of the bumps 15 without any gap, it can alleviate the thermal stress caused depending on the operation and non-operation of the apparatus. Because of this, the breakdown of the apparatus which can be caused by the generating of cracks becomes unlikely, and the reliability o-~the apparatus can be remarkably increased. In addition, since the circuit surface of the LSI chip 8 cannot be exposed to the outside by the filled sealing agent 4, it becomes possible to protect the circuit surface of the LSI chip 8 from dew, dust, contact with the outside or the like.
As a modified embodiment of this embodiment, bump may be used in place of the micropin 7a.
Fig. 6 is a cross-sectional view of a third embodiment of the LSI chip carrier according to the present invention, in which the same sign is assigned to the member having a similar function as in Figs. 3 through 5.
This embodiment uses a micropin 7a in place of the bump 7 of the carrier substrate 5 -for the LSI chip carrier of Fig. 3 embodiment. This embodiment displays a similar effect as in the Fig. 3 embodiment.
Fig. 7 is a cross-sectional view of a second embodiment of the packaged structure of the LSI chip carrier according to the present invention, in which the same sign is assigned to the member having a similar function as in Figs. 3 through 6.
This embodiment is achieved by loading the LSI chip carrier according to the Fig. 5 embodiment on the circuit board.
On the circuit board 13, a plurality of LSI chip carriers 17 shown in Fig. 5 is loaded. During the loading, if the gap between the adjacent carriers 17 is narrowed to improve the - 11 - 2~3~
loading dens;ty of the carrier, then ;t becomes possible to shorten the interconnecting length for the LSI chip 8 to thereby improve the processing spéed of the apparatus.
In this embodiment, since the stress alleviating e~fect can be obtained by using a soft material such as Cu or the like for the micropin 7a, one which is not close to the carrier substrate 5 in thermal expansion coefficient, such as alumina, may be used for the circuit board 13.
Alternatively, in place of the micropin 7a, bump may be used.
Fig. 8 is a cross-sectional view of a -third embodiment of the packaged structure of the LSI chip carrier according to the present invention, in which the same sign is assigned to the member having a similar function as in Figs. 3 through 7.
This embodiment is achieved by loading the LSI chip carrier according to the Fig. 6 embodiment on the circuit board.
This embodiment is also achieved by joining the heat spreader 1 to the LSI chip 8 for the LSI chip carrier 17 of the Fig. 7 embodiment. In this embodiment, the joining of the LSI chip carrier 17 and the circuit board 13 and its effect are substantially the same as in the Fig. 7 embodiment.
The present invention is not necessarily restricted to the foregoing embodiments, but various changes and modifications may be made within the scope and spirit of the appended claims.
Claims (16)
1. Integrated circuit chip carrier in which an integrated circuit chip having a group of connecting terminals on the circuit surface is loaded on a chip carrier substrate having a group of first connecting terminals on either one surface there-of with its face down to electrically connect the connecting terminal of said integrated circuit chip and the first connect-ing terminal of said chip carrier substrate, characterized in that a sealing agent is filled within a gap between said inte-grated circuit chip and said chip carrier substrate to seal the circuit surface of said integrated circuit chip.
2. Integrated circuit chip carrier as set forth in Claim 1 wherein said chip carrier substrate has an internal connection, has a group of second connecting terminals on its other surface, and said first and second connecting terminals are electrically connected to each other via said internal connection.
3. Integrated circuit chip carrier as set forth in Claim 1 wherein the connecting terminal of said integrated circuit chip comprises a bump.
4. Integrated circuit chip carrier as set forth in Claim 1 wherein said first connecting terminal of said chip carrier substrate comprises a pad.
5. Integrated circuit chip carrier as set forth in Claim 2 wherein said second connecting terminal of said chip carrier substrate comprises a bump.
6. Integrated circuit chip carrier as set forth in Claim 2 wherein said second connecting terminal of said chip carrier substrate comprises a micropin.
7. Integrated circuit chip carrier as set forth in Claim 1 wherein said connecting terminal of said integrated circuit chip and said first connecting terminal of said chip carrier substrate are connected to each other by solder.
8. Integrated circuit chip carrier as set forth in Claim 1 wherein said sealing agent comprises a silicone resin or an epoxy resin.
9. Integrated circuit chip carrier as set forth in Claim 1 wherein a heat spreader is joined to the surface opposite to the circuit surface of said integrated circuit chip.
10. Integrated circuit chip carrier as set forth in Claim 9 wherein the thermal expansion coefficient of said heat spreader is substantially equal to that of said chip carrier substrate.
11. Integrated circuit chip carrier as set forth in Claim 1 wherein said integrated circuit comprises an LSI.
12. Packaged structure of the integrated circuit chip carrier wherein an integrated circuit chip carrier is loaded on a circuit board, and, in said integrated circuit chip carrier, an integrated circuit chip having a group of connecting termi-nals on its circuit surface is loaded on a chip carrier sub-strate having a group of first connecting terminals on either one surface thereof, with its face down, to electrically connect the connecting terminal of said integrated circuit chip and the first connection terminal of said chip carrier substrate, characterized in that a sealing agent is filled within a gap between said integrated circuit chip and said chip carrier sub-strate to seal the circuit surface of said integrated circuit chip.
13. Packaged structure of the integrated circuit chip carrier as set forth in Claim 12 wherein:
said chip carrier substrate has an internal connection, has a group of second connecting terminals on its other surface, said first connecting terminal and said second connecting termi-nal being electrically connected to each other via said internal connection;
said circuit board has an internal connection, has a group of first connecting terminals on either one surface thereof, has a group of second connecting terminals on its other surface, these first and second connecting terminals being electrically connected to each other via said internal connection of said circuit board; and said second connecting terminal of the chip carrier sub-strate and said first connecting terminal of the circuit board are electrically connected to each other.
said chip carrier substrate has an internal connection, has a group of second connecting terminals on its other surface, said first connecting terminal and said second connecting termi-nal being electrically connected to each other via said internal connection;
said circuit board has an internal connection, has a group of first connecting terminals on either one surface thereof, has a group of second connecting terminals on its other surface, these first and second connecting terminals being electrically connected to each other via said internal connection of said circuit board; and said second connecting terminal of the chip carrier sub-strate and said first connecting terminal of the circuit board are electrically connected to each other.
14. Packaged structure of the integrated circuit chip carrier as set forth in Claim 13 wherein said first connecting terminal of the circuit board comprises a pad.
15. Packaged structure of the integrated circuit chip carrier as set forth in Claim 13 wherein said second connecting terminal of the circuit board comprises a pin.
16. Packaged structure of the integrated circuit chip carrier as set forth in Claim 13 wherein said second connecting terminal of the integrated circuit chip carrier substrate and said first connecting terminal of the circuit board are connected to each other by solder.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8381592A JPH05326625A (en) | 1992-04-06 | 1992-04-06 | Lsi mounting structure |
| JP083815/1992 | 1992-04-06 | ||
| JP214832/1992 | 1992-08-12 | ||
| JP4214832A JPH0661306A (en) | 1992-08-12 | 1992-08-12 | Chip carrier and its mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2093409A1 true CA2093409A1 (en) | 1993-10-07 |
Family
ID=26424861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2093409 Abandoned CA2093409A1 (en) | 1992-04-06 | 1993-04-05 | Integrated circuit chip carrier and its packaging |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2093409A1 (en) |
-
1993
- 1993-04-05 CA CA 2093409 patent/CA2093409A1/en not_active Abandoned
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Dead |