JPS5850021B2 - Manufacturing method for semiconductor devices - Google Patents
Manufacturing method for semiconductor devicesInfo
- Publication number
- JPS5850021B2 JPS5850021B2 JP57122986A JP12298682A JPS5850021B2 JP S5850021 B2 JPS5850021 B2 JP S5850021B2 JP 57122986 A JP57122986 A JP 57122986A JP 12298682 A JP12298682 A JP 12298682A JP S5850021 B2 JPS5850021 B2 JP S5850021B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- container
- wiring
- film carrier
- external connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
Description
【発明の詳細な説明】
本発明は半導体装置に関し、殊に容器内の結線にフィル
ムキャリヤ実装体を適用した半導体装置の製法に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a film carrier mounting body is used for connection within a container.
現在用いられている半導体素子の実装方式はワイヤボン
ディング方式が主流である。The wire bonding method is the mainstream method for mounting semiconductor elements currently in use.
ワイヤボンディング方式は容器に固着した半導体素子の
電極と容器上のリードとを３０〜５０μｍφの金線又は
アルミニウム線で接続するものである。The wire bonding method connects the electrodes of a semiconductor element fixed to a container and the leads on the container with a gold wire or aluminum wire with a diameter of 30 to 50 μm.
一方、接続にワイヤを使用しない所謂ワイヤレスボンデ
ィング方式は１９６０年後半より例えばフリップチップ
、バンプスオンサブストレート、ビームリード、ビーム
リードオンサブストレート、サブリードボンディング、
チップ埋め込み及びフィルムキャリヤ等多くの方式が提
案されている。On the other hand, so-called wireless bonding methods that do not use wires for connection have been introduced since the late 1960s, such as flip chip, bump-on-substrate, beam lead, beam lead-on substrate, sub-lead bonding, etc.
Many methods have been proposed, such as chip embedding and film carrier.
ワイヤレスボンディング方式はその開発当初より多ピン
化及び高い生産性が期待されていたが未だ広く実用化さ
れてはいない。Since the beginning of its development, the wireless bonding method has been expected to increase the number of pins and increase productivity, but it has not yet been widely put into practical use.
これは半導体素子からの放熱性が悪く（殊にビームリー
ド等）素子の価格が高くなり（殊にビームリード及びバ
ンプスオンサブストレート）、また実装技術が複雑で（
殊にチップ埋込み）信頼性が低い為である。This is because the heat dissipation from the semiconductor element is poor (especially for beam leads, etc.), the cost of the element is high (especially for beam leads and bump-on-substrate), and the mounting technology is complicated (
This is because the reliability (especially in chip embedding) is low.
殊にワイヤレスボンディング方式では半導体素子と収容
容器基板間との接触面積が小さく両者間に大きな空隙空
間がある為、素子を基板に直接固着する一般のワイヤボ
ンディング方式に比較して素子の放熱性が著しく劣って
いた。In particular, in the wireless bonding method, the contact area between the semiconductor element and the container substrate is small, and there is a large gap between them, so the heat dissipation of the element is lower than that of the general wire bonding method, which directly fixes the device to the substrate. It was significantly inferior.
本発明は従来のワイヤレスボンディング方式にあった上
記の欠点を考慮して、フィルムキャリヤ方式及びチップ
埋込み方式等の利点を生かし、さらにハンダ接合を使用
して改良された半導体素子の実装方法を提供するもので
ある。The present invention takes into consideration the above-mentioned drawbacks of the conventional wireless bonding method, takes advantage of the advantages of the film carrier method and the chip embedding method, and further provides an improved semiconductor device mounting method using solder bonding. It is something.
以下、実施例について本発明の詳細な説明する。Hereinafter, the present invention will be described in detail with reference to Examples.
第１図に本発明にかかるフィルムキャリヤ配線体１を示
す。FIG. 1 shows a film carrier wiring body 1 according to the present invention.
同図において、２は可撓性透明フィルムで、例えばポリ
イミド、ポリアミドイミド、紙等の少くとも５〜１０分
の短時間に亘つて３００℃程度の加熱に耐える材料から
なる。In the figure, reference numeral 2 denotes a flexible transparent film made of a material such as polyimide, polyamideimide, paper, etc. that can withstand heating at about 300° C. for at least 5 to 10 minutes.
３は有機接着剤である。3 is an organic adhesive.
５は約３５μｍ厚さの鋼よりなる平らな配線体（層）で
、接着剤３に面した一面に錫６０重量％鉛４０重量％の
共晶ハンダ層４を有し、他面にハンダに対して濡れ性が
悪く又銅に対して密着性の良好な例えばクロム、チタン
あるいはポリイミド等よりなるハンダダム６と例えば錫
３０亜鉛７０．鉛９４．５銀５．５、錫１０亜鉛９０等
からなる融点が３７０〜４００℃のハンダで形成したバ
ンプ７．８を有する。5 is a flat wiring body (layer) made of steel with a thickness of about 35 μm, and has a eutectic solder layer 4 of 60% tin and 40% lead by weight on one side facing the adhesive 3, and a layer 4 of eutectic solder containing 60% tin and 40% lead by weight on the other side. In contrast, solder dam 6 is made of, for example, chromium, titanium, or polyimide, which has poor wettability and good adhesion to copper, and tin 30, zinc 70. It has bumps 7.8 formed of solder having a melting point of 370 to 400° C. and is made of 94.5 parts lead, 5.5 parts silver, 10 parts tin, and 90 parts zinc.
尚、バンプ７゜８は実装体１底面のほぼ両端部に配置さ
れ、ハンダ層４の厚さを１０〜３０μｍ、バンプ７．８
の高さを１００〜５００μｍに形成すると以後の工程に
おいて好都合である。Incidentally, the bumps 7.8 are arranged at almost both ends of the bottom surface of the mounting body 1, and the thickness of the solder layer 4 is set to 10 to 30 μm, and the bumps 7.8
It is convenient to form the height of 100 to 500 μm in subsequent steps.
配線層５はフォトエツチング或はスタンピングにより、
ハンダダム６は蒸着とフォトエツチング或はマスク蒸着
により、又バンプ７．８はマスク蒸着とウェットバック
或はスクリーンプリントにより製造する。The wiring layer 5 is formed by photoetching or stamping.
The solder dam 6 is manufactured by vapor deposition and photoetching or mask vapor deposition, and the bumps 7.8 are manufactured by mask vapor deposition and wet back or screen printing.
ここでバンプ８は、後述の半導体素子の電極へ接続され
る端子部を構威し、またバンプ７は半導体素子収容器に
配線される外部接続端子等へ接続される端子部を構成す
る。Here, the bump 8 constitutes a terminal portion connected to an electrode of a semiconductor element, which will be described later, and the bump 7 constitutes a terminal portion connected to an external connection terminal etc. wired to the semiconductor element housing.
従って、これらのバンプを有する配線体はその数を半導
体素子の電極の数と同じ数として構成される。Therefore, the number of wiring bodies having these bumps is the same as the number of electrodes of the semiconductor element.
上記のようにして製造したフィルムキャリヤ配線体１を
半導体素子に仮付けするためのインナーリードボンディ
ングの方法を第２図に示す。FIG. 2 shows an inner lead bonding method for temporarily bonding the film carrier wiring body 1 manufactured as described above to a semiconductor element.
同図において１０はシリコン等から構成される半導体素
子で一面（上面）に電極９を、また他面（下面）に亘っ
て金属層１１を備える。In the figure, 10 is a semiconductor element made of silicon or the like, and has an electrode 9 on one surface (upper surface) and a metal layer 11 over the other surface (lower surface).
電極９の少くとも表層はバンプ８に対して濡れ性のよい
金属にすることが必要である。At least the surface layer of the electrode 9 needs to be made of a metal that has good wettability to the bumps 8.
該半導体素子１０はウェハー状態のままで融点がワック
ス等約１５０℃程の接着層１２を介して保持板１３に固
着された後、さらにダイヤモンドソー等の切断工具によ
り所定間隔に該ウェハーを切断し接着層１２まで至る切
離し用溝１２ａが形成される。After the semiconductor element 10 is fixed in a wafer state to a holding plate 13 via an adhesive layer 12 having a melting point of wax or the like of approximately 150° C., the wafer is further cut into predetermined intervals using a cutting tool such as a diamond saw. A cutting groove 12a extending to the adhesive layer 12 is formed.
そして、該切離し用溝を付けた連続状の半導体素子を保
持板１３に載せた状態でホットプレート１４上に置き１
５０〜１８０℃に加熱する。Then, the continuous semiconductor element with the separation groove is placed on the holding plate 13 and placed on the hot plate 14.
Heat to 50-180°C.
この際、接着層１２は溶融して保持板１３に付着してい
る。At this time, the adhesive layer 12 is melted and adhered to the holding plate 13.
かかる状態において半導体素子の電極９に前記配線体の
バンプ８を位置合わせし、上方より工具１５で矢印の方
向に軽く押圧して両者を接触させてインナーリードボン
ディングを行なう。In this state, the bumps 8 of the wiring body are aligned with the electrodes 9 of the semiconductor element, and pressed lightly from above in the direction of the arrow with the tool 15 to bring them into contact and perform inner lead bonding.
次にフィルムキャリヤ配線体１を引き上げると、接着層
１２はホットプレート１４の加熱で溶けているので第３
図に示すように１個の半導体素子１０が保持板１３から
フィルムキャリヤ配線体上に接続されて取り出される。Next, when the film carrier wiring body 1 is pulled up, the adhesive layer 12 has been melted by the heating of the hot plate 14, so the third
As shown in the figure, one semiconductor element 10 is connected to the film carrier wiring body and taken out from the holding plate 13.
このようにして構成したフィルムキャリヤ実装体を１６
で示す。The film carrier assembly constructed in this way was assembled into 16
Indicated by
この時、第３図に示すように半導体素子１０の下面には
接着層１２が一部残存するが、適当な溶剤を用いて除去
する。At this time, as shown in FIG. 3, a portion of the adhesive layer 12 remains on the lower surface of the semiconductor element 10, but it is removed using an appropriate solvent.
第４図に該フィルムキャリヤ実装体を、実装すべき収容
容器の一つとして所謂サーディツプ型容器２１を示す。FIG. 4 shows a so-called cerdip type container 21 as one of the containers in which the film carrier mounting body is to be mounted.
同図において２２はアルミナセラミック等の熱伝導性の
良い絶縁体からなる基板で、その一面の中央付近に少く
とも最上層が鑞材に対し濡れ性の良いパターン２３を有
し、コバール等からなる外部接続用リード２４がガラス
２５により固着されている。In the figure, 22 is a substrate made of an insulator with good thermal conductivity such as alumina ceramic, and near the center of one surface, at least the top layer has a pattern 23 with good wettability for the solder material, and is made of Kovar or the like. External connection leads 24 are fixed with glass 25.
またリード２４の内端にはバンプ７に対して濡れ性の良
い金属層２６が形成されている。Further, a metal layer 26 having good wettability with respect to the bump 7 is formed at the inner end of the lead 24 .
前記フィルムキャリヤ実装体１６とサーディツプ型容器
２１をリード上の金属層２６及びバンプ７部において位
置合わせする。The film carrier mounting body 16 and the cerdip type container 21 are aligned at the metal layer 26 on the lead and the bump 7 portion.
この際フィルム２が透明であるので整合点が見えて好都
合である。At this time, since the film 2 is transparent, it is convenient because the matching points can be seen.
これと同時にハンダ層２７がパターン２３上に載せられ
る。At the same time, a solder layer 27 is placed on the pattern 23.
かかる状態において容器２１を３８０〜４００℃に加熱
するとバンプ７．８及び・・ンダ層２７が同時に溶融し
、半導体素子１０の電極９はフィルム実装体１６を介し
て外部接続用リード２４へ接続され且つ該半導体素子１
０は容器２１へ固着され続いて徐冷することにより一体
化される。When the container 21 is heated to 380 to 400° C. in such a state, the bumps 7.8 and the layer 27 are simultaneously melted, and the electrodes 9 of the semiconductor element 10 are connected to the external connection leads 24 via the film mounting body 16. and the semiconductor element 1
0 is fixed to the container 21 and then integrated by slow cooling.
次いで再び２５０°Ｃ程に加熱して前記有機接着剤３を
溶融し可撓性透明フィルムを除去した後。Then, the organic adhesive 3 was melted by heating to about 250° C. and the flexible transparent film was removed.
更に４３０〜４５０℃に加熱してガラス３２によりキャ
ップ３３を固着し実装構造体が完成する。Further, the cap 33 is fixed with the glass 32 by heating to 430 to 450° C., and the mounting structure is completed.
第５図に本発明による半導体装置の構造３１を示す。FIG. 5 shows a structure 31 of a semiconductor device according to the present invention.
本発明は上記のように構成したので下記に示す如く多く
の利点を有する。Since the present invention is configured as described above, it has many advantages as shown below.
（１）半導体素子が基板へ直接固着されることにより半
導体素子から基板への熱抵抗は従来のワイヤレスボンデ
ィング方式に比し約１／１０となり１〔Ｗ〕当り１°Ｃ
以下である。(1) Since the semiconductor element is directly fixed to the substrate, the thermal resistance from the semiconductor element to the substrate is approximately 1/10 compared to the conventional wireless bonding method, and is 1°C per 1 [W].
It is as follows.
又配線体５の断面積をワイヤボンディング方式における
ワイャに比し大きくすることができ、該配線体５を介し
ての熱放散性がすぐれている（例えばワイヤー３０μｍ
φ、リード＝５ ｏμｍｘｉ ｏ。In addition, the cross-sectional area of the wiring body 5 can be made larger than that of a wire in the wire bonding method, and heat dissipation through the wiring body 5 is excellent (for example, when the wire is 30 μm thick,
φ, lead = 5 oμmxi o.
μｍ）。μm).
（２）半導体素子の固着と、該半導体素子の電極及び外
部接続用リードの配線体への接続固着を同時に行なえる
ので組立工数が減少し又技術的に容易である。(2) Since the fixation of the semiconductor element and the connection and fixation of the electrodes of the semiconductor element and external connection leads to the wiring body can be performed simultaneously, the number of assembly steps is reduced and it is technically easy.
（３）・・ンダ接合を利用しているので多ピン化に有利
である。(3) It is advantageous for increasing the number of pins because it uses a solder junction.
（４）配線層上部の・・ンダ層の厚みが大きくとれるの
で配線が丈夫であり耐酸性及び耐薬品性にすぐれている
。(4) Since the thickness of the layer above the wiring layer can be increased, the wiring is strong and has excellent acid resistance and chemical resistance.
（５）容器を大型化し、半導体素子を複数個搭載するこ
とが可能である。(5) It is possible to increase the size of the container and mount a plurality of semiconductor elements thereon.
（６）配線抵抗が小さく又電流容量を大きくとることが
できる。(6) Wiring resistance is low and current capacity can be increased.
なお、以上の説明にあっては、半導体素子収容容器とし
てサーディツプ型容器を掲げたが、本発明はこれに限定
されるものではなく、他の封止構造をとるのに適用し得
ることはもちろんである。In the above description, a cerdip type container is used as the semiconductor device storage container, but the present invention is not limited to this, and can of course be applied to other sealing structures. It is.
第１図は本発明のフィルムキャリヤ配線体の構造を示す
図、第２図は第１図のフィルムキャリヤ配線体を半導体
素子に仮付けする要領を示す図、第３図は本発明のフィ
ルムキャリヤ実装体の構造を示す図、第４図はサーディ
ツプ型容器の構造を示す図、第５図は本発明の半導体素
子の実装構造を示す全体図である。
１・・・・°°フィルムキャリヤ配線体、２・・・・・
・可撓性透明フィルム、３・・・・・・有機接着剤層、
４・・・・・・ハンダ層、５・・・・・・配線層、７・
・・・・・外部接続用リードへ接続されるバンプ、８・
・・・・・電極へ接続されるバンプ、９・・・・・・電
極、１０・・・・・・半導体素子、２１・・・・・・収
容容器、２４・・・・・・外部接続用リード、２７・・
・・・・・・ンダ層。FIG. 1 is a diagram showing the structure of the film carrier wiring body of the present invention, FIG. 2 is a diagram showing how to temporarily attach the film carrier wiring body of FIG. 1 to a semiconductor element, and FIG. 3 is a diagram showing the structure of the film carrier wiring body of the present invention. 4 is a diagram showing the structure of a cerdip type container, and FIG. 5 is an overall diagram showing the mounting structure of the semiconductor element of the present invention. 1...°°film carrier wiring body, 2...
・Flexible transparent film, 3...organic adhesive layer,
4...Solder layer, 5...Wiring layer, 7.
...Bump connected to external connection lead, 8.
... Bump connected to electrode, 9 ... Electrode, 10 ... Semiconductor element, 21 ... Container, 24 ... External connection Lead for use, 27...
・・・・・・Nada layer.
Claims (1)
導体素子の裏面が固着され、且つ上記半導体素子周囲の
上記容器上に外部接続用リードが配設された半導体装置
の製法であって、可撓性フィルムと、該可撓性フィルム
に有機接着剤により接着され、該外部接続用リードと該
電極間を接続するための複数組の配線導体と、該配線導
体の両端に形成されたバンプとから成るフィルムキャリ
ヤ配線体を用意し、該配線導体の一方のバンプと該半導
体素子の電極とを接続して該半導体素子を該フィルムキ
ャリヤ配線体上に固定し、 該フィルムキャリヤ配線体を該収容容器上に移動し、該
配線導体の他方のバンプな該外部接続用リードに接続す
ると共に該半導体素子を該収容容器に固着し、 しかる後、該有機接着剤層を溶融して該可撓性フィルム
を除去し、該収容容器を封止する工程を有することを特
徴とする半導体装置の製法。[Scope of Claims] 1. A semiconductor in which the back surface of a semiconductor element having a plurality of electrodes on its main surface is fixed to an insulating housing container, and external connection leads are provided on the container around the semiconductor element. A method for manufacturing a device, comprising: a flexible film; a plurality of sets of wiring conductors bonded to the flexible film with an organic adhesive for connecting the external connection leads and the electrodes; and the wiring conductors. preparing a film carrier wiring body consisting of bumps formed on both ends of the wiring conductor, and fixing the semiconductor element on the film carrier wiring body by connecting one bump of the wiring conductor to an electrode of the semiconductor element; The film carrier wiring body is moved onto the container, and connected to the external connection lead, which is the other bump of the wiring conductor, and the semiconductor element is fixed to the container, and then the organic adhesive layer is A method for manufacturing a semiconductor device, comprising the steps of melting the flexible film, removing the flexible film, and sealing the container.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57122986A JPS5850021B2 (en) | 1982-07-16 | 1982-07-16 | Manufacturing method for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57122986A JPS5850021B2 (en) | 1982-07-16 | 1982-07-16 | Manufacturing method for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5825242A JPS5825242A (en) | 1983-02-15 |
| JPS5850021B2 true JPS5850021B2 (en) | 1983-11-08 |
Family
ID=14849459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57122986A Expired JPS5850021B2 (en) | 1982-07-16 | 1982-07-16 | Manufacturing method for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5850021B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61156051A (en) * | 1984-12-27 | 1986-07-15 | Daicel Chem Ind Ltd | Electrostatic recording material |
| US4876221A (en) * | 1988-05-03 | 1989-10-24 | Matsushita Electric Industrial Co., Ltd. | Bonding method |
| US5270260A (en) * | 1990-08-23 | 1993-12-14 | Siemens Aktiengesellschaft | Method and apparatus for connecting a semiconductor chip to a carrier system |
| US5620131A (en) * | 1995-06-15 | 1997-04-15 | Lucent Technologies Inc. | Method of solder bonding |
| US6404063B2 (en) | 1995-12-22 | 2002-06-11 | Micron Technology, Inc. | Die-to-insert permanent connection and method of forming |
| US5686318A (en) * | 1995-12-22 | 1997-11-11 | Micron Technology, Inc. | Method of forming a die-to-insert permanent connection |
| DE19840226B4 (en) * | 1998-09-03 | 2006-02-23 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method of applying a circuit chip to a carrier |
-
1982
- 1982-07-16 JP JP57122986A patent/JPS5850021B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5825242A (en) | 1983-02-15 |
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