JPS6155778B2 - - Google Patents
Info
- Publication number
- JPS6155778B2 JPS6155778B2 JP51142601A JP14260176A JPS6155778B2 JP S6155778 B2 JPS6155778 B2 JP S6155778B2 JP 51142601 A JP51142601 A JP 51142601A JP 14260176 A JP14260176 A JP 14260176A JP S6155778 B2 JPS6155778 B2 JP S6155778B2
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- semiconductor device
- low melting
- chip
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000000919 ceramic Substances 0.000 claims abstract description 25
- 239000011521 glass Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims description 22
- 238000002844 melting Methods 0.000 claims description 19
- 230000008018 melting Effects 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 238000007789 sealing Methods 0.000 abstract description 7
- 239000010931 gold Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910000676 Si alloy Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052839 forsterite Inorganic materials 0.000 description 2
- HCWCAKKEBCNQJP-UHFFFAOYSA-N magnesium orthosilicate Chemical compound [Mg+2].[Mg+2].[O-][Si]([O-])([O-])[O-] HCWCAKKEBCNQJP-UHFFFAOYSA-N 0.000 description 2
- -1 steatite Inorganic materials 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003472 neutralizing effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Abstract
Description
【発明の詳細な説明】
本発明は、低融点硝子を用いて封止する半導体
装置の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in semiconductor devices sealed using low melting point glass.
従来の低融点硝子封止型半導体装置の構造は、
半導体素子を塔載するセラミツク基板とセラミツ
クキヤツプとにはさまれたリードフレームが、低
融点硝子によつて封着されたもので、その内部空
間部のセラミツク基板上に半導体素子が固着さ
れ、金属細線によつて素子電極と内部リード先端
とが接続されたものである。 The structure of conventional low melting point glass sealed semiconductor devices is as follows:
A lead frame sandwiched between a ceramic substrate on which a semiconductor element is mounted and a ceramic cap is sealed with low melting point glass, and the semiconductor element is fixed on the ceramic substrate in the internal space, and the metal The element electrode and the tip of the internal lead are connected by a thin wire.
第１図は、従来の低融点硝子封止型半導体装置
のキヤツプ取り付け前の部分断面斜視図である。 FIG. 1 is a partially sectional perspective view of a conventional low melting point glass sealed semiconductor device before a cap is attached.
すなわち、アルミナやステアタイト、フオルス
テライト等のセラミツク基板１のほぼ中央の凹部
に、半導体素子２（以下チツプと称す）を接続す
る為の半導体素子固着部（以下アイランド部３と
呼ぶ）となるメタライズ層がAuペーストにより
つくられている。次にFe―Ni合金から成るリー
ドフレームの放射状に配置された内部リード６
は、アイランド部３の凹部周辺から基板１に重ね
合わされて、PbO―B2O3―ZnO系の低融点硝子５
によつて接着されている。 In other words, metallization is applied to a concave portion approximately in the center of a ceramic substrate 1 made of alumina, steatite, forsterite, etc., to serve as a semiconductor element fixing portion (hereinafter referred to as an island portion 3) for connecting a semiconductor element 2 (hereinafter referred to as a chip). The layer is made of Au paste. Next, the internal leads 6 arranged radially of the lead frame made of Fe-Ni alloy.
is superimposed on the substrate 1 from around the concave part of the island part 3, and a PbO-B 2 O 3 -ZnO-based low melting point glass 5
It is glued by.
又、内部リード６の先端にはアルミニウム又は
金が被着されている。 Further, the tips of the internal leads 6 are coated with aluminum or gold.
この様に構成された半導体用容器は、アイラン
ド部３にチツプ２を接着した後チツプ電極と内部
リード６の先端との間を金属細線で結線し、セラ
ミツクキヤツプ（図示せず）を低融点硝子を用い
て封止して使用するものである。 In the semiconductor container constructed in this way, after the chip 2 is bonded to the island portion 3, the chip electrode and the tip of the internal lead 6 are connected with a thin metal wire, and the ceramic cap (not shown) is attached to a low melting point glass. It is used by sealing it with.
第２図ａ〜ｄは、上述の従来の低融点硝子封止
型半導体装置の製造手順を示すものである。まず
ａは、セラミツク基板１をヒーターブロツク７の
上にのせ、450〜480℃に加熱して低融点硝子５を
軟化させ、次に個々の半導体装置用に切り離され
た個別リードフレーム１４を、前記軟化した硝子
５の上に位置合せして固着する。次にｂは、400
℃前後に加熱されたヒーターブロツク７上に載置
したセラミツク基板１のアイランド部３上にチツ
プ２をのせて摺動させ、AuペーストとSiチツプ
の間にAu―Si合金を生成させて接着させる。ｃ
の工程は、超音波ボンダーによつて内部リード６
の先端とチツプ２の電極とを金属細線８で結線す
る。ｄの工程は、低融点硝子５がグレーズされた
セラミツクキヤツプ９を封入治具（図示せず）に
セツトし、この治具をベルト炉に入れて封着する
ものである。この半導体装置の欠点は、リードフ
レームを個々に分離して基板に硝子で融着する構
造であるために、このリードフレームの取り付け
作業が短時間に大量にできないこと、次に基板へ
の半導体素子の固着及び金属細線によるチツプ電
極と内部リード先端との結線において自動機によ
る作業が難しい事、又キヤツプ封入作業の能率が
悪い事などが欠点となつていた。このため、リー
ドフレームを個々の半導体装置用に個別に切り離
すことなく複数個を連ねたままの状態で、自動機
を用いて半導体装置を組み立てる方法が行われて
いるが、この方法による半導体装置は、半導体素
子固着部がセラミツク基板上ではなくリードフレ
ームに形成されたアイランド部であるため、この
アイランド部が封止後に容器内で浮いた状態とな
つて半導体素子からの熱伝導が悪くなり、又振動
等に対しても強度的に不安定なものであつた。 FIGS. 2a to 2d show the manufacturing procedure of the above-mentioned conventional low melting point glass sealed semiconductor device. First, in step a, the ceramic substrate 1 is placed on the heater block 7 and heated to 450 to 480°C to soften the low melting point glass 5, and then the individual lead frames 14 cut out for individual semiconductor devices are It is aligned and fixed onto the softened glass 5. Then b is 400
The chip 2 is placed on the island portion 3 of the ceramic substrate 1 placed on the heater block 7 which is heated to around 10°C and is slid to form an Au--Si alloy between the Au paste and the Si chip and bond them together. . c.
The process is to connect the internal lead 6 using an ultrasonic bonder.
The tip of the chip 2 and the electrode of the chip 2 are connected with a thin metal wire 8. In step d, the ceramic cap 9 glazed with the low melting point glass 5 is set in a sealing jig (not shown), and the jig is placed in a belt furnace for sealing. The disadvantage of this semiconductor device is that the lead frames are separated individually and fused to the substrate with glass, so it is not possible to attach a large number of lead frames in a short period of time. The disadvantages were that it was difficult to use automatic machines to connect the chip electrodes and the tips of the internal leads using thin metal wires, and that the efficiency of the cap-sealing process was low. For this reason, there is a method of assembling semiconductor devices using an automatic machine without separating the lead frames individually for each semiconductor device. Since the semiconductor element fixing part is an island part formed on the lead frame rather than on the ceramic substrate, this island part floats in the container after sealing, resulting in poor heat conduction from the semiconductor element. It was also unstable in terms of strength against vibrations and the like.
本発明は、これらの欠点を除去し、一連のリー
ドフレームを用いてセラミツク容器で硝子封止し
てなる半導体装置を提供するものである。 The present invention eliminates these drawbacks and provides a semiconductor device that uses a series of lead frames and is sealed with glass in a ceramic container.
次に、本発明について図面を用いて説明する。
第３図は本発明に用いるリードフレームの基板へ
の取り付け状態を示す平面図、又第４図〜第７図
は本発明の半導体装置の実施例を示すもので、第
１の実施例を第４図の部分断面斜視図と第５図の
断面図に示す。まず、第３図に示す本発明に使用
するリードフレーム１４′は、アイランド部３′が
タイバー１３に連結され、又４は外部リード、６
は内部リードである。このアイランド部３′の連
結のされ方は任意のリードでもよい。この一連の
リードフレーム１４′はエツチング又は打抜きに
より成形される。次に第４図および第５図のよう
にアルミナ、ステアタイト、フオルステライト等
のセラミツク基板１のほぼ中央に、頂面が平面状
の突起１０を設け、この突起の周囲の基板一面に
PbO―B2O3―ZnO系低融点硝子５をグレーズす
る。 Next, the present invention will be explained using the drawings.
FIG. 3 is a plan view showing how the lead frame used in the present invention is attached to the substrate, and FIGS. 4 to 7 show embodiments of the semiconductor device of the present invention. This is shown in a partially sectional perspective view in FIG. 4 and a sectional view in FIG. First, in the lead frame 14' used in the present invention shown in FIG. 3, the island portion 3' is connected to the tie bar 13, 4 is an external lead,
is an internal read. The island portion 3' may be connected by any lead. This series of lead frames 14' is formed by etching or stamping. Next, as shown in FIGS. 4 and 5, a projection 10 with a flat top surface is provided approximately at the center of the ceramic substrate 1 made of alumina, steatite, forsterite, etc., and the entire surface of the substrate around this projection is
PbO-B 2 O 3 -ZnO-based low melting point glass 5 is glazed.
突起１０はアイランド部３′が浮いた状態にな
るのを支えるために設けられたもので、アイラン
ド部３′と突起１０の頂面との間には熱伝導性ペ
ースト１２を介在させてチツプからの熱放散をよ
くしている。 The protrusion 10 is provided to support the island part 3' in a floating state, and a thermally conductive paste 12 is interposed between the island part 3' and the top surface of the protrusion 10 to remove the chip. It has good heat dissipation.
突起１０の周囲のグレーズ面には基板外部に向
け放射状に内部リード６および外部リード４が固
着されている。アイランド部３′にはAuメツキを
１〜２μｍ施し、内部リード６の先端にはAuメ
ツキ又はAl被膜が数μｍ施されている。アイラ
ンド部３′上にはチツプ２がAu―Si合金層を介し
て接着されており、又チツプ２の電極と内部リー
ド６の先端との間はアルミニウム又は金の金属細
線８によつて結線されており、これらの上にセラ
ミツクキヤツプ（図示せず）を被せて低融点硝子
により封着するものである。又外部リード４の表
面にはSnメツキが３〜５μｍの厚さに施されて
防錆及びソケツト差しの時の接触抵抗を低くする
役目をしている。 Internal leads 6 and external leads 4 are fixed to the glazed surface around the protrusion 10 in a radial direction toward the outside of the substrate. The island portion 3' is plated with Au to a thickness of 1 to 2 μm, and the tips of the internal leads 6 are plated with Au or coated with Al to a thickness of several μm. A chip 2 is bonded onto the island portion 3' via an Au--Si alloy layer, and the electrodes of the chip 2 and the tips of the internal leads 6 are connected by thin metal wires 8 of aluminum or gold. A ceramic cap (not shown) is placed over these and sealed with low melting point glass. Furthermore, the surface of the external lead 4 is coated with Sn plating to a thickness of 3 to 5 .mu.m to prevent rust and to reduce contact resistance when inserting into a socket.
第２の実施例は第６図の断面図に示す如く、ア
イランド部３′の位置が内部リード６の先端位置
よりも低位置になるように折り曲げられたリード
フレームを用い、前述した材質のセラミツク基板
１のほぼ中央にアイランド部３′が収容できる大
きさの凹部１１を設け、凹部１１の底部には良好
なる熱伝導性ペースト１２、例えば低融点硝子に
AgやCuなどの微粒子を混入したペーストにてア
イランド部３′を接着し、チツプ２から発生する
熱をセラミツク基板１の外部に放散する構造であ
る。チツプの接着、金属細線の結線、セラミツク
キヤツプ９の封入は前記と同じである。 The second embodiment, as shown in the cross-sectional view of FIG. A recess 11 large enough to accommodate the island portion 3' is provided approximately in the center of the substrate 1, and the bottom of the recess 11 is filled with a good thermally conductive paste 12, such as low melting point glass.
The structure is such that the island portion 3' is bonded with a paste containing fine particles such as Ag or Cu, and the heat generated from the chip 2 is dissipated to the outside of the ceramic substrate 1. The adhesion of the chip, the connection of the thin metal wires, and the sealing of the ceramic cap 9 are the same as described above.
第３の実施例は、第７図の断面図に示す如く、
内部リード６の先端がアイランド部３′よりも高
い位置に配置されてチツプ２の電極と内部リード
６の先端とのボンデイング作業性の向上および歩
留りを改良したものである。 The third embodiment, as shown in the cross-sectional view of FIG.
The tips of the internal leads 6 are arranged at a higher position than the island portion 3', thereby improving the workability and yield of bonding between the electrodes of the chip 2 and the tips of the internal leads 6.
次に本発明による半導体装置の製造の手順につ
いて、第８図ａ〜ｄの図面を用いて説明する。 Next, the procedure for manufacturing a semiconductor device according to the present invention will be explained using the drawings of FIGS. 8a to 8d.
ａの工程において、まず第３図に示す如く個々
のリードフレームを５〜10個連結した一連のリー
ドフレーム１４′を400℃位の温度のヒーターブロ
ツク７上にセツトする。次にアイランド部３′に
施されたAuメツキ上にSiチツプ２を摺動圧着さ
せるとAu―Si合金が生成し、アイランド部３′に
チツプ２が強固に固着される。ｂの工程におい
て、内部リード先端とチツプ電極とをアルミニウ
ム又は金の金属細線８で超音波ボンダー又は熱圧
着ボンダーにより結線する。ｃの工程において、
低融点硝子５および熱伝導性ペースト１２が付着
された５〜10個のセラミツク基板１′およびこれ
らの基板に対応する低融点硝子５が付着されたセ
ラミツクキヤツプ９が装着できる封入治具１５に
該基板１とリードフレーム１４′を装着し、300〜
350℃で予熱した後にセラミツクキヤツプ９をリ
ードフレーム１４′上にのせて450〜500℃に調節
された中性又は酸化性雰囲気に通す。その結果ｄ
の如くセラミツク基板１及びセラミツクキヤツプ
９にグレーズされた低融点硝子５が軟化溶融して
リードフレーム１４′をはさんで基板とキヤツプ
が封着される。次にこのものにSnメツキ処理、
リード切断、リード折り曲げを施すと気密封止さ
れた低融点硝子封止型半導体装置が得られる。 In step a, first, as shown in FIG. 3, a series of lead frames 14' in which 5 to 10 individual lead frames are connected is set on the heater block 7 at a temperature of about 400 DEG C. Next, when the Si chip 2 is slid and crimped onto the Au plating applied to the island portion 3', an Au--Si alloy is generated, and the chip 2 is firmly fixed to the island portion 3'. In step b, the tips of the internal leads and the chip electrodes are connected with thin metal wires 8 of aluminum or gold using an ultrasonic bonder or a thermocompression bonder. In step c,
5 to 10 ceramic substrates 1' to which low melting point glass 5 and thermally conductive paste 12 are attached, and ceramic caps 9 to which low melting point glasses 5 corresponding to these substrates are attached are attached to an enclosure jig 15. Attach the board 1 and lead frame 14', and
After preheating at 350°C, the ceramic cap 9 is placed on the lead frame 14' and passed through a neutral or oxidizing atmosphere adjusted to 450-500°C. The result d
As shown, the low melting point glass 5 glazed on the ceramic substrate 1 and the ceramic cap 9 is softened and melted to seal the substrate and the cap with the lead frame 14' in between. Next, apply Sn plating to this item.
By cutting the leads and bending the leads, a hermetically sealed low melting point glass sealed semiconductor device is obtained.
以上述べたように、本発明の半導体装置は、
個々のリードフレームが複数個連結された状態で
製造できるので自動機が非常に使り易くなり、従
来の個別のリードフレーム取り付け工程を除去で
き、又アイランド部を外部リードと一体に成形す
るようにすれば、金属細線で従来のように基板上
のアイランド部と内部リードとを接続する必要も
なくなり、大幅な原価低減が可能となるものであ
る。 As described above, the semiconductor device of the present invention has
Since multiple individual lead frames can be manufactured in a connected state, automatic machines are much easier to use, the conventional individual lead frame attachment process can be eliminated, and the island part can be molded integrally with the external leads. This eliminates the need to connect the island portion on the board and the internal leads using thin metal wires, as in the conventional method, making it possible to significantly reduce costs.
第１図は従来の半導体装置の部分断面斜視図、
第２図ａ〜ｄはその製造方法の工程図、第３図は
本発明に用いるリードフレームの基板への取り付
け状態を示す平面図、第４図及び第５図は本発明
の半導体装置の一実施例を示す部分断面斜視図と
その断面図、第６図、第７図は本発明の第２、第
３の実施例を示す断面図、第８図ａ〜ｄは本発明
の半導体装置の製造方法工程図である。
１…セラミツク基板、２…半導体素子、３…ア
イランド部、４…外部リード、５…低融点硝子、
６…内部リード、７…ヒーターブロツク、８…金
属細線、９…セラミツクキヤツプ、１０…突起、
１１…凹部、１２…熱伝導性ペースト、１３…タ
イバー、１４…リードフレーム、１５…封入治
具。
FIG. 1 is a partial cross-sectional perspective view of a conventional semiconductor device.
Figures 2 a to d are process diagrams of the manufacturing method, Figure 3 is a plan view showing how the lead frame used in the present invention is attached to the substrate, and Figures 4 and 5 are part of the semiconductor device of the present invention. 6 and 7 are sectional views showing the second and third embodiments of the present invention, and FIGS. 8a to 8d are views of the semiconductor device of the present invention. It is a manufacturing method process diagram. DESCRIPTION OF SYMBOLS 1...Ceramic substrate, 2...Semiconductor element, 3...Island part, 4...External lead, 5...Low melting point glass,
6...Internal lead, 7...Heater block, 8...Metal thin wire, 9...Ceramic cap, 10...Protrusion,
DESCRIPTION OF SYMBOLS 11... Recessed part, 12... Heat conductive paste, 13... Tie bar, 14... Lead frame, 15... Enclosing jig.
Claims (1)
素子と内部リードとが金属細線で接続されている
リードフレームを、セラミツク基板とセラミツク
キヤツプではさんで低融点ガラスで一体に封止す
る構造の半導体装置において、前記アイランド部
とセラミツク基板との間には前記低融点ガラスよ
り熱伝導性の良い接着剤が充填されていることを
特徴とする半導体装置。1. In a semiconductor device having a structure in which a lead frame in which a semiconductor element is fixed to an island part, and this element and internal leads are connected by thin metal wires, is sandwiched between a ceramic substrate and a ceramic cap and integrally sealed with low-melting glass. . A semiconductor device, wherein an adhesive having better thermal conductivity than the low melting point glass is filled between the island portion and the ceramic substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14260176A JPS5367358A (en) | 1976-11-27 | 1976-11-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14260176A JPS5367358A (en) | 1976-11-27 | 1976-11-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5367358A JPS5367358A (en) | 1978-06-15 |
| JPS6155778B2 true JPS6155778B2 (en) | 1986-11-29 |
Family
ID=15319093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14260176A Granted JPS5367358A (en) | 1976-11-27 | 1976-11-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5367358A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60190043U (en) * | 1984-05-25 | 1985-12-16 | 関西日本電気株式会社 | flat package |
| US4801996A (en) * | 1987-10-14 | 1989-01-31 | Hewlett-Packard Company | Gigahertz rate integrated circuit package incorporating semiconductive MIS power-line substrate |
-
1976
- 1976-11-27 JP JP14260176A patent/JPS5367358A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5367358A (en) | 1978-06-15 |
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