JPH0525182B2 - - Google Patents
Info
- Publication number
- JPH0525182B2 JPH0525182B2 JP13717584A JP13717584A JPH0525182B2 JP H0525182 B2 JPH0525182 B2 JP H0525182B2 JP 13717584 A JP13717584 A JP 13717584A JP 13717584 A JP13717584 A JP 13717584A JP H0525182 B2 JPH0525182 B2 JP H0525182B2
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- substrate
- semiconductor device
- adhesion
- sealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 56
- 229910052751 metal Inorganic materials 0.000 claims description 41
- 239000002184 metal Substances 0.000 claims description 41
- 238000007789 sealing Methods 0.000 claims description 38
- 239000000853 adhesive Substances 0.000 claims description 34
- 230000001070 adhesive effect Effects 0.000 claims description 34
- 239000004065 semiconductor Substances 0.000 claims description 23
- 229910000679 solder Inorganic materials 0.000 claims description 14
- 238000002844 melting Methods 0.000 claims description 10
- 230000008018 melting Effects 0.000 claims description 10
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910052790 beryllium Inorganic materials 0.000 description 2
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】
［技術分野］
本発明は、半導体装置に係り、特に、複数の半
導体ペレツト（以下、チツプという）を塔載した
塔載用基板を、封止用基板と封止用キヤツプとで
封止してなる半導体装置に適用して有効な技術に
関するものである。[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor device, and in particular, a mounting substrate on which a plurality of semiconductor pellets (hereinafter referred to as chips) are mounted is connected to a sealing substrate and a sealing substrate. The present invention relates to a technique that is effective when applied to a semiconductor device sealed with a cap.
［背景技術］
半導体装置の実装法の一つに、高密度実装化を
図るために、複数個のチツプを半田電極を介して
塔載用基板に塔載し、封止用基板と封止用キヤツ
プとで封止してなる構成が知られている（例え
ば、特開昭54−73564号公報参照）。塔載用基板
は、ICの動作による熱応力ひずみを緩和するた
めに同一材料の単結晶シリコンによつて形成され
ている。[Background technology] One of the mounting methods for semiconductor devices is to mount a plurality of chips on a mounting board via solder electrodes in order to achieve high-density packaging. A structure in which the cap is sealed with a cap is known (see, for example, Japanese Patent Laid-Open No. 73564/1983). The mounting substrate is made of the same material, single-crystal silicon, in order to alleviate thermal stress and strain caused by the operation of the IC.
本発明者等は先に、前記塔載用基板を固着する
封止用基板（パツケージのベース）として、熱応
力ひずみの緩和と熱放出効果に優れている少量ベ
リリウムを含む炭化シリコン焼結体からなる基板
を用いることを提案した。 The present inventors first developed a silicon carbide sintered body containing a small amount of beryllium, which has excellent thermal stress relaxation and heat dissipation effects, as a sealing substrate (base of the package) to which the tower mounting substrate is fixed. We proposed the use of a substrate of
そして、本発明者はさらに、上述の技術におい
て、塔載用基板を封止用基板に固着する手段とし
て、それぞれの接合面に設けられたチツプの発生
する熱を効率よく放出できる金属と、該両者の金
層を半田電極よりも低融点を有する金とスズとの
合金層とを用いることを検討した。 Further, in the above-mentioned technique, the present inventor further proposed that, as a means for fixing the mounting substrate to the sealing substrate, a metal capable of efficiently releasing heat generated by chips provided on each joint surface, We considered using an alloy layer of gold and tin, which has a lower melting point than the solder electrode, as both gold layers.
その検討の結果、本発明者は、以下の述べる問
題点を見い出した。 As a result of the study, the present inventor discovered the following problems.
(1) 超音波振動を用い前記合金層で両者の金層を
接着する際に、塔載用基板、封止用基板と金層
との被着性が悪く剥離を生じるので、チツプが
発生する熱を効率よく封止用基板に伝達するこ
とができない。(1) When bonding both gold layers with the alloy layer using ultrasonic vibration, the adhesion between the tower mounting substrate, the sealing substrate and the gold layer is poor and peeling occurs, resulting in chips. Heat cannot be efficiently transferred to the sealing substrate.
(2) 金層と合金層とに比べて塔載用基板、封止用
基板と金層との被着性が悪いので剥離を生じ、
かつ、塔載用基板、封止用基板と合金層との熱
膨張率が異なるので、前記剥離部からクラツク
を生じる。(2) The adhesion of the mounting substrate and sealing substrate to the gold layer is poorer than that of the gold layer and the alloy layer, resulting in peeling.
Moreover, since the thermal expansion coefficients of the mounting substrate, the sealing substrate and the alloy layer are different, cracks occur from the peeled portion.
(3)前記(1)及び(2)のために、半導体装置の電気的
信頼性等の低下を生じる。 (3) Due to the above (1) and (2), the electrical reliability of the semiconductor device is reduced.
［発明の目的］
本発明の目的は、半導体装置の電気的信頼性を
向上することが可能な技術手段を提供することに
ある。[Object of the Invention] An object of the present invention is to provide technical means that can improve the electrical reliability of a semiconductor device.
本発明の前記ならびにその他の目的と新規な特
徴は、本明細書の記述及び添付図面によつて明ら
かになるであろう。 The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
［発明の概要］
本願において開示される発明のうち、代表的な
ものの概要を簡単に説明すれば、下記のとおりで
ある。[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.
すなわち、塔載用基板と封止用基板との接合面
に、それぞれとの被着性が良好で、かつ、熱伝導
が良好な接着用金属層を設け、該両者を半田電極
よりも低融点を有し、かつ、前記基板との熱膨張
率差が小さい接着用金属層で接合することによつ
て、チツプが発生する熱を効率よく封止用基板に
伝達することができ、かつ、剥離によるクラツク
を生じることがなくなるので、半導体装置の電気
的信頼性を向上することができる。 That is, an adhesive metal layer with good adhesion to each and good thermal conductivity is provided on the bonding surfaces of the mounting substrate and the sealing substrate, and both are bonded to a metal layer with a melting point lower than that of the solder electrode. By bonding with an adhesive metal layer that has a small coefficient of thermal expansion and has a small difference in coefficient of thermal expansion from the substrate, the heat generated by the chip can be efficiently transferred to the sealing substrate, and the chip can be easily peeled off. Therefore, the electrical reliability of the semiconductor device can be improved.
以下、本発明の構成について、実施例とともに
説明する。 Hereinafter, the configuration of the present invention will be explained along with examples.
［実施例］
第１図は、本発明の実施例の構造を説明するた
めの半導体装置の平面図、第２図は、第１図の
−切断線における断面図、第３図は、第２図の
要部を示す断面図である。第１図は、その図面を
見易くするために、塔載用基板上部に設けられる
導電層、絶縁膜及び封止用キヤツプは図示しな
い。[Example] FIG. 1 is a plan view of a semiconductor device for explaining the structure of an example of the present invention, FIG. 2 is a sectional view taken along the - cutting line in FIG. 1, and FIG. FIG. 3 is a sectional view showing the main part of the figure. In FIG. 1, in order to make the drawing easier to read, a conductive layer, an insulating film, and a sealing cap provided on the top of the mounting substrate are not shown.
なお、実施例の全図において、同一機能を有す
るものは同一符号を付け、そのくり返しの説明は
省略する。 In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.
第１図乃至第３図において、１は特開昭57−
2591号に示されている0.1〜3.5［重量％］のベリ
リウムを含む炭化シリコン焼結体からなる封止用
基板であり、塔載用基板を配置し封止するための
ものである。 In Figures 1 to 3, 1 is JP-A-57-
This is a sealing substrate made of a silicon carbide sintered body containing 0.1 to 3.5 [wt%] beryllium as shown in No. 2591, and is used for arranging and sealing a tower mounting substrate.
２は封止用基板１周辺部に設けられたガラス等
からなる絶縁性接着剤、３は絶縁性接着剤２を介
して複数本設けられたリードである。リード３の
外部リード３Ａは、耐腐蝕性を向上するために、
半田メツキが施されている。 2 is an insulating adhesive made of glass or the like provided around the sealing substrate 1, and 3 is a plurality of leads provided through the insulating adhesive 2. The external lead 3A of the lead 3 is made of
Solder plating has been applied.
４は接着用金属層５を介して封止用基板１に設
けられた単結晶シリコンからなる塔載用基板であ
り、半田電極６を介して複数のチツプ７を塔載
し、半導体装置の実装密度を向上するためのもの
である。 Reference numeral 4 denotes a mounting substrate made of single crystal silicon that is provided on the sealing substrate 1 via an adhesive metal layer 5, on which a plurality of chips 7 are mounted via solder electrodes 6, and is used for mounting semiconductor devices. This is to improve density.
接着用金属層５は、封止用基板１、塔載用基板
４の接合面に設けられたそれぞれとの被着性が良
好でかつ熱伝導が良好な接着用金属層５Ａ，５Ｅ
と、これに被着してそれぞれ設けられた接着用金
属層５Ａ，５Ｅとの被着性が良好でかつ熱伝導が
良好な接着用金属層５Ｂ，５Ｄと、それらと接合
して設けられた接着用金属層５Ｂ，５Ｄとの被着
性が良好でかつ熱伝導が良好な接着用金属層５Ｃ
とによつて構成されている。 The adhesive metal layer 5 is made of adhesive metal layers 5A and 5E that have good adhesion to the bonding surfaces of the sealing substrate 1 and tower mounting substrate 4, respectively, and have good thermal conductivity.
and adhesion metal layers 5B and 5D which have good adhesion to the adhesion metal layers 5A and 5E provided thereon and have good thermal conductivity, and are bonded thereto. Adhesive metal layer 5C that has good adhesion to adhesive metal layers 5B and 5D and has good thermal conductivity
It is composed of:
接着用金属層５Ｃとしては、超音波振動によつ
て封止用基板１と塔載用基板４とを接合する工程
すなわち接着用金属層５Ｂ，５Ｄとの接合に際
し、半田電極６が不要に融解するのを防止するた
めに、低融点の材料が用いられている。さらに、
接着用金属層５Ｃは、封止用基板１、塔載用基板
４との熱膨張率が小さいもので構成されている。 As for the adhesive metal layer 5C, the solder electrode 6 is melted unnecessarily during the process of joining the sealing substrate 1 and tower mounting substrate 4 by ultrasonic vibration, that is, when joining the adhesive metal layers 5B and 5D. To prevent this, materials with low melting points are used. moreover,
The adhesive metal layer 5C is made of a material having a small coefficient of thermal expansion with respect to the sealing substrate 1 and the mounting substrate 4.
また、半田電極６は、塔載用基板４側に設けら
れる半田電極６Ａと、チツプ７側に設けられる半
田電極６Ｂとによつて構成されている。 Further, the solder electrode 6 is composed of a solder electrode 6A provided on the mounting substrate 4 side and a solder electrode 6B provided on the chip 7 side.
８は塔載用基板４周辺部に設けられた外部端
子、９は外部端子８とリード３とを電気的に接続
するボンデイングワイヤである。 8 is an external terminal provided around the mounting board 4, and 9 is a bonding wire that electrically connects the external terminal 8 and the lead 3.
１１は絶縁性接着剤１０を介してリード３上部
を覆うように設けられた封止壁、１３は絶縁性接
着剤１２を介して設けられた封止用キヤツプであ
る。キヤツプ１３は、放熱性の良いアルミニウム
又は封止用基板１と同一材料からなる。 11 is a sealing wall provided to cover the upper part of the lead 3 via an insulating adhesive 10, and 13 is a sealing cap provided via an insulating adhesive 12. The cap 13 is made of aluminum with good heat dissipation or the same material as the sealing substrate 1.
次に、本実施例の製造方法について説明する。 Next, the manufacturing method of this example will be explained.
第４図乃至第８図は、本発明の実施例の製造方
法を説明するための図であり、第４図は、所定の
製造工程における塔載用基板の要部断面図、第５
図乃至第８図は、各製造工程における半導体装置
の断面図である。 4 to 8 are diagrams for explaining the manufacturing method of the embodiment of the present invention, and FIG.
8 are cross-sectional views of the semiconductor device in each manufacturing process.
まず、塔載用基板４の接合面に、接着用金属層
５Ｅ，５Ｄを順次積層する。この後、第４図に示
すように、半田電極６を介して、塔載用基板４に
複数のチツプ７を塔載する。 First, the adhesive metal layers 5E and 5D are sequentially laminated on the joint surface of the mounting substrate 4. Thereafter, as shown in FIG. 4, a plurality of chips 7 are mounted on the mounting substrate 4 via the solder electrodes 6.
第４図に示す工程を併せて、塔載用基板４を配
置する封止用基板１の接合面に、接着用金属層５
Ａ，５Ｂを順次積層する。この後、封止用基板１
の周辺部に絶縁性接着剤２を介してリード形成部
材３Ｂを形成し、第５図に示すように、絶縁性接
着剤１０を介して封止壁１１を形成する。 In addition to the process shown in FIG.
A and 5B are stacked one after another. After this, the sealing substrate 1
A lead forming member 3B is formed on the periphery of the lead forming member 3B via an insulating adhesive 2, and a sealing wall 11 is formed via an insulating adhesive 10, as shown in FIG.
接着用金属層５Ａ，５Ｅは、例えば、チタン、
タングステン等の高融点金属層で形成し、その膜
厚を2000〜3000［オングストローム（以下、］Ａ
［という）］程度にすればよい。 The adhesive metal layers 5A and 5E are made of, for example, titanium,
It is formed of a high melting point metal layer such as tungsten, and the film thickness is 2000 to 3000 [angstroms (hereinafter referred to as] A).
It should be about [that].
接着用金属層５Ｂ，５Ｄは、例えば、アルミニ
ウム層で形成し、接着用金属層５Ｂはその膜厚を
１〜２［μm］程度、接着用金属層５Ｄはその膜厚
を4000〜5000［Ａ］程度にすればよい。 The adhesive metal layers 5B and 5D are formed of, for example, an aluminum layer, and the adhesive metal layer 5B has a thickness of about 1 to 2 μm, and the adhesive metal layer 5D has a thickness of 4000 to 5000 μm. ] should be enough.
第４図及び第５図に示す工程の後に、第６図に
示すように、接着用金属層５Ｃを介して塔載用基
板４を封止用基板１に配置する。接着用金属層５
Ｃは、半田電極６よりも低融点（350［℃］程度以
下）となるように、例えば、アルミニウムとスズ
との合金層で形成し、その膜厚を50［μm］程度で
形成すればよい。そして、接着用金属層５Ｃは、
接着用金属層５Ｂ，５Ｄと、超音波振動によるス
クラブ技術により被着すればよい。 After the steps shown in FIGS. 4 and 5, as shown in FIG. 6, the mounting substrate 4 is placed on the sealing substrate 1 via the adhesive metal layer 5C. Adhesive metal layer 5
C may be formed of an alloy layer of aluminum and tin, for example, so that it has a lower melting point than the solder electrode 6 (approximately 350 [°C] or less), and the film thickness may be approximately 50 [μm]. . The adhesive metal layer 5C is
The adhesive metal layers 5B and 5D may be adhered by a scrub technique using ultrasonic vibration.
第６図に示す工程の後に、外部端子８とリード
３とを電気的に接続するボンデイングワイヤ９を
形成する。そして、第７図に示すように、絶縁性
接着剤１２を介して封止用キヤツプ１３を形成す
る。 After the process shown in FIG. 6, bonding wires 9 for electrically connecting external terminals 8 and leads 3 are formed. Then, as shown in FIG. 7, a sealing cap 13 is formed via an insulating adhesive 12.
第７図に示す工程の後に、リード形成部材３Ｂ
を成形してリード３を形成し、第８図に示すよう
に、外部のリード３に半田メツキを施すことによ
り、外部リード３Ａを形成する。 After the step shown in FIG. 7, the lead forming member 3B
The leads 3 are formed by molding, and as shown in FIG. 8, the external leads 3 are soldered to form external leads 3A.
これら一連の製造工程により、本実施例の半導
体装置は完成する。 Through these series of manufacturing steps, the semiconductor device of this example is completed.
［効 果］
以上説明したように、本願において開示された
新規な技術手段によれば、以下に述べるような効
果を得ることができる。[Effects] As explained above, according to the novel technical means disclosed in the present application, the following effects can be obtained.
(1) 塔載用基板と封止用基板との接合面に、それ
ぞれとの被着性が良好で、かつ、熱伝導が良好
な接着用金属層を設け、該両者を半田電極より
も低融点を有し、かつ、前記基板との熱膨張率
差が小さい接着用金属層で接合することによつ
て、塔載用基板、封止用基板と接着用金属層と
の剥離を生じることがないので、チツプが発生
する熱を効率よく封止用基板に伝達することが
できる。(1) An adhesive metal layer with good adhesion to each and good thermal conductivity is provided on the bonding surfaces of the tower mounting board and the sealing board, and both are bonded at a temperature lower than that of the solder electrode. By bonding with an adhesive metal layer that has a melting point and a small difference in coefficient of thermal expansion with the substrate, peeling between the tower mounting substrate, the sealing substrate, and the adhesive metal layer may not occur. Therefore, the heat generated by the chip can be efficiently transferred to the sealing substrate.
(2) 前記(1)により、塔載用基板、封止用基板と接
着用金属層との剥離を生じることがないので、
前記基板のクラツクの発生を防止することがで
きる。(2) Due to (1) above, there is no possibility of separation between the mounting substrate, the sealing substrate, and the adhesive metal layer.
It is possible to prevent the occurrence of cracks in the substrate.
(3) 前記(1)及び(2)により、半導体装置の電気的信
頼性を向上することができる。(3) According to (1) and (2) above, the electrical reliability of the semiconductor device can be improved.
以上、本発明者によつてなされた発明を実施例
にもとずき具体的に説明したが、本発明は、前記
実施例に限定されるものではなく、その要旨を逸
脱しない範囲において、種々変形し得ることは勿
論である。 As above, the invention made by the present inventor has been specifically explained based on Examples. However, the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist thereof. Of course, it can be modified.
例えば、前記実施例は、本発明を複数個のチツ
プを塔載した塔載用基板を封止してなる半導体装
置に適用した例について説明したが、１つのチツ
プを塔載した塔載用基板を封止してなる半導体装
置に適用してもよい。 For example, in the above embodiment, the present invention was applied to a semiconductor device formed by sealing a mounting substrate on which a plurality of chips were mounted, but a mounting substrate on which one chip was mounted was applied to a semiconductor device. It may be applied to a semiconductor device formed by sealing.
第１図は、本発明の実施例の構造を説明するた
めの半導体装置の平面図、第２図は、第１図の
−切断線における断面図、第３図は、第２図の
要部を示す断面図、第４図乃至第８図は、本発明
の製造方法を説明するための図であり、第４図
は、所定の製造工程における塔載用基板の要部断
面図、第５図乃至第８図は、各製造工程における
半導体装置の断面図である。
図中、１…封止用基板、２，１０，１２…絶縁
性接着剤、３…リード、３Ａ…外部リード、３Ｂ
…リード形成部材、４…塔載用基板、５，５Ａ，
５Ｂ，５Ｃ，５Ｄ，５Ｅ…接着用金属層、６，６
Ａ，６Ｂ…半田電極、７…チツプ、８…外部端
子、９…ボンデイングワイヤ、１１…封止壁、１
３…封止用キヤツプである。
1 is a plan view of a semiconductor device for explaining the structure of an embodiment of the present invention, FIG. 2 is a sectional view taken along the - cutting line in FIG. 1, and FIG. 3 is a main part of FIG. 2. FIGS. 4 to 8 are diagrams for explaining the manufacturing method of the present invention, and FIG. 8 are cross-sectional views of the semiconductor device in each manufacturing process. In the figure, 1... Sealing substrate, 2, 10, 12... Insulating adhesive, 3... Lead, 3A... External lead, 3B
...Lead forming member, 4...Tower mounting board, 5,5A,
5B, 5C, 5D, 5E...adhesive metal layer, 6, 6
A, 6B... Solder electrode, 7... Chip, 8... External terminal, 9... Bonding wire, 11... Sealing wall, 1
3...Sealing cap.
Claims (1)
属層によつて搭載した搭載用基板を、封止用基板
と封止用キヤツプとで封止してなる半導体装置で
あつて、前記塔載用基板と封止用基板との接合面
に、それぞれとの被着性が良好で、かつ、熱伝導
が良好な接着用第２金属層を設け、該両者を前記
接着用第１金属層よりも低融点を有し、かつ、前
記基板との熱膨張率差が小さい接着用第３金属層
で接合したことを特徴とする半導体装置。 ２ 前記接着用第１金属層は、半田によつて形成
され、前記接着用第２金属層は、塔載用基板と封
止用基板とのそれぞれの接合面に被着して設けら
れた高融点金属層と、該高融点金属層上部に被着
して設けられたアルミニウム層とによつて形成さ
れ、前記接着用第３金属層は、それぞれの第２の
金属層に被着して設けられたアルミニウムとスズ
との合金層によつて形成されてなることを特徴と
する特許請求の範囲第１項記載の半導体装置。 ３ 前記接着用第２金属層の高融点金属層は、チ
タン、タングステン等からなつていることを特徴
とする特許請求の範囲第２項記載の半導体装置。[Scope of Claims] 1. A semiconductor device in which a mounting substrate on which a plurality of semiconductor integrated circuit devices are mounted by a first metal layer for adhesion is sealed with a sealing substrate and a sealing cap. A second metal layer for adhesion having good adhesion to each and good thermal conductivity is provided on the bonding surface of the tower mounting substrate and the sealing substrate, and the two are bonded together. A semiconductor device, characterized in that the third metal layer for adhesion has a lower melting point than the first metal layer for bonding, and has a smaller difference in coefficient of thermal expansion from the substrate. 2. The first metal layer for adhesion is formed of solder, and the second metal layer for adhesion is formed of a height provided on the bonding surfaces of the mounting substrate and the sealing substrate. It is formed of a melting point metal layer and an aluminum layer deposited on top of the high melting point metal layer, and the third adhesive metal layer is deposited on each of the second metal layers. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed of an alloy layer of aluminum and tin. 3. The semiconductor device according to claim 2, wherein the high melting point metal layer of the second adhesive metal layer is made of titanium, tungsten, or the like.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13717584A JPS6118157A (en) | 1984-07-04 | 1984-07-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13717584A JPS6118157A (en) | 1984-07-04 | 1984-07-04 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6118157A JPS6118157A (en) | 1986-01-27 |
| JPH0525182B2 true JPH0525182B2 (en) | 1993-04-12 |
Family
ID=15192564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13717584A Granted JPS6118157A (en) | 1984-07-04 | 1984-07-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6118157A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0732867A (en) * | 1993-07-19 | 1995-02-03 | Showa Alum Corp | Heat exchanger |
| JPH07190668A (en) * | 1993-12-28 | 1995-07-28 | Showa Alum Corp | Heat exchanger |
-
1984
- 1984-07-04 JP JP13717584A patent/JPS6118157A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0732867A (en) * | 1993-07-19 | 1995-02-03 | Showa Alum Corp | Heat exchanger |
| JPH07190668A (en) * | 1993-12-28 | 1995-07-28 | Showa Alum Corp | Heat exchanger |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6118157A (en) | 1986-01-27 |
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