JP2707984B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a chip and a sealing cap for sealing the chip.

[0002]

2. Description of the Related Art Conventionally, as this type of semiconductor device,
The one described in Japanese Patent Application Laid-Open No. 1-192125 is known. This semiconductor device, as shown in FIG.
It comprises a substrate 11, a chip 13, and a sealing cap 15. The substrate 11 is formed of a synthetic resin.
The substrate 11 may be formed of alumina. The substrate 11 has a main surface 17.

[0005] A plurality of conductive wires 19 are formed on the main surface 17. The chip 13 is an integrated circuit (not shown)
, A first chip surface 21 and a second chip surface 23. The chip 13 further includes a plurality of bumps 25.
And a conductor film 27. The conductor film 27 covers the bumps 25 and is connected to the integrated circuit. The conductor film 27 protrudes from the first chip surface 21.

A sealing adhesive mass 29 is formed on the main surface 17. The sealing cap 15 is made of metal. The sealing cap 15 has a lower end surface 31 and an inner wall surface 3.
3 and an inner upper surface 35. The inner wall surface 33 and the inner upper surface 35 define a hole accommodating the chip 13. The sealing cap 15 has an elastic film 37 adhered to the inner upper surface 35. The chip 1
The lower end surface 31 is adhered to the main surface 17 by a sealing adhesive mass 29 in a state where 3 is pressed by the conductive wire 19 by the elastic film 37. The conductive film 27 is in contact with the conductive wire 19 by the elastic force of the elastic film 37.

Another conventional semiconductor device is shown in FIG. 6, and this semiconductor device will be described next. This semiconductor device is described in JP-A-4-355937. This semiconductor device includes a substrate 11, a chip 13, and a sealing cap 15. The conductive wire 19 is formed on the main surface. The plurality of conductor bumps 39 are formed on the conductive lines 19. The chip 13 has an integrated circuit, a first chip surface 21, and a second chip surface 23.
The chip 13 further has a plurality of conductor pads 41 connected to the integrated circuit. These conductor pads 41 protrude from the first chip surface 21.

The adhesive layer 43 is formed on the second chip surface 23. The sealing adhesive mass 29 is formed on the main surface 17. The sealing cap 15 has a lower end surface 31, an inner wall surface 33, and an inner upper surface 35. The inner wall surface 33 and the inner upper surface 35 define a hole accommodating the chip 13. The inner upper surface 35 is secondly formed by the adhesive layer 43.
Is bonded to the chip surface 23. The lower end surface 31 is adhered to the main surface 17 by a sealing adhesive mass 29. In this case, the conductor pad 41 is in contact with the conductor bump 39 due to its elastic force.

[0007]

However, in the conventional semiconductor device shown in FIG. 5, the first coefficient of thermal expansion of the substrate 11 is very different from the second coefficient of thermal expansion of the sealing cap 15. In this case, a shear stress is generated in the bump 25 and the conductor film 27 by heating and cooling the chip 13, the substrate 11, and the sealing cap 15. Therefore, this semiconductor device has a problem that it is easily broken by shear stress.

In the conventional semiconductor device shown in FIG. 6, when the first coefficient of thermal expansion of the substrate 11 is very different from the second coefficient of thermal expansion of the sealing cap 15, the shear stress is reduced. Chip 13, substrate 11, and sealing cap 1
5 and the conductor bumps 39 by heating and cooling.
Occurs. Therefore, this semiconductor device has a problem that it is easily broken by shear stress.

An object of the present invention is to provide a semiconductor device which is hardly broken.

[0010]

SUMMARY OF THE INVENTION The present invention has a major surface.
Wiring board and the plurality of conductive lines formed on the wiring substrate main surface, conductor bumps of the chip connected to said conductive line
And a second main surface of the chip and an upper inside of a sealing cap.
In the semiconductor device in which the periphery of the wiring substrate is sealed with a sealing cap, the conductive wire and the conductive bump of the chip
A first conductive thermoplastic resin, which is in close contact with the second main surface of the chip;
An inner upper portion of the sealing cap and a second thermoplastic adhesive;
Each of the sealing caps around the substrate is made of a third thermoplastic resin.
It is characterized by being connected with fat .

[0011]

[0012]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic plan view showing one embodiment of the present invention from which a sealing cap is removed. FIG. 2 is a schematic enlarged longitudinal sectional view showing the embodiment of FIG. The embodiment of FIGS. 1 and 2 has components with the same reference numerals as FIGS. 5 and 6.

This semiconductor device comprises a substrate 11 and a chip 1
3 and a sealing cap 15. The substrate 1
1 is formed of an insulating material. This substrate 11 is formed of, for example, glass epoxy resin. The substrate 11 has a main surface 17 and a sub surface 44. Further, the substrate 11
Has a plurality of through holes from the main surface 17 to the sub surface 44. The plurality of pin terminals 45 are inserted into through holes of the substrate 11. These pin terminals 45 may be fixed to the substrate 11 with copper. Each pin terminal 45 has an upper end connected to the conductive line 19. Each pin terminal 45 has a lower end protruding from the sub surface 44.

The conductive wire 19 is formed on the main surface 17. A plurality of conductive adhesive masses 47 having conductivity are formed on the conductive wires 19. The chip 13 has an integrated circuit, first and second chip surfaces 21 and 23, and a plurality of conductive bumps 49. The conductor bump 4
9 is connected to the integrated circuit and protrudes from the first chip surface 21. The conductor bumps 49 are bonded to the conductive wires 19 by a thermoplastic adhesive mass 47. The thermoplastic adhesive layer 51 is provided on the second chip surface 2.
3 is formed.

A sealed thermoplastic adhesive mass 53 is formed on the main surface 17. The sealing cap 15 has a lower end face 31.
And an inner wall surface 33 and an inner upper surface 35. The inner wall surface 33 and the inner upper surface 35 are defined as holes accommodating the chip 13. The inner upper surface 35 is bonded to the second chip surface 23 by the thermoplastic adhesive layer 51. The lower end surface 31 is adhered to the main surface 17 by the hermetic thermoplastic adhesive mass 53.

Each of the thermoplastic adhesive masses 47 has a first melting point. The thermoplastic adhesive layer 51 has a second melting point. The sealed thermoplastic adhesive mass 53 has a third melting point. Each of the first to third melting points is 1
It is in the range of 60 ° C. or more and 375 ° C. or less.

Each of the thermoplastic adhesive masses 47 has a first coefficient of thermal expansion. The thermoplastic adhesive layer 51 is a second layer.
Has a coefficient of thermal expansion of The sealed thermoplastic adhesive mass 53 has a third coefficient of thermal expansion. Each of the first to third coefficients of thermal expansion is 230 × 10 ⁻⁷ or more and 4
It is within the range of 00 × 10 ⁻⁷ or less.

Each of the thermoplastic adhesive masses 47 has a first thermal conductivity. The thermoplastic adhesive layer 51 has a second thermal conductivity. The sealed thermoplastic adhesive mass 53
Has a third thermal conductivity. Each of the first to third thermal conductivity is 3 Watt / Metter / ° C. (W / M
/ C) or more and 3.5 (W / M / C) or less.

For example, each thermoplastic adhesive mass 47 is
It is formed of a mixture of polyurethane, ethyl sulfone or polyoxyether and silver powder. The silver powder is 1
It has a particle size of 0 μm or less. The mixture comprises:
It contains 70 to 90% by weight of the silver powder and 30 to 10% by weight of polyurethane, ethyl sulfone or polyoxyether. Each of the thermoplastic adhesive layers 51 and the hermetic thermoplastic adhesive mass 53 are made of polyurethane, ethyl sulfone or polyoxyether. The sealing cap 15 is made of copper or aluminum.

Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. The embodiment of FIGS. 3 and 4 has the same reference number components as the embodiment of FIGS. 1 and 2. The semiconductor device further has an upper substrate 55 formed on the substrate 11 and the conductive lines 19 so as to surround the sealing cap 15. The upper substrate 55 is formed of an insulator material. Upper substrate 5
5 has a plurality of through holes. The pin terminals 45 are inserted into through holes of the upper substrate 55.
Each pin terminal 45 has a lower end connected to one of the conductive lines 19. Each pin terminal 45 has an upper end protruding from the upper surface 57 of the upper substrate 55. The substrate 11 can be formed of a semiconductor material, for example, silicon.

[0022]

According to the semiconductor device of the present invention, the thermoplastic adhesive is used to bond between the substrate and the sealing cap, between the chip and the sealing cap, and between the conductor bumps and the conductive wires of the chip. Even if the sealing cap and the chip are heated and cooled, the conductive bumps are less likely to be broken because they are less likely to generate shear stress.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a semiconductor device according to a first embodiment of the present invention with a cap removed.

FIG. 2 is a substantially enlarged vertical sectional view showing the semiconductor device shown in FIG. 1;

FIG. 3 is a schematic plan view showing a semiconductor device according to a second embodiment of the present invention with a cap removed.

FIG. 4 is a substantially enlarged vertical sectional view showing the semiconductor device shown in FIG. 3;

FIG. 5 is a schematic vertical sectional view showing a conventional semiconductor device.

FIG. 6 is a schematic longitudinal sectional view showing another conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Substrate 13 Chip 15 Sealing cap 17 Main surface 19 Conductive wire 21 First chip surface 23 Second chip surface 25 Bump 27 Dielectric film 29 Sealing adhesive mass 31 Lower end surface 33 Inner wall surface 35 Inner upper surface 37 Elastic film 39 Conductive Body bump 41 Conductor pad 43 Adhesive layer 44 Subsurface 45 Pin terminal 47 Thermoplastic adhesive mass 49 Conductor bump 51 Thermoplastic adhesive layer 53 Sealed thermoplastic adhesive mass

Claims (4)

(57) [Claims] A wiring board having a main surface; a plurality of conductive lines formed on the wiring substrate ; and a plurality of conductive lines connected to the conductive lines.
Conductive bumps of the chip, and a second main surface of the chip.
In a semiconductor device in which an inner upper portion of a sealing cap and the periphery of the wiring substrate are sealed with a sealing cap,
The conductive bump of the chip is the first conductive thermoplastic resin,
The second main surface of the chip and the upper inside of the sealing cap are
Thermoplastic adhesive, the periphery of the substrate is that of a sealed cap
A semiconductor device, wherein each is connected by a third thermoplastic resin . 2. The semiconductor device according to claim 1, wherein
The first thermoplastic resin has a first softening point and a second thermoplastic resin.
The plastic resin has a second softening point, and the third thermoplastic resin is
A semiconductor device having a third softening point , wherein each of the first to third softening points is in a range of 160 ° C. or more and 375 ° C. or less. 3. The semiconductor device according to claim 2, wherein
The first thermoplastic resin has a first coefficient of thermal expansion and a second
The thermoplastic has a second coefficient of thermal expansion and a third thermoplastic.
Resin has a third coefficient of thermal expansion, and the first to third coefficients of thermal expansion are each not less than 230 × 10 ⁻⁷ and 400 ×
A semiconductor device having a range of 10 ⁻⁷ or less. 4. The semiconductor device according to claim 2, wherein
The first thermoplastic has a first thermal conductivity and a second thermal conductivity.
The thermoplastic resin has a second thermal conductivity and a third thermoplastic resin.
The fat has a third thermal conductivity, and each of the first to third thermal conductivity is not less than 3 (W / M / ° C.) and not less than 3.5 (W / M / M).
/ ° C) within the following range.