JPS59117250A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59117250A JPS59117250A JP22630082A JP22630082A JPS59117250A JP S59117250 A JPS59117250 A JP S59117250A JP 22630082 A JP22630082 A JP 22630082A JP 22630082 A JP22630082 A JP 22630082A JP S59117250 A JPS59117250 A JP S59117250A
- Authority
- JP
- Japan
- Prior art keywords
- silicon substrate
- chips
- chip
- fixed
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
Description
【発明の詳細な説明】
本発明はシリコンチップをフェースダウンポンディング
法によりセラミックパッケージ内に実装した半導体装置
に関し、特に複数個のチップを同一パッケージ内に高密
度に実装可能な半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which a silicon chip is mounted in a ceramic package using a face-down bonding method, and particularly to a semiconductor device in which a plurality of chips can be mounted in the same package at high density. be.
シリコンチップをフェースダウンポンディング法により
セラミックパッケージ内に実装する場合、第１図に示す
ようにセラミックベース１のキャビティｌａ内底面に所
定の配線２をメタライズ等の手段によって形成し、この
配線２、即ちセラミックベース１上にチップ３のバンプ
４を直接接続させてチップ３の固着およびチップと配線
２に続く外部リード５の電気的接続を行なっている。図
中、６はキャップ、７は封止用の低融点ガラスである。When a silicon chip is mounted in a ceramic package by the face-down bonding method, as shown in FIG. That is, the bumps 4 of the chip 3 are directly connected to the ceramic base 1 to fix the chip 3 and to electrically connect the external leads 5 following the chip and the wiring 2. In the figure, 6 is a cap, and 7 is a low melting point glass for sealing.
しかしながら、この構造では温度変化がチップ３やセラ
ミックベース１に作用してこれらが熱膨張される状態に
なると、シリコンとセラミックの熱膨張係数が大幅に相
違しているため、両者間に熱的ストレスが発生し、この
熱的ストレスがバンプ４部に加わってその応力によりバ
ンプ４部における前記した接続を破壊し、装置の信頼性
を低下するという問題が起り易い。However, with this structure, when a temperature change acts on the chip 3 and ceramic base 1 and causes them to thermally expand, thermal stress is generated between them because the thermal expansion coefficients of silicon and ceramic are significantly different. occurs, and this thermal stress is applied to the bump 4, which tends to destroy the connection at the bump 4 and reduce the reliability of the device.
このため、複数個のチップを同一のパッケージ内に実装
して装置の高密度化を図るという要求が生じていても、
信頼性の点から前述した構成を採用することは殆んど不
可能である。したがって、従来ではチップ毎（（ワイヤ
ボンディングを利用した実装形態を採らざるを得す、パ
ッケージ工程の複雑化を生じ或いは高密度化の障害にな
る等の問題がある。For this reason, even if there is a demand to increase the density of devices by mounting multiple chips in the same package,
From the viewpoint of reliability, it is almost impossible to employ the above-mentioned configuration. Therefore, in the past, there were problems such as having to adopt a mounting method using wire bonding for each chip, complicating the packaging process, and impeding high density.
したがって本発明の目的は、チップをフェースダウンボ
ンディング法により同一のパンケージ内に高密度に実装
してもその信頼性を低下させることのない半導体装置を
提供することにある。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device in which the reliability of the semiconductor device is not reduced even when chips are mounted at high density in the same pan cage using the face-down bonding method.
この目的を達成するために本発明は、表面に絶縁配線を
施したシリコン基板上に複数個のチップをフェースダウ
ンボンディングし、かつこのシリコン基板をセラミック
パッケージ内に内装してパンケージを構成するようにし
たものである。In order to achieve this object, the present invention involves bonding a plurality of chips face-down onto a silicon substrate with insulated wiring on the surface, and then arranging this silicon substrate inside a ceramic package to form a pan cage. This is what I did.
以下、本発明を図示の実施例により説明する。Hereinafter, the present invention will be explained with reference to illustrated embodiments.
第２図は本発明の半導体装置の一実施例の断面図であり
、図において１０は比較的に強度の高いシリコン基板で
ある。このシリコン基板１０はその表面に５ｉｎ２等の
酸化膜を形成すると共に蒸着等の薄膜技術によって所要
の金属（例えばアルミニウム）配線１１を互に絶縁状態
で形成している。FIG. 2 is a cross-sectional view of one embodiment of the semiconductor device of the present invention, and in the figure, reference numeral 10 indicates a relatively strong silicon substrate. On the surface of this silicon substrate 10, an oxide film of 5 in 2 or the like is formed, and required metal (for example, aluminum) wirings 11 are formed insulated from each other by thin film technology such as vapor deposition.
そして、このシリコン基板１００表面の配線１１には複
数個のシリコンチップ１２・・・・・・をそのバンプ１
３を介してフェースダウンボンディングにより固着して
いる。また、チップ１２を固着したシリコン基板１０は
Ａｇペーストや比較的に融点の高いガラス等からなるろ
う材１４にてセラミックベース１５のキャビテイ１５ａ
内底面上に固着している。その上で、セラミックベース
１５の周辺部に低融点ガラス１６にて支持した外部導出
り−ド１７とシリコン基板１０の配線一部１１ａとをワ
イヤ１８にて接続し、更にセラミックキャップ１９を被
せてこれを前記低融点ガラス１６にてペース１５に溶着
することにより封止を完成している。なお、外部導出リ
ード１７は通常リードフレームとして構成される。また
、封止材として低融点ガラス１６に替えてエポキシ系樹
脂等を用いることもできる。Then, on the wiring 11 on the surface of the silicon substrate 100, a plurality of silicon chips 12 .
It is fixed by face down bonding via 3. Further, the silicon substrate 10 to which the chip 12 is fixed is connected to the cavity 15a of the ceramic base 15 using a brazing material 14 made of Ag paste or glass having a relatively high melting point.
It is fixed on the inner bottom surface. Then, the external lead 17 supported by the low melting point glass 16 around the ceramic base 15 and the wiring part 11a of the silicon substrate 10 are connected with a wire 18, and a ceramic cap 19 is further placed on the wire 18. Sealing is completed by welding this to the paste 15 using the low melting point glass 16. Note that the external leads 17 are usually configured as a lead frame. Furthermore, an epoxy resin or the like may be used as the sealing material instead of the low melting point glass 16.
以上の構成によれば、複数個の各チップ１２は同一材料
であるシリコンの基板１０に直接固着されているため、
温度変化によってチップ１２およびシリコン基板１０が
共に熱膨張しても両者は同一の熱膨張係数によって同一
状態で伸縮するため、熱ストレスが生じることはなく、
したがってバンプ１３における接続破壊が発生すること
は全くない。一方、シリコン基板１０とセラミックベー
ス１５との間では熱膨張係数の差による熱的応力が生じ
るが、基板１００強度が高いことおよびろう材１４によ
る応力の吸収作用によって両者の固着状態が破壊される
ことはない。According to the above configuration, since each of the plurality of chips 12 is directly fixed to the silicon substrate 10 made of the same material,
Even if both the chip 12 and the silicon substrate 10 thermally expand due to temperature changes, both expand and contract in the same state due to the same coefficient of thermal expansion, so no thermal stress occurs.
Therefore, connection failure at the bump 13 never occurs. On the other hand, thermal stress is generated between the silicon substrate 10 and the ceramic base 15 due to the difference in coefficient of thermal expansion, but due to the high strength of the substrate 100 and the stress absorption effect of the brazing material 14, the bonding state between the two is broken. Never.
したがって、本例のように複数個のチップ１２を一枚の
シリコン基板１０を介して同一のパッケージ内に内装し
ても、チップ接続の信頼性を充分高いものに保持でき、
かつ一方ではチップ実装の高密度化を極めて容易に実現
することができるのである。Therefore, even if a plurality of chips 12 are housed in the same package via a single silicon substrate 10 as in this example, the reliability of chip connection can be maintained at a sufficiently high level.
On the other hand, high-density chip packaging can be achieved extremely easily.
第３図は本発明の他の実施例を示し、前例と同一部分に
は同一符号を付してその説明は省略している。FIG. 3 shows another embodiment of the present invention, in which the same parts as in the previous example are denoted by the same reference numerals and the explanation thereof is omitted.
本実施例では、セラミックベース１５の周辺の高さをシ
リコン基板１００表面位置と略等しくすると共に、セラ
ミックベースの周辺状に支持した外部導出リード１７の
内端を直接シリコン基板１０表面の配線１１ａに接続し
ている。In this embodiment, the height of the periphery of the ceramic base 15 is made approximately equal to the surface position of the silicon substrate 100, and the inner end of the external lead 17 supported around the periphery of the ceramic base is directly connected to the wiring 11a on the surface of the silicon substrate 10. Connected.
このように構成すれば、シリコン基板１０と外部導出リ
ード１７とを接続するワイヤ１８およびそのボンディン
グ作業をも不要にできるので、前述した効果に加えて部
品点数の低減、Ａ・ｉ］付作業の簡易化を図ると共に、
ワイヤ１８に関する故障防止を図って信頼性を更に向上
することができるという効果が得られる。With this configuration, the wire 18 that connects the silicon substrate 10 and the external lead 17 and the bonding work therefor can be eliminated, so in addition to the above-mentioned effects, the number of parts can be reduced and the work with A.i. In addition to simplifying the
The effect is that failures related to the wire 18 can be prevented and reliability can be further improved.
なお、前記シリコン基板は単結晶シリコンのみならず多
結晶シリコンであってもよい。また、熱膨張係数を変化
させない範囲で化学的或いは物理的な処理を施したもの
であってもよい。更にシリコン基板はＡｕ−８ｉ共晶を
利用してベース上に固着してもよい。Note that the silicon substrate may be made of not only single crystal silicon but also polycrystal silicon. Further, it may be subjected to chemical or physical treatment within a range that does not change the coefficient of thermal expansion. Furthermore, the silicon substrate may be fixed onto the base using Au-8i eutectic.
以上のように本発明の半導体装置によれば、シリコン基
板上に複数個のチップをフェースダウンボンディングし
、かつこのシリコン基板をセラミックペース内に固着し
た構成としているので、温度変化に伴なうバンブ等の破
壊を防止してその信頼性を高めると共に、複数個げチッ
プによる高密度化を可能に１２かつそのパッケージ作業
の簡易化を図ることもできるという効果を奏する。As described above, according to the semiconductor device of the present invention, a plurality of chips are face-down bonded onto a silicon substrate, and this silicon substrate is fixed within a ceramic paste, so that bumps due to temperature changes can be avoided. This has the advantage of not only increasing its reliability by preventing damage such as the like, but also making it possible to increase the density by using a plurality of chips, and simplifying the packaging process.
第１図は従来装置の断面図、
第２図は本発明の一実施例装置の断面図、７５３図は他
の実施例の断面図である。
１０・・・シリコン基板、１１・・・配線、１２・・・
チップ、１３・・・バンプ、１４・・・ろう材、１５・
・・セラミックベース、１７・・・外部導出リード（リ
ードフレーム）、１８・・・ワイヤ、１９・・・キャッ
プ。
代理人 弁理士 薄 １）利 幸ｉ 霞２１１−FIG. 1 is a sectional view of a conventional device, FIG. 2 is a sectional view of an embodiment of the device of the present invention, and FIG. 753 is a sectional view of another embodiment. 10... Silicon substrate, 11... Wiring, 12...
Chip, 13... Bump, 14... Brazing metal, 15.
... Ceramic base, 17... External lead-out lead (lead frame), 18... Wire, 19... Cap. Agent Patent Attorney Susuki 1) Yukii Kasumi 211-
Claims (1)
ングによりシリコン基板上に固着すると共に、このシリ
コン基板をセラミックパッケージ内に固着内装したこと
を特徴とする半導体装置。 ２、一枚のシリコン基板上に各チップを固着してなる特
許請求の範囲第１項記載の半導体装置。 ３、 セラミックパッケージに支持した外部導出リード
の内端をシリコン基板表面の配線に直接接続してなる特
許請求の範囲第１項又は第２項記載の半導体装置。[Scope of Claims] 1. A semiconductor device characterized in that a plurality of silicon chips are fixed onto a silicon substrate by face-down bonding, and the silicon substrate is fixedly housed inside a ceramic package. 2. The semiconductor device according to claim 1, wherein each chip is fixed on a single silicon substrate. 3. The semiconductor device according to claim 1 or 2, wherein the inner end of the external lead supported by the ceramic package is directly connected to wiring on the surface of the silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22630082A JPS59117250A (en) | 1982-12-24 | 1982-12-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22630082A JPS59117250A (en) | 1982-12-24 | 1982-12-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59117250A true JPS59117250A (en) | 1984-07-06 |
Family
ID=16843046
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22630082A Pending JPS59117250A (en) | 1982-12-24 | 1982-12-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59117250A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4901136A (en) * | 1987-07-14 | 1990-02-13 | General Electric Company | Multi-chip interconnection package |
| US4907062A (en) * | 1985-10-05 | 1990-03-06 | Fujitsu Limited | Semiconductor wafer-scale integrated device composed of interconnected multiple chips each having an integration circuit chip formed thereon |
| JPH06268090A (en) * | 1993-03-17 | 1994-09-22 | Kyocera Corp | Package for storing semiconductor element |
| JPH07201921A (en) * | 1993-11-25 | 1995-08-04 | Nec Corp | Semiconductor device |
| JP2006191117A (en) * | 2005-01-06 | 2006-07-20 | Sychip Inc | Integrated passive device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56134747A (en) * | 1980-03-25 | 1981-10-21 | Mitsubishi Electric Corp | Semiconductor device |
-
1982
- 1982-12-24 JP JP22630082A patent/JPS59117250A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56134747A (en) * | 1980-03-25 | 1981-10-21 | Mitsubishi Electric Corp | Semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4907062A (en) * | 1985-10-05 | 1990-03-06 | Fujitsu Limited | Semiconductor wafer-scale integrated device composed of interconnected multiple chips each having an integration circuit chip formed thereon |
| US4901136A (en) * | 1987-07-14 | 1990-02-13 | General Electric Company | Multi-chip interconnection package |
| JPH06268090A (en) * | 1993-03-17 | 1994-09-22 | Kyocera Corp | Package for storing semiconductor element |
| JPH07201921A (en) * | 1993-11-25 | 1995-08-04 | Nec Corp | Semiconductor device |
| JP2006191117A (en) * | 2005-01-06 | 2006-07-20 | Sychip Inc | Integrated passive device |
| JP4589237B2 (en) * | 2005-01-06 | 2010-12-01 | サイチップ インコーポレーテッド | Integrated passive device |
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