JPS62183133A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62183133A
JPS62183133A JP61023740A JP2374086A JPS62183133A JP S62183133 A JPS62183133 A JP S62183133A JP 61023740 A JP61023740 A JP 61023740A JP 2374086 A JP2374086 A JP 2374086A JP S62183133 A JPS62183133 A JP S62183133A
Authority
JP
Japan
Prior art keywords
bonding
bonded
external connection
semiconductor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61023740A
Other languages
Japanese (ja)
Inventor
Yasuo Maruyama
丸山　泰男
Minoru Suda
須田　実
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61023740A priority Critical patent/JPS62183133A/en
Publication of JPS62183133A publication Critical patent/JPS62183133A/en
Pending legal-status Critical Current

Links

Classifications

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/166—Material

Abstract

PURPOSE:To improve the hermetic property as well as the reliability of a semiconductor device, by bonding semiconductor conducting terminals of silicon or the like previously provided with an aluminum layer to external connection terminals so that bonding wires are bonded to the aluminum layers, and heating and melting low-melting frit glass for sealing a ceramic package so that the ceramic package hermetically contains the elements thus wire-bonded. CONSTITUTION:An aluminum layer 19 is formed on the top face of each of silicon chips 16 and 17. The silicon chips 16 and 17 are then bonded to an end of external connection terminals 14 and 15, respectively, by means of AuSi eutectic 18. A semiconductor chip 22 is bonded at a predetermined position on an external connection terminal 21 by means of the AuSi eutectic 18. They are wire bonded with bonding wires of aluminum 24. Subsequently, low-melting frit glass 13 is heated and molten. Even if the chips are exposed to a temperature of about 400-450 deg.C during this heating process, no purple plague occurs since there is no Au at the bonding positions of the bonding wires 24.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置、特に高周波パワートランジスタに
利用して有効な技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique that is effectively applied to semiconductor devices, particularly high frequency power transistors.

〔従来の技術〕[Conventional technology]

半導体集積回路（以下においてＩＣという）、トランジ
スタ等の半導体装置は、プラスチックや金属等によって
パッケージングされてｂる。上記パッケージについては
、「電子デバイス事典」（昭昭５１年３月２０日初版発
行、発行所ラジオ技術社、ｐｌ）３１６〜３１８）に記
載されている。その概要は、パッケージは単に外装とい
うイメージを離れて実装という概念に近付きつつあり、
半導体装置にとって極めて重要な要素になっている、等
である。Semiconductor devices such as semiconductor integrated circuits (hereinafter referred to as ICs) and transistors are packaged with plastic, metal, or the like. The above packages are described in "Electronic Device Encyclopedia" (first edition published March 20, 1970, published by Radio Gijutsusha, pl) 316-318). The outline of this is that packages are moving away from the image of just an exterior and are moving closer to the concept of packaging.
It has become an extremely important element for semiconductor devices.

本発明者等は、半導体装置、特に制周波パワーＭＯ８Ｆ
ＥＴの気密性の向上、信頼性の向上環について検討した
。以下は、公知とされた技術ではないが、本発明者等に
よって検討された技術であシ、その概要は次のとおりで
ある。The present inventors have developed a semiconductor device, particularly a frequency control power MO8F.
We considered ways to improve the airtightness and reliability of ET. Although the following is not a publicly known technique, it is a technique that has been studied by the present inventors, and its outline is as follows.

すなわち、第５図はストリップライン型に形成された高
周波パワーＭＯ８ＦＥＴ１の外形を示すものであり、第
６図は上記第５図のＡ−Ａ／線に沿う断面図であり、両
者を参照しつつ説明する。That is, FIG. 5 shows the outline of the high frequency power MO8FET 1 formed in a strip line type, and FIG. 6 is a cross-sectional view taken along the line A-A/ in FIG. explain.

２はセラミックパッケージであり、パッケージ２内にお
いてＨ型の外部接続端子３のほぼ中央部には半導体チッ
プ４が接着されている。そして外部接続端子５．６と上
記半導体チップ４の端子とはＡｌ線７，８によってボン
ティングされている。Reference numeral 2 denotes a ceramic package, and within the package 2, a semiconductor chip 4 is bonded approximately at the center of an H-shaped external connection terminal 3. The external connection terminals 5.6 and the terminals of the semiconductor chip 4 are bonded by Al wires 7 and 8.

なお、上記外部接続端子３．５．６は耐触性の点からＡ
ｕメッキが施されている。Note that the external connection terminals 3.5.6 are A in terms of contact resistance.
U-plated.

更に１セラミツク基板９は放熱効果を高めるため、酸化
ベリリア（以下単にベリリアとも言う。）が使用されて
いる。そして上記パッケージ２と上記各接続端子３　、
５　、６、セラミック基板９との接着は、エポキシレジ
ン接着剤１０によってなされている。Furthermore, the ceramic substrate 9 uses beryllia oxide (hereinafter also simply referred to as beryllia) in order to enhance the heat dissipation effect. and the package 2 and each connection terminal 3,
5, 6. Adhesion to the ceramic substrate 9 is achieved using an epoxy resin adhesive 10.

上記高周波パワーＭＯ８ＦＥＴ１の構造によれば、エポ
キシレジン接着剤１０は１２０℃〜１８０℃程度の過熱
で上記接着がおこなわれること、安価である、等の利点
を有している。According to the structure of the high-frequency power MO8FET 1, the epoxy resin adhesive 10 has advantages such as the above-mentioned bonding can be performed by heating at about 120° C. to 180° C., and it is inexpensive.

しかし、本発明者等の検討によると、以下に述べるよう
な問題点を有していることが明らかになっ九。However, according to the studies conducted by the present inventors, it has become clear that there are problems as described below9.

ｒ発明が解決しようとする問題点〕 エポキシレジン接着剤１０は耐湿性がよくなく、半導体
装置の気密性が低下するので、半導体装置の信頼性を損
うものである。Problems to be Solved by the Invention] The epoxy resin adhesive 10 does not have good moisture resistance, which reduces the airtightness of the semiconductor device, thereby impairing the reliability of the semiconductor device.

そこで本発明者等は、Ａｕ−８ｆｌ或いはＡＵＧｅ等の
低融点共晶ロー材を使用して、上記接着を行うことを検
討した。Therefore, the present inventors considered using a low melting point eutectic brazing material such as Au-8fl or AUGe to perform the above-mentioned adhesion.

しかしこの場合は、パッケージ２の接着位置のメタライ
ズ、ステム９側では外部接続端子との接触部分を絶縁し
、かつ上記パッケージ２との接触部分をメタライズした
セラミックリングを積層する必要があり、このため上記
構造に比較してほぼ２倍ものコスト高になることが明ら
かになった。However, in this case, it is necessary to metalize the bonding position of the package 2, insulate the contact area with the external connection terminal on the stem 9 side, and laminate a metalized ceramic ring at the contact area with the package 2. It has become clear that the cost is approximately twice as high as that of the above structure.

そこで本発明者等は、低融点ガラスにより封止を行うこ
とを検討した。この場合、気密性は良好になり、半導体
装置の信頼性を著しく向上せしめることが可能になる。Therefore, the present inventors considered performing sealing with low melting point glass. In this case, the airtightness becomes good and the reliability of the semiconductor device can be significantly improved.

しかし低融点カラスの溶融には、４００℃〜４５０℃も
の加熱が必要であシ、加熱時においてボンディングワイ
ヤ７．８と外部接続端子５，６とのボンティング位置に
おいてＡＡ’とＡｕの合金のうちパープルプレイブと呼
ばれる合金現象が発生し易いことが判明した。However, heating of 400°C to 450°C is required to melt the low melting point glass, and during heating, the alloy of AA' and Au is heated at the bonding position between the bonding wire 7.8 and the external connection terminals 5 and 6. It has been found that an alloying phenomenon called purple plave is likely to occur.

上記現象が発生すると、ＡＩとＡｕとの合金部分、換言
すればボンディングワイヤと外部接続端子のＡｕ処理さ
れた両者のボンティング位置において断線が発生するこ
とがある。When the above phenomenon occurs, a wire breakage may occur at the alloy part of AI and Au, in other words, at the bonding position of both the bonding wire and the external connection terminal treated with Au.

本発明者等は、低融点ガラスを用い、かつ上記バーブル
プレイグ現象の発生を低減すれば、安価で高信頼性の半
導体装置が得られることに気づき、本発明をなすに至っ
たものである。The present inventors realized that by using a low melting point glass and reducing the occurrence of the bubble plague phenomenon described above, an inexpensive and highly reliable semiconductor device could be obtained, and this led to the present invention.

本発明の目的は、気密性が良好で信頼性が高く、かつ安
価に生産し得る半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device that has good airtightness, is highly reliable, and can be produced at low cost.

本発明の上記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔問題を解決するための手段〕[Means to solve the problem]

本願において開示される発明のうちの代表的なものの概
要を簡単に述べれば、下記の通りである。A brief summary of typical inventions disclosed in this application is as follows.

すなわち、パッケージと外部接続端子、更にセラミック
基板とを低融点ガラスにより接着するとともに、ボンデ
ィングワイヤと外部接続端子とのボンディング位置に、
上記外部接続端子に導電可能に例えば低抵抗のシリコン
等からなる半導体導電端子を設け、その上部のボンディ
ングワイヤがボンディングされる位置に予めＡＪ層を形
成し、ＡＪ線にて形成されたボンディングワイヤと上記
ＡＪ層とをボンディングするものである。That is, the package, the external connection terminals, and the ceramic substrate are bonded together using low-melting glass, and at the bonding position of the bonding wire and the external connection terminal,
A semiconductor conductive terminal made of, for example, low-resistance silicon is provided on the external connection terminal so as to be conductive, and an AJ layer is formed in advance at the position on which the bonding wire is bonded, and the bonding wire formed of the AJ wire is bonded to the AJ layer. It is for bonding with the above AJ layer.

〔作用〕[Effect]

上記した手段によれば、低融点ガラスを４００℃程度で
加熱し上記接着をおこなっても、ボンデイング位置にＡ
ｕ成分がなく、上記パープルプレイブ現象による断線が
発生しないので、パッケージの気密性が良好で高信頼性
の半導体装置を得る、という本発明の目的を達成するこ
とができる。According to the above means, even if the low melting point glass is heated to about 400°C and the above bonding is performed, the A
Since there is no u component and disconnection due to the purple plave phenomenon does not occur, the object of the present invention, which is to obtain a highly reliable semiconductor device with good package airtightness, can be achieved.

〔実施例〕〔Example〕

以下、第１図〜第４図を参照して本発明を適用した半導
体装置の一実施例を説明する。なお、第１図は半導体装
置の構造を示す断面図、第２図は要部の拡大断面図、第
３図は半導体装置の平面図、第４図は本発明の達成する
作業工程の７０−チャートを示すものである。Hereinafter, one embodiment of a semiconductor device to which the present invention is applied will be described with reference to FIGS. 1 to 4. Note that FIG. 1 is a sectional view showing the structure of a semiconductor device, FIG. 2 is an enlarged sectional view of main parts, FIG. 3 is a plan view of the semiconductor device, and FIG. It shows a chart.

本実施例の特徴は、低融点ガラスを用いてパッケージの
封止全行うとともに、ボンディングワイヤの断線を低減
し得るように構成したことにある。The feature of this embodiment is that the package is completely sealed using low-melting glass, and the structure is such that disconnection of bonding wires can be reduced.

高周波パワーＭＯ８ＦＥＴＩＩにおいて、１２はセラミ
ックパッケージであり、１３は低融点フリットガラスを
示すものである。第１図および第２図に示すように、本
発明でいう第１の外部接続端子１４．１５上の一端には
、本発明でいう半導体導電端子であるシリコンチップ１
６．１７がＡｕＳｉ共晶１８によって接着されている。In the high frequency power MO8FET II, 12 is a ceramic package, and 13 is a low melting point frit glass. As shown in FIGS. 1 and 2, at one end of the first external connection terminal 14.15, there is a silicon chip 1, which is a semiconductor conductive terminal in the invention.
6.17 is bonded by AuSi eutectic 18.

そして上記シリコンチップ１６．１７の上面には、ＡＪ
層１９が形成されている。And on the upper surface of the silicon chip 16.17, AJ
A layer 19 is formed.

上記シリコンチップ１６．１７は、抵抗率０．０２Ω−
ｃｍ程度であり、導体として充分に使用することができ
る。The silicon chip 16.17 has a resistivity of 0.02Ω-
cm, and can be sufficiently used as a conductor.

第３図に示すように、平面Ｈ字型に形成された本発明で
いう第２の外部接続端子２１のほぼ中央部には、半導体
テップ２２がＡｕＳｉ共晶１８によって接着されている
。As shown in FIG. 3, a semiconductor tip 22 is bonded with an AuSi eutectic 18 approximately at the center of the second external connection terminal 21 referred to in the present invention, which is formed into an H-shape in plan.

そして半導体チップ２２上のＡｌ端子２３と上記ＡＪ層
１９との間は、ＡＪ線によって形成されたボンディング
ワイヤ２４によって接続されている。The Al terminals 23 on the semiconductor chip 22 and the AJ layer 19 are connected by bonding wires 24 formed by AJ lines.

なお、２５はセラミック基板であシ、半導体チップ２２
から発生した熱を効率よく放熱し得るものである。Note that 25 is a ceramic substrate, and a semiconductor chip 22
It is possible to efficiently dissipate the heat generated from the

次に、第４図を参照して作業工程を説明する。Next, the working process will be explained with reference to FIG.

先ず、Ａｕ５ｌ共晶１８によって外部接続端子１４．１
５の一端にシリコンチップ１６．１７を接着する。次に
、外部接続端子２１上の所定位置に、ＡｕＳｉ共晶１８
によシ、半導体チップ２２を接着し、ＡＪ線のボンディ
ングワイヤ２４により上記の如きワイヤボンディングを
行う。First, the external connection terminal 14.1 is connected using the Au5L eutectic 18.
A silicon chip 16, 17 is glued to one end of 5. Next, place the AuSi eutectic 18 at a predetermined position on the external connection terminal 21.
Then, the semiconductor chip 22 is bonded, and wire bonding as described above is performed using the AJ wire bonding wire 24.

次いで低融点フリットガラス１３を加熱によシ溶融する
のであるが、この際４００℃〜４５０℃程度の熱が加え
られるが％Ａｌ端子２３とボンディングワイヤ２４との
ボンディング位置、ならびにボンディングワイヤ２４と
１層１９とのボンディング位置とにＡｕ成分がないので
、上記パープルプレイブ現象が発生しない。Next, the low melting point frit glass 13 is melted by heating, and at this time, heat of about 400°C to 450°C is applied, but the bonding position between the Al terminal 23 and the bonding wire 24, as well as the bonding wire 24 and 1 Since there is no Au component at the bonding position with layer 19, the purple plave phenomenon described above does not occur.

したがって、低融点７リツトガラス１３による接着が行
われても、ボンディング位置に断線がなく、本発明の目
的のひとつである気密性の向上が達成されるうえに、の
断線事故の発生が未然に防止される。Therefore, even if bonding is performed using the low melting point 7 lithium glass 13, there will be no wire breakage at the bonding position, and one of the objectives of the present invention, which is improved airtightness, can be achieved, and the occurrence of wire breakage accidents can be prevented. be done.

ところで、半導体装置は製造工程において各種検査がな
されるが、そのひとつに高温検査がある。Incidentally, semiconductor devices are subjected to various inspections during the manufacturing process, one of which is high temperature inspection.

しかし、この工程においてもボンディングワイヤに断線
が発生するようなことがなく、シかも低融点フリットガ
ラスの接着力は強固であるので、パッケージのり一ケー
ジが大巾に低減される。However, even in this step, the bonding wire does not break, and the adhesive strength of the low melting point frit glass is strong, so the package glue and cage can be greatly reduced.

（１）半導体装置のパッケージの接着を低融点７す、ト
ガラスの加熱溶融によりおこなうことにより。(1) The semiconductor device package is bonded by heating and melting glass, which has a low melting point of 7.

パッケージの接着が強固になるという作用で、半導体装
置の気密性を向上せしめる、という効果が得られる。By strengthening the bonding of the package, it is possible to improve the airtightness of the semiconductor device.

（２）上記（１）により、半導体装置の信頼性が向上す
る、という効果が得られる。(2) The above (1) provides the effect of improving the reliability of the semiconductor device.

（３）半導体装置の外部接続端子の一端でボンディング
ワイヤが接続される位置に、パッドチップとなるシリコ
ンチップを導電可能に接着し、しかもボンディング位置
にＡｊＮを形成して上記ボンディングワイヤとのボンデ
ィングを行うように構成することにより、パッケージの
接着時に加熱されてもボンディング部分でＡＪとＡｕと
の合金が形成されず、パープルプレイブ現象が発生しな
いという作用で、ボンディング位置の断線を低減し得る
、という効果が得られる。(3) At one end of the external connection terminal of the semiconductor device, a silicon chip that will become a pad chip is adhered to the position where the bonding wire is connected in a conductive manner, and AjN is formed at the bonding position to facilitate bonding with the bonding wire. By configuring it to do so, even if heated during bonding of the package, an alloy of AJ and Au will not be formed at the bonding part, and the purple plave phenomenon will not occur, so that disconnection at the bonding position can be reduced. This effect can be obtained.

（４）上記（３）により、半導体装置の信頼性が著しく
向上する、という効果が得られる。(4) The above (3) provides the effect that the reliability of the semiconductor device is significantly improved.

（５）上記（１）（３）により、半導体装置の大幅なコ
ストダウンが図れる、という効果が得られる。(5) According to (1) and (3) above, it is possible to achieve the effect that the cost of the semiconductor device can be significantly reduced.

以上て、本発明者等によってなされた発明を実施例にも
とづき具体的に説明し念が、本発明は上記実施例に限定
されるものではなく、その要旨は逸脱しない範囲で種々
変形可能であることはいうまでもない。In the above, the invention made by the present inventors has been specifically explained based on examples. However, the present invention is not limited to the above-mentioned examples, and various modifications can be made without departing from the gist of the invention. Needless to say.

たとえば、パッケージの形状は上記円板状に限定されず
、デュアルインライン型ＩＣのごとき板状の形状であっ
てもよい。For example, the shape of the package is not limited to the above disk shape, but may be a plate shape such as a dual in-line IC.

以上の説明では、主として本発明者等によってなされた
発明をその背景となった利用分野である高周波パワーＭ
Ｏ８）ｉ’ＥＴに適用した場合について説明したが、そ
れに限定されるものではなく、高周波用セラミックパッ
ケージの半導体装置に利用することができる。In the above explanation, the invention made by the present inventors will be mainly described as a field of application for high frequency power M
O8) Although the case where the present invention is applied to i'ET has been described, the present invention is not limited thereto, and can be applied to a semiconductor device in a high frequency ceramic package.

更に、トランジスタに限定されず、ＩＣのパッケージに
も利用することができる。Furthermore, it can be used not only for transistors but also for IC packages.

〔発明の効果〕〔Effect of the invention〕

本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

すなわち、ボンディングワイヤがポンディングされる外
部接続端子に予めＡｌ／ｉ＃を形成し念シリコン等の半
導体導電端子を接着し、上記Ａ１層とボンディングワイ
ヤとをボンティングする。この状態で、セラミックパッ
ケージを低融点フリットガラスを加熱溶融してセラミッ
クパッケージによる封止全行う。上記加熱溶融時に上記
ボンディング位置も加熱されるが、ボンディング位置に
Ａｕ成分がなく、パープルプレイブ現象が発生せず、ボ
ンディング位置の断線を防止し得るので、低コストが高
信頼性の半導体装置を得ることができる。That is, Al/i# is previously formed on the external connection terminal to which the bonding wire is bonded, a semiconductor conductive terminal made of silicon or the like is bonded, and the A1 layer and the bonding wire are bonded. In this state, the ceramic package is completely sealed with the ceramic package by heating and melting the low melting point frit glass. Although the bonding position is also heated during the heating and melting process, there is no Au component at the bonding position, no purple plaib phenomenon occurs, and disconnection at the bonding position can be prevented, resulting in a low-cost, high-reliability semiconductor device. Obtainable.

【図面の簡単な説明】[Brief explanation of drawings]

第１図〜第４図は本発明を適用した半導体装置の一実施
例を示すものであ）、 第１図は半導体装置の構造を示す断面図、第２図は半導
体装置の要部の拡大断面図、第３図は半導体装置の平面
図をそれぞれ示［２、第４図は半導体装置の製造工程の
要部を説明するフローチャートを示し、 第５図は本発明に先立って検討された半導体装置の一例
を示す斜視図、 第６図は上記第５図のＡ　−Ａ’線断面図を示すもので
ある。 １１・・・高周波パワーＭＯ８ＦＥＴ、１２・・・パッ
ケージ、１３・・・低融点７リツトガラス、　１４．１
５゜２１・・・外部接続端子、１７・・・半導体導電端
子、１８・・・ＡｕＳｉ共晶、１９・・・ＡＪ層、２２
・・・半導体チップ、２４・・・ボンディングワイヤ。 代理人　弁理士　　小　川　勝　男 ソー 第　　１　　図Figures 1 to 4 show an embodiment of a semiconductor device to which the present invention is applied), Figure 1 is a sectional view showing the structure of the semiconductor device, and Figure 2 is an enlarged view of the main parts of the semiconductor device. A cross-sectional view and a plan view of the semiconductor device are shown in FIG. A perspective view showing an example of the device. FIG. 6 is a sectional view taken along the line A-A' in FIG. 5. 11...High frequency power MO8FET, 12...Package, 13...Low melting point 7-lithium glass, 14.1
5゜21... External connection terminal, 17... Semiconductor conductive terminal, 18... AuSi eutectic, 19... AJ layer, 22
... Semiconductor chip, 24... Bonding wire. Agent Patent Attorney Masaru Ogawa Figure 1

Claims (1)

【特許請求の範囲】 １、（１）第１の外部接続端子の一端にＡｕＳｉ共晶体
を用いて導電可能に接着され、かつその表面のワイヤボ
ンディング位置にアルミニウムが施された半導体導電端
子と、 （２）第２の外部接続端子の一端にＡｕＳｉ共晶体を用
いて導電可能に接着され、かつワイヤボンディング位置
にアルミニウムによって形成された接続端子を有する半
導体チップと、 （３）上記半導体チップの接続端子と上記半導体導電端
子とを接続するアルミニュームよりなるボンディングワ
イヤと、 （４）上記第１および第２の外部接続端子の一部との接
着部、ならびに他のパッケージとの接着部がガラス封止
体を介して接着され、上記接着を行うことにより、上記
半導体チップ、上記半導体導電端子、上記ボンディング
ワイヤ、上記第１および第２の外部接続端子の一部を気
密封止するパッケージと、 をそれぞれ具備したことを特徴とする半導体装置。[Claims] 1. (1) A semiconductor conductive terminal which is electrically conductively bonded to one end of a first external connection terminal using an AuSi eutectic and whose surface is coated with aluminum at a wire bonding position; (2) a semiconductor chip that is conductively bonded to one end of a second external connection terminal using an AuSi eutectic and has a connection terminal made of aluminum at a wire bonding position; (3) connection of the semiconductor chip; A bonding wire made of aluminum that connects the terminal and the semiconductor conductive terminal, (4) an adhesive part with a part of the first and second external connection terminals, and an adhesive part with another package are sealed with glass. a package that is bonded via a stopper and that hermetically seals a portion of the semiconductor chip, the semiconductor conductive terminal, the bonding wire, and the first and second external connection terminals by performing the bonding; A semiconductor device characterized by each of the following.
JP61023740A 1986-02-07 1986-02-07 Semiconductor device Pending JPS62183133A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61023740A JPS62183133A (en) 1986-02-07 1986-02-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61023740A JPS62183133A (en) 1986-02-07 1986-02-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62183133A true JPS62183133A (en) 1987-08-11

Family

ID=12118703

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61023740A Pending JPS62183133A (en) 1986-02-07 1986-02-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62183133A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0415106A2 (en) * 1989-07-31 1991-03-06 Kabushiki Kaisha Toshiba Lead frames for semiconductor device
JPH05275964A (en) * 1991-11-15 1993-10-22 Oki Electric Ind Co Ltd Surface acoustic wave filter
JP2012233876A (en) * 2011-04-28 2012-11-29 Honeywell Internatl Inc Electronic ph sensor die packaging

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0415106A2 (en) * 1989-07-31 1991-03-06 Kabushiki Kaisha Toshiba Lead frames for semiconductor device
JPH05275964A (en) * 1991-11-15 1993-10-22 Oki Electric Ind Co Ltd Surface acoustic wave filter
JP2012233876A (en) * 2011-04-28 2012-11-29 Honeywell Internatl Inc Electronic ph sensor die packaging

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