KR100214857B1 - Multi-chip package - Google Patents

Multi-chip package Download PDF

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Publication number
KR100214857B1
KR100214857B1 KR1019960077724A KR19960077724A KR100214857B1 KR 100214857 B1 KR100214857 B1 KR 100214857B1 KR 1019960077724 A KR1019960077724 A KR 1019960077724A KR 19960077724 A KR19960077724 A KR 19960077724A KR 100214857 B1 KR100214857 B1 KR 100214857B1
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South Korea
Prior art keywords
semiconductor chip
package
tape
inner lead
chip
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KR1019960077724A
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Korean (ko)
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KR19980058400A (en
Inventor
강병영
Original Assignee
김영환
현대전자산업주식회사
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Priority to KR1019960077724A priority Critical patent/KR100214857B1/en
Publication of KR19980058400A publication Critical patent/KR19980058400A/en
Application granted granted Critical
Publication of KR100214857B1 publication Critical patent/KR100214857B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 멀티 칩 패키지에 관한 것으로, 하나의 패키지에 2개의 반도체 칩을 내장시킴으로써, 패키지의 메모리 용량을 증가시킬 수 있다. 본 발명의 멀티 칩 패키지는 리드 프레임의 패들에 탑재되고 본딩 패드에 범프가 형성된 제1반도체 칩과, 소정 회로가 형성되어 있고 상기 제1반도체 칩의 본딩 패드 상에 형성된 범프에 의해 접속되는 테이프와, 상기 테이프 위에 탑재된 제2반도체 칩과, 상기 제1 및 제2반도체 칩의 외부로의 전기적 신호 경로를 이루기 위한 리드 프레임의 인너 리드와, 상기 제2반도체 칩과 상기 인너 리드를 전기적으로 접속하기 위한 금속 와이어, 및 상기 테이프에 장기적으로 접속된 제1반도체 칩, 그 위에 탑재된 제2반도체 칩 및 인너 리드를 포함하는 일정 면적을 밀봉하고 있는 패키지 몸체를 포함하는 것을 특징으로 한다.The present invention relates to a multi-chip package, by embedding two semiconductor chips in one package, it is possible to increase the memory capacity of the package. The multi-chip package of the present invention includes a first semiconductor chip mounted on a paddle of a lead frame and having bumps formed on a bonding pad, and a tape connected by bumps formed on a bonding pad of a predetermined circuit and formed with a predetermined circuit. A second semiconductor chip mounted on the tape, an inner lead of a lead frame for forming an electrical signal path to the outside of the first and second semiconductor chips, and an electrical connection between the second semiconductor chip and the inner lead And a package body sealing a predetermined area including a first metal chip, a second semiconductor chip mounted thereon, and an inner lead connected to the tape for a long time.

Description

멀티 칩 패키지Multi-chip package

본 발명은 반도체 패키지에 관한 것으로, 보다 상세하게는, 하나의 패키지에 패키지의 용량을 증가시키기 위하여 회로가 형성된 테이프를 이용하는 멀티 칩 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a multi-chip package using tape in which a circuit is formed to increase the capacity of the package in one package.

일반적으로, 통상의 방법에 의해 형성된 집적회로 칩은 조립공정으로 보내져서 칩절단,칩부착, 와이어 본딩, 몰드, 포밍, 트림공정 등의 공정을 순서적으로 거쳐 패키지화 된다.In general, an integrated circuit chip formed by a conventional method is sent to an assembly process and packaged through a sequence such as chip cutting, chip attaching, wire bonding, mold, forming, and trimming.

이러한 반도체 패키지는 도 1에 도시된 바와 같이, 리드 프레임의 패들(2a)상에 반도체 칩(1)이 접착제(3)에 의해 부착되고, 상기 반도체 칩(1)은 금속 와이어(4)에 의해 리드 프레임의 인너 리드(2b)와 전기적으로 접속되며, 상기 반도체 칩(1), 인너 리드(2b) 및 금속 와이어(4)를 포함하는 일정 면적이 몰딩 컴파운드에 의해 밀봉되어 패키지 몸체(5)가 형성된다.In this semiconductor package, as shown in FIG. 1, a semiconductor chip 1 is attached by an adhesive 3 on a paddle 2a of a lead frame, and the semiconductor chip 1 is attached by a metal wire 4. Electrically connected to the inner lead 2b of the lead frame, a predetermined area including the semiconductor chip 1, the inner lead 2b and the metal wire 4 is sealed by the molding compound so that the package body 5 is closed. Is formed.

이후에 패키지 몸체(5)의 외측으로 돌출되어 있는 상기 리드 프레임의 아웃리드(2c)를 소정의 형태를 갖도록 하는 트림/포밍 공정이 실시된다.Subsequently, a trim / forming process is performed in which the outlead 2c of the lead frame protruding outward of the package body 5 has a predetermined shape.

그러나, 상기와 같은 종래 기술은, 하나의 패키지에 한개의 반도체 칩이 내장되기 때문에 패키지의 메모리 용량을 확장시키는데 한계가 있는 문제점이 있었다.However, the prior art as described above has a problem in that the memory capacity of the package is limited because one semiconductor chip is embedded in one package.

따라서, 본 발명은 제1반도체 칩의 본딩 패드 상에 범프를 형성하고, 이 범프를 이용하여 회로가 형성된 테이프와 접속한 후, 상기 테이프를 인너 리드와 접속시켜 외부와 전기적으로 연결하고,상기 테이프 위에 제2반도체 칩을 탑재시킨 후, 상기 제2반도체 칩은 금속 와이어를 이용하여 상기 인너 리드와 전기적으로 접속함으로써, 패키지의 용량을 증가시킬 수 있는 멀티 칩 패키지를 제공하는 것을 목적으로 한다.Accordingly, the present invention is to form a bump on the bonding pad of the first semiconductor chip, and to connect with the tape formed circuit using the bump, and then to connect the tape to the inner lead and electrically connected to the outside, the tape After mounting the second semiconductor chip thereon, the second semiconductor chip is to provide a multi-chip package that can increase the capacity of the package by electrically connecting to the inner lead using a metal wire.

제1도는 종래 기술에 따른 반도체 패키지를 설명하기 위한 단면도.1 is a cross-sectional view illustrating a semiconductor package according to the prior art.

제2도는 본 발명에 따른 테이프를 설명하기 위한 도면.2 is a view for explaining a tape according to the present invention.

제3도는 본 발명에 따른 멀티 칩 패키지를 설명하기 위한 공정 단면도.3 is a cross-sectional view illustrating a multi-chip package according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 테이프 12a : 패들11: tape 12a: paddle

12b : 인너 리드 13 : 제1반도체 칩12b: inner lead 13: first semiconductor chip

14 : 제2반도체 칩 15 : 금속와이어14 second semiconductor chip 15 metal wire

16 : 패키지 몸체 20 : 기판16: package body 20: substrate

21 : 범프21: bump

상기와 같은 목적은, 리드 프레임의 패들에 탑재되고 본딩 패드에 범프가 형성된 제1반도체 칩과, 소정 회로가 형성되어 있고 상기 제1반도체 칩의 본딩 패드 상에 형성된 범프에 의해 접속되는 테이프와, 상기 테이프 위에 탑재된 제2반도체 칩과, 상기 제1 및 제2반도체 칩의 외부로의 전기적 신호 경로를 이루기 위한 리드 프레임의 인너 리드와, 상기 제2반도체 칩과 상기 인너리드를 전기적으로 접속하기 위한 금속 와이어, 및 상기 테이프에 전기적으로 접속된 제 1 반도체 칩, 그 위에 탑재된 제 2 반도체 칩 및 인너 리드를 포함하는 일정 면적을 밀봉하고 있는 패키지 몸체를 포함하는 것을 특징으로 하는 본 발명에 따른 멀티 칩 패키지에 의하여 달성된다.The above object is the first semiconductor chip is mounted on the paddle of the lead frame and the bump is formed on the bonding pad, the tape is formed by a bump formed on the bonding pad of the first semiconductor chip, and the tape is connected; Electrically connecting a second semiconductor chip mounted on the tape, an inner lead of a lead frame to form an electrical signal path to the outside of the first and second semiconductor chips, and the second semiconductor chip and the inner lead And a package body sealing a predetermined area including a metal wire, and a first semiconductor chip electrically connected to the tape, a second semiconductor chip mounted thereon and an inner lead. Achieved by a multi-chip package.

본 발명에 따르면, 하나의 패키지에 2개의 반도체 패키지를 탑재시킴으로써, 메모리의 용량을 증가시킬 수 있다.According to the present invention, by mounting two semiconductor packages in one package, the capacity of the memory can be increased.

[실시예]EXAMPLE

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

도 2는 본발명에 따른 테이프를 설명하기 위한 도면으로써, 테이프(11)는 절연성 및 접착력을 갖는 기판(20)에 반도체 칩의 본딩 패드와 일치되는 소정의 회로가 형성되어 있으며, 상기 테이프(11)의 소정 부분, 즉, 리드 프레임의 인너 리드와 접속되는 부분에는 Au 또는 Pb/Sn과 같은 전도성 물질로 이루어진 범프(21)가 형성된다.2 is a view for explaining a tape according to the present invention. In the tape 11, a predetermined circuit is formed on a substrate 20 having insulating property and adhesion, and is matched with a bonding pad of a semiconductor chip. A bump 21 made of a conductive material such as Au or Pb / Sn is formed at a predetermined portion of the lead, that is, the portion connected to the inner lead of the lead frame.

도 3은 본 발명에 따른 멀티 칩 패키지를 설명하기 위한 공정 단면도로써, 먼저, 소정의 회로가 형성된 테이프(11)는 그의 소정 부분에 형성된 범프에 의해 리드 프레임의 인너 리드(12b)와 접속되고, 이어서, 리드 프레임의 패들(12a) 위에 탑재된 제1반도체 칩(13)은 그의 본딩 패드 상에 형성된 범프를 이용하여 상기 테이프(11)와 접속시킨다.3 is a cross-sectional view for explaining a multi-chip package according to the present invention. First, a tape 11 having a predetermined circuit is connected to an inner lead 12b of a lead frame by bumps formed at a predetermined portion thereof. Subsequently, the first semiconductor chip 13 mounted on the paddle 12a of the lead frame is connected to the tape 11 using bumps formed on the bonding pads thereof.

그리고 나서, 상기 테이프(11)의 윗면에 제2반도체 칩(14)을 탑재시킨 후,상기 제2반도체 칩(14)은 그의 본딩 패드와 상기 인너 리드가 금속 와이어에 의해 본딩되어 외부와의 전기적 신호 전달 경로를 형성하게 된다.Then, after mounting the second semiconductor chip 14 on the upper surface of the tape 11, the second semiconductor chip 14 is bonded to the bonding pad and the inner lead by a metal wire to the electrical It forms a signal transmission path.

마지막으로, 몰딩 컴파운드를 사용하여 상기 결과물의 일정 면적을 밀봉하는 패키지 몸체(16)을 형성한다. 이때, 상기 제1반도체 칩(13)가 탑재된 리드 프레임의 패들(12a)의 밑면은 밀봉되지 않기 때문에 상기 반도체 칩의 동작시 발생되는 열을 패키지의 외부로 신속하게 방출시킬 수 있다.Finally, the molding compound is used to form a package body 16 that seals a certain area of the resulting product. At this time, since the bottom surface of the paddle 12a of the lead frame on which the first semiconductor chip 13 is mounted is not sealed, heat generated during operation of the semiconductor chip can be quickly released to the outside of the package.

이상에서와 같이, 본 발명의 멀티 칩 패키지는 하나의 패키지에 하나 이상의 반도체 칩을 내장시키기 때문에 패키지의 메모리 용량을 증가시킬 수 있으며, 또한, 리드 프레임의 패들이 패키지의 외부로 노출되도록 형성함으로써, 반도체 칩의 동작시 발생되는 열을 외부로 신속하게 방출시켜 소자의 특성 저하를 방지할 수 있다.As described above, the multi-chip package of the present invention can increase the memory capacity of the package because one or more semiconductor chips are embedded in one package, and by forming the paddle of the lead frame to be exposed to the outside of the package, The heat generated during the operation of the semiconductor chip can be quickly released to the outside to prevent deterioration of device characteristics.

한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (3)

리드 프레임의 패들에 탑재되고, 본딩 패드에 범프가 형성된 제1반도체 칩과, 소정 회로가 형성되어 있고, 상기 제1반도체 칩의 본딩 패드 상에 형성된 범프에 의해 접속되는 테이프와, 상기 테이프 위에 탑재된 제2반도체 칩과, 상기 제1 및 제2반도체 칩의 외부로의 전기적 신호 경로를 이루기 위한 리드 프레임의 인너 리드와 상기 제2반도체 칩과 상기 인너 리드를 전기적으로 접속하기 위한 금속 와이어, 및 상기 테이프에 전기적으로 접속된 제1반도체 칩, 그 위에 탑재된 제2반도체 칩 및 인너 리드를 포함하는 일정 면적을 밀봉하고 있는 패키지 몸체를 포함하는 것을 특징으로 하는 멀티 칩 패키지.A first semiconductor chip mounted on a paddle of a lead frame and having bumps formed on a bonding pad, a tape formed with a predetermined circuit, and connected by a bump formed on a bonding pad of the first semiconductor chip, and mounted on the tape A second semiconductor chip, an inner lead of a lead frame for forming an electrical signal path to the outside of the first and second semiconductor chips, and a metal wire for electrically connecting the second semiconductor chip and the inner lead; And a package body sealing a predetermined area including a first semiconductor chip electrically connected to the tape, a second semiconductor chip mounted thereon, and an inner lead. 제1항에 있어서, 상기 인너 리드와 테이프의 접속은 Au 또는 Pb/Sn과 같은 전도성 물질로 형성된 범프를 이용하는 것을 특징으로 하는 멀티 칩 패키지.The multi-chip package according to claim 1, wherein the inner lead and the tape are connected to each other using bumps formed of a conductive material such as Au or Pb / Sn. 제1항에 있어서, 상기 패키지 몸체는 몰딩 공정시 패들의 밑면이 외부로 노출되도록 형성하는 것을 특징으로 하는 멀티 칩 패키지.The multi-chip package of claim 1, wherein the package body is formed such that a bottom surface of the paddle is exposed to the outside during a molding process.
KR1019960077724A 1996-12-30 1996-12-30 Multi-chip package KR100214857B1 (en)

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