JPH05152495A - Semiconductor devices - Google Patents
Semiconductor devicesInfo
- Publication number
- JPH05152495A JPH05152495A JP3310783A JP31078391A JPH05152495A JP H05152495 A JPH05152495 A JP H05152495A JP 3310783 A JP3310783 A JP 3310783A JP 31078391 A JP31078391 A JP 31078391A JP H05152495 A JPH05152495 A JP H05152495A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- resin
- external
- semiconductor device
- sealing body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に、面実装型半導体装置に適用して有効な技術に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a surface mount type semiconductor device.
【０００２】[0002]
【従来の技術】樹脂封止型（レジンモールド型）半導体
装置はそれを組み込む外部機器の小型化かつ薄肉化の傾
向から面実装型かつ薄型の要求が高い。このような要求
からＴＳＯＰ（Ｔhin Ｓmall Ｏutline Ｐackage）構
造、ＴＱＦＰ（Ｔhin Ｑuad Ｆlat Ｐackage）構造等の
薄型の面実装型の樹脂封止型半導体装置が開発されてい
る。この種の構造を採用する樹脂封止型半導体装置は、
例えば全体の厚さが１.０〜１.５ 〔ｍｍ〕の薄型で構
成され、従来の面実装型の樹脂封止型半導体装置の厚さ
に比べて約２分の１〜３分の１の薄型で構成される。2. Description of the Related Art A resin-sealed type (resin mold type) semiconductor device is highly required to be a surface mount type and a thin type because an external device incorporating the resin device tends to be smaller and thinner. Such TSOP from the request (T hin S mall O utline P ackage) structure, TQFP (T hin Q uad F lat P ackage) thin surface mounting type resin-sealed semiconductor device such as a structure has been developed. A resin-sealed semiconductor device that employs this type of structure is
For example, the overall thickness is 1.0 to 1.5 [mm], which is thin, and is about 1/2 to 1/3 of the thickness of the conventional surface mount type resin-sealed semiconductor device. It is composed of a thin type.
【０００３】この薄型の樹脂封止型半導体装置は、一般
的に、ダイパッドに搭載された半導体ペレットの外部端
子（ボンディングパッド）に内部リードが電気的に接続
され、これらの半導体ペレット及び内部リードが樹脂封
止体で封止される。ダイパッド、半導体ペレットの夫々
は樹脂ペ−スト、半田、Ａｕ−Ｓｉ共晶合金等のいずれ
かの接着層を介在して固着される。半導体ペレットの外
部端子、内部リードの夫々は例えば直径約３０〔μｍ〕
のＡｕ線（Ａｕワイヤ）を通して電気的に接続される。
半導体ペレットの外部端子は一般的にＡｌ合金で構成さ
れる。内部リードはＦｅ−Ｎｉ合金で構成され、この内
部リードのＡｕ線が接続される領域はＡｇメッキ処理さ
れる。樹脂封止体は、低圧トランスファーモールド法で
成型され、エポキシ系樹脂に石英粉、硬化剤、難燃剤、
離型剤等を配合した半導体用熱硬化樹脂で形成される。
前記内部リードは外部リードに電気的に接続され（一体
に構成され）、この外部リードは樹脂封止体の外部側面
周囲に複数本配列される。In this thin resin-encapsulated semiconductor device, generally, internal leads are electrically connected to the external terminals (bonding pads) of the semiconductor pellets mounted on the die pad, and these semiconductor pellets and internal leads are connected to each other. It is sealed with a resin sealing body. The die pad and the semiconductor pellet are fixed by interposing an adhesive layer of any one of resin paste, solder, Au-Si eutectic alloy and the like. Each of the external terminals and the internal leads of the semiconductor pellet has a diameter of, for example, about 30 [μm].
Are electrically connected through the Au wire (Au wire).
The external terminals of the semiconductor pellet are generally made of Al alloy. The inner lead is made of Fe-Ni alloy, and the region of the inner lead to which the Au wire is connected is Ag-plated. The resin encapsulant is molded by the low-pressure transfer molding method, and is made of epoxy resin with quartz powder, curing agent, flame retardant,
It is formed of a thermosetting resin for semiconductors containing a release agent or the like.
The inner leads are electrically connected to the outer leads (integrally configured), and a plurality of the outer leads are arranged around the outer side surface of the resin sealing body.
【０００４】前記樹脂封止型半導体装置は、組立プロセ
スにおいて、リードフレームのダイパッドに半導体ペレ
ットを搭載し、Ａｕ線をボンディングし、そして樹脂封
止体を成型した後、リードフレームから外部リードが切
断されるとともに、外部リードが面実装型のリードとし
て成型される。この樹脂封止型半導体装置は、その外部
リードと外部機器に組込まれる実装基板例えばプリント
配線基板の端子との間に半田接着層を介在し、このプリ
ント配線基板に実装される。In the resin encapsulation type semiconductor device, in the assembly process, the semiconductor pellets are mounted on the die pad of the lead frame, the Au wire is bonded, and the resin encapsulant is molded, and then the external lead is cut from the lead frame. At the same time, the external leads are molded as surface-mounted leads. This resin-encapsulated semiconductor device is mounted on a printed wiring board with a solder adhesive layer interposed between the external lead and a mounting board incorporated in an external device, for example, a terminal of the printed wiring board.
【０００５】なお、ＴＳＯＰ構造を採用する樹脂封止型
半導体装置については、例えば日経マイクロデバイセ
ス、１９９０年６月号、第３４頁乃至第６２頁に記載さ
れる。The resin-encapsulated semiconductor device adopting the TSOP structure is described, for example, in Nikkei Micro Devices, June 1990, pp. 34-62.
【０００６】[0006]
【発明が解決しようとする課題】前述のＴＳＯＰ構造又
はＴＱＦＰ構造を採用する樹脂封止型半導体装置は、プ
リント配線基板に実装後に行われる温度サイクル試験に
おいて、半田接着層に損傷や破壊が発生し、断線不良若
しくは実装不良が多発した。本発明者が行った不良解析
によれば、以下の原因である結論に達した。The resin-sealed semiconductor device adopting the TSOP structure or the TQFP structure described above does not suffer damage or destruction in the solder adhesive layer in the temperature cycle test performed after mounting on the printed wiring board. , Disconnection failure or mounting failure occurred frequently. According to the failure analysis conducted by the present inventor, the following causes have been reached.
【０００７】樹脂封止型半導体装置の半導体ペレット、
樹脂封止体、内部リード、外部リード、さらに実装され
るプリント配線基板の夫々の熱膨張係数差に起因し、応
力が発生する。特に、ＤＲＡＭ（Ｄynamic Ｒandom Ａc
cess Ｍemory）等の記憶回路システムが搭載される半導
体ペレットにおいては、情報記憶容量の増大に基づき、
半導体ペレットのサイズが大型化の傾向にある（樹脂封
止体の占有面積に対する半導体ペレットの占有面積の割
合が大きくなる）。また、樹脂封止型半導体装置は、薄
型化の要求に基づき、半導体ペレットの厚さ自体も多少
薄く構成されるが、その薄くされる割合に対して樹脂封
止体の厚さを薄くする割合が大きい。このため、樹脂封
止体の実際の割合が極端に減少され、樹脂封止体のクラ
ックの発生を防止する（パッケージクラックを防止す
る）目的から、樹脂封止体は半導体ペレットの熱膨張係
数に近い低熱膨張係数化された材料が使用され、益々プ
リント配線基板（例えば、ガラス−エポキシ系樹脂）と
の熱膨張係数に開きが発生した。このような技術動向に
加えて、ＴＳＯＰ構造又はＴＱＦＰ構造を採用する樹脂
封止型半導体装置は、実装密度の向上及び外部リ−ドの
曲がりの低減から、外部リードのリード長さが短くさ
れ、外部リードで前述の応力が吸収できないので、前述
の不良が顕著化される。A semiconductor pellet of a resin-sealed semiconductor device,
Stress is generated due to the difference in thermal expansion coefficient between the resin sealing body, the internal leads, the external leads, and the printed wiring board to be mounted. In particular, DRAM (D ynamic R andom A c
In cess M emory) semiconductor pellet storage circuit system are mounted such on the basis of the increase in information storage capacity,
The size of the semiconductor pellet tends to increase (the ratio of the area occupied by the semiconductor pellet to the area occupied by the resin encapsulant increases). Also, in the resin-encapsulated semiconductor device, the thickness of the semiconductor pellet itself is configured to be a little thin based on the demand for thinning. Is big. Therefore, the actual ratio of the resin encapsulant is extremely reduced, and the resin encapsulant has a coefficient of thermal expansion of the semiconductor pellet for the purpose of preventing the occurrence of cracks in the resin encapsulant (preventing package cracks). A material having a low coefficient of thermal expansion was used, and the coefficient of thermal expansion with the printed wiring board (for example, glass-epoxy resin) was more and more widened. In addition to such technological trends, resin-encapsulated semiconductor devices adopting the TSOP structure or the TQFP structure have shorter lead lengths of external leads because of improved packaging density and reduced bending of the external leads. Since the above-mentioned stress cannot be absorbed by the external lead, the above-mentioned defect becomes remarkable.
【０００８】また、前述の断線不良や実装不良を防止す
る技術として、外部リードの板厚を薄くする、軟化す
る、接着面積を広げる、プリント配線基板の材質を変え
る等の技術の採用が考えられる。しかしながら、このよ
うな技術の採用は、加工コスト、材料コストのいずれも
が増加となり、樹脂封止型半導体装置の製品コストが増
大するばかりか、プリント配線基板の実装密度の低下
や、リードフレームの機械的強度不足を招くことにな
る。Further, as a technique for preventing the above-mentioned disconnection defect and mounting defect, it is possible to adopt a technique of thinning the external lead, softening it, widening the bonding area, changing the material of the printed wiring board, or the like. .. However, the adoption of such a technique increases both the processing cost and the material cost, which not only increases the product cost of the resin-encapsulated semiconductor device but also lowers the mounting density of the printed wiring board and reduces the lead frame. This leads to insufficient mechanical strength.
【０００９】本発明の目的は、面実装型半導体装置にお
いて、応力の吸収作用を付加することが可能な技術を提
供することにある。An object of the present invention is to provide a technique capable of adding a stress absorbing action to a surface-mounted semiconductor device.
【００１０】本発明の他の目的は、面実装型半導体装置
において、前記目的を達成するとともに、実装時の断線
不良若しくは実装不良を防止することが可能な技術を提
供することにある。Another object of the present invention is to provide a surface-mounting type semiconductor device which can achieve the above-mentioned object and can prevent disconnection failure or mounting failure during mounting.
【００１１】本発明の他の目的は、面実装型半導体装置
において、前記目的を達成するとともに、放熱効果を向
上することが可能な技術を提供することにある。Another object of the present invention is to provide a technique capable of achieving the above-mentioned object and improving the heat dissipation effect in a surface-mounted semiconductor device.
【００１２】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【００１３】[0013]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記のとおりである。Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
【００１４】（１）半導体ペレットを封止する封止体の
外部側面周囲の少なくとも一部の領域に前記半導体ペレ
ットの外部端子に電気的に接続される外部リードが複数
本配列される面実装型半導体装置において、前記外部リ
ードの一端側の実装時にリードを取り付けるリード取付
け下面から他端側の封止体との境界部までの間のリード
高さ寸法が、前記封止体の前記リード高さの方向と一致
する方向の厚さ寸法に比べて大きく構成される。(1) A surface mount type in which a plurality of external leads electrically connected to the external terminals of the semiconductor pellet are arranged in at least a part of the area around the external side surface of the sealing body for sealing the semiconductor pellet. In the semiconductor device, the lead height dimension from the lead mounting lower surface to which the lead is mounted when mounting the one end side of the external lead to the boundary with the sealing body on the other end side is the lead height of the sealing body. It is configured to be larger than the thickness dimension in the direction corresponding to the direction.
【００１５】（２）前記手段（１）に記載の外部リード
の他端側は、封止体の外部側面周囲から封止体の外部上
面に沿って延在され、封止体の外部上面において内部リ
ードに電気的に接続される。(2) The other end side of the external lead described in the above-mentioned means (1) extends from around the outer side surface of the sealing body along the outer upper surface of the sealing body, and at the outer upper surface of the sealing body. Electrically connected to internal leads.
【００１６】[0016]
【作用】上述した手段（１）によれば、以下の作用効果
が得られる。 （Ａ）前記外部リードのリード取付け面（実装時基準面
又はシーティングプレーン：sheeting plane）から封止
体の境界部までの間のリード長さを長くしたので、この
外部リードに機械的応力の吸収作用を付加できる。この
結果、半導体装置の外部リードを半田接着層を介在して
実装基板に実装した際、半導体装置の半導体ペレット、
封止体、内部リード、外部リード、実装基板の夫々の熱
膨張係数差に起因して発生する応力が、半導体装置の外
部リードで吸収できるので、温度サイクル（試験時、実
使用時のいずれも含む）による半田接着層の損傷や破壊
を防止し、半田断線不良若しくは実装不良を防止でき
る。 （Ｂ）前記外部リードのリード長さを外部リードの高さ
方向に稼ぐので、封止体の占有面積及び外部リードの配
置の占有面積を含む半導体装置の全体の占有面積を縮小
し、半導体装置の小型化を図れる。 （Ｃ）前記外部リードのリード長さを長くするだけで、
外部リードの板厚を薄くする加工、外部リードを軟化す
る加工等の加工を行う必要がないので、これらの加工コ
ストに相当する分、半導体装置の製造コストを低減でき
る。また、外部リードにこれらの加工を施さないので、
外部リードの根本的な機械的強度の不足を防止できる。
上述した手段（２）によれば、前記封止体の外部上面に
沿って延在する分、外部リードのリード長さを長くで
き、半導体ペレットに搭載された回路システムの回路動
作で発生する熱の放熱面積を増加できるので、又前記封
止体の外部上面に沿って延在する分、内部リードの長さ
（外部までの熱放出経路の長さ）を短くでき、半導体ペ
レットに搭載された回路システムと外部リードの他端側
までの間の熱抵抗を小くできるので、半導体装置の放熱
効果を向上できる。According to the above-mentioned means (1), the following operational effects can be obtained. (A) Since the lead length between the lead mounting surface (mounting reference surface or sheeting plane) of the external lead and the boundary of the sealing body is increased, the external lead absorbs mechanical stress. The action can be added. As a result, when the external leads of the semiconductor device are mounted on the mounting board with the solder adhesive layer interposed, the semiconductor pellet of the semiconductor device,
The stress generated due to the difference in thermal expansion coefficient between the encapsulation body, the internal leads, the external leads, and the mounting board can be absorbed by the external leads of the semiconductor device, so that the temperature cycle (during test or actual use is either It is possible to prevent damage or destruction of the solder adhesive layer due to (including) and to prevent solder disconnection failure or mounting failure. (B) Since the lead length of the external lead is earned in the height direction of the external lead, the overall occupied area of the semiconductor device including the occupied area of the sealing body and the occupied area of the arrangement of the external lead is reduced, and the semiconductor device is reduced. Can be miniaturized. (C) Only by increasing the lead length of the external lead,
Since it is not necessary to perform processing such as processing for thinning the thickness of the external leads and processing for softening the external leads, the manufacturing cost of the semiconductor device can be reduced by an amount corresponding to these processing costs. Also, since these processes are not applied to the external leads,
The fundamental lack of mechanical strength of the external leads can be prevented.
According to the above-mentioned means (2), the length of the lead of the external lead can be increased by the amount of extending along the outer upper surface of the sealing body, and the heat generated by the circuit operation of the circuit system mounted on the semiconductor pellet can be increased. Since the heat dissipation area can be increased, the length of the internal leads (the length of the heat dissipation path to the outside) can be shortened by extending along the outer upper surface of the encapsulant, so that it can be mounted on the semiconductor pellet. Since the thermal resistance between the circuit system and the other end of the external lead can be reduced, the heat dissipation effect of the semiconductor device can be improved.
【００１７】以下、本発明の構成について、ＴＳＯＰ構
造（又はＴＱＦＰ構造）を採用する面実装型の樹脂封止
型半導体装置に本発明を適用した、一実施例とともに説
明する。The structure of the present invention will be described below with reference to an embodiment in which the present invention is applied to a surface mount type resin-sealed semiconductor device adopting a TSOP structure (or TQFP structure).
【００１８】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, parts having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.
【００１９】[0019]
【実施例】本発明の一実施例であるＴＳＯＰ構造を採用
する樹脂封止型半導体装置の構成を図１（断面図）で示
す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 (cross-sectional view) shows the structure of a resin-sealed semiconductor device adopting a TSOP structure which is an embodiment of the present invention.
【００２０】図１に示すように、ＴＳＯＰ構造（又はＴ
ＱＦＰ構造）を採用する樹脂封止型半導体装置１は、半
導体ペレット２の外部端子（ボンディングパッド）２Ａ
に内部リード３Ａが電気的に接続され、この半導体ペレ
ット２及び内部リード３Ａが樹脂封止体６で封止され
る。As shown in FIG. 1, the TSOP structure (or T
The resin-encapsulated semiconductor device 1 adopting the QFP structure has an external terminal (bonding pad) 2A of the semiconductor pellet 2.
The internal lead 3A is electrically connected to, and the semiconductor pellet 2 and the internal lead 3A are sealed with the resin sealing body 6.
【００２１】前記半導体ペレット２は平面方形状（本実
施例においては長方形状）で形成される単結晶珪素基板
で構成される。これに限定されないが、半導体ペレット
２の表面（図１中、上側表面）にはＤＲＡＭが搭載さ
れ、このＤＲＡＭは１６〔Ｍbit〕、６４〔Ｍbit〕又は
それ以上の情報記憶容量を有する。外部端子２Ａは半導
体ペレット２の表面つまりＤＲＡＭが搭載される表面上
に複数配列される。本実施例の樹脂封止型半導体装置１
は、この構造に限定されないが、半導体ペレット２の表
面上に内部リード３Ａを引き回す ＬＯＣ（Ｌead Ｏn
Ｃhip）構造が採用されるので、外部端子２Ａは半導体
ペレット２の表面の中央領域に配列される。外部端子２
Ａは例えばＤＲＡＭの複数個の回路間、素子間の夫々を
結線する配線と同様のＡｌ合金で形成される。前記半導
体ペレット２は、ダイシング工程前の状態の半導体ウエ
ーハ自体が薄く形成され、若しくは半導体ウエーハの裏
面を研磨加工することにより薄く形成され、例えば０.
２５〜０.４０〔ｍｍ〕の厚さで形成される。The semiconductor pellet 2 has a flat rectangular shape (actual
Single crystal silicon substrate formed in a rectangular shape in the example)
Composed of. Semiconductor pellets include, but are not limited to
DRAM is mounted on the surface of No. 2 (upper surface in FIG. 1).
This DRAM is 16 [Mbit], 64 [Mbit] or
It has more information storage capacity. External terminal 2A is semi-conductive
On the surface of the body pellet 2, that is, the surface on which the DRAM is mounted
It is arranged in multiple. Resin-encapsulated semiconductor device 1 of this embodiment
Is not limited to this structure.
Locating the internal lead 3A on the surface LOC (LeadOn
CSince the hip) structure is adopted, the external terminal 2A is a semiconductor
The pellets 2 are arranged in the central area of the surface. External terminal 2
A indicates, for example, between a plurality of circuits of DRAM and between elements.
It is formed of an Al alloy similar to the wiring to be connected. The semi-conductor
The body pellet 2 is a semiconductor wafer in a state before the dicing process.
-The wafer itself is thinly formed, or the backside of the semiconductor wafer
It is thinly formed by polishing the surface, for example,
It is formed with a thickness of 25 to 0.40 [mm].
【００２２】前記半導体ペレット２の外部端子２Ａ、内
部リード３Ａの夫々はワイヤ５を通して電気的に接続さ
れる。内部リード３Ａは、Ｆｅ−Ｎｉ合金（例えば、Ｎ
ｉ含有量が４２若しくは５０〔％〕、又はＣｕ若しくは
その合金を使用してもよい）で形成され、例えば０.１
２〜０.１５〔ｍｍ〕の板厚で形成される。ワイヤ５は
例えばＡｕワイヤが使用され、このＡｕワイヤは直径約
３０〔μｍ〕のものが使用される。このワイヤ５は例え
ば熱圧着に超音波振動を併用したボンディング法でボン
ディングされる。また、内部リード３Ａのワイヤ５がボ
ンディングされる領域は、ボンダビリティを向上する目
的で、Ａｇメッキ層が形成される。The external terminals 2A and the internal leads 3A of the semiconductor pellet 2 are electrically connected through wires 5. The inner lead 3A is made of a Fe-Ni alloy (for example, N
i content is 42 or 50 [%], or Cu or its alloy may be used), for example, 0.1
It is formed with a plate thickness of 2 to 0.15 [mm]. As the wire 5, for example, an Au wire is used, and the Au wire having a diameter of about 30 [μm] is used. The wire 5 is bonded by, for example, a bonding method using thermocompression and ultrasonic vibration. In addition, an Ag plating layer is formed in a region of the inner lead 3A to which the wire 5 is bonded for the purpose of improving bondability.
【００２３】内部リード３Ａは、半導体ペレット２の表
面上に配置され、接着フィルム層４を介在して半導体ペ
レット２の表面に接着される。接着フィルム層４は例え
ば絶縁性を有するポリイミド系樹脂を主体に構成され
る。The internal lead 3A is arranged on the surface of the semiconductor pellet 2 and adhered to the surface of the semiconductor pellet 2 with the adhesive film layer 4 interposed therebetween. The adhesive film layer 4 is mainly composed of, for example, an insulating polyimide resin.
【００２４】前記内部リード３Ａは外部リード３Ｂの一
端側に電気的に接続されかつ一体に構成される。この内
部リード３Ａ、外部リード３Ｂの夫々は同一リードフレ
ーム３から切断され、外部リード３Ｂはガルウィング形
状に成型される。外部リード３Ｂは樹脂封止体６の外部
側面にこの側面に沿って複数本配列される。本実施例の
ＴＳＯＰ構造を採用する樹脂封止型半導体装置１は、樹
脂封止体６が長方体形状で構成されるので、相互に対向
する２個の外側面、図１中、右側の外側面、左側の外側
面の夫々に沿って夫々複数本の外部リード３Ａが配列さ
れる。また、図示しないが、ＴＱＦＰ構造を採用する樹
脂封止型半導体装置１においては、４個の外側面の夫々
に沿って夫々複数本の外部リード３Ａが配列される。The inner lead 3A is electrically connected to one end of the outer lead 3B and is integrally formed. The inner lead 3A and the outer lead 3B are cut from the same lead frame 3, and the outer lead 3B is molded into a gull wing shape. A plurality of external leads 3B are arranged on the outer side surface of the resin sealing body 6 along the side surface. In the resin-encapsulated semiconductor device 1 adopting the TSOP structure of the present embodiment, since the resin encapsulation body 6 is formed in a rectangular parallelepiped shape, the two outer surfaces facing each other, that is, the right side in FIG. A plurality of external leads 3A are arranged along the outer surface and the left outer surface, respectively. Although not shown, in the resin-encapsulated semiconductor device 1 employing the TQFP structure, a plurality of external leads 3A are arranged along each of the four outer surfaces.
【００２５】前記樹脂封止体６は、低圧トランスファー
モールド法で成型され、エポキシ系樹脂に石英粉、硬化
剤、難燃剤、離型剤等を配合した半導体用熱硬化樹脂で
形成される。The resin encapsulant 6 is molded by a low pressure transfer molding method, and is formed of a thermosetting resin for semiconductor in which quartz powder, a curing agent, a flame retardant, a release agent, etc. are mixed with an epoxy resin.
【００２６】このＴＳＯＰ構造を採用する樹脂封止型半
導体装置１は、組立プロセスにおいて、リードフレーム
３の内部リード３Ａ、半導体ペレット２の夫々を接着
し、ワイヤ５をボンディングし、そして樹脂封止体６を
成型した後、リードフレーム３から外部リード３Ｂが切
断されるとともに、外部リード３Ｂが成型される。In the resin-encapsulated semiconductor device 1 adopting this TSOP structure, in the assembly process, the internal leads 3A of the lead frame 3 and the semiconductor pellet 2 are bonded together, the wires 5 are bonded, and the resin-encapsulated body is formed. After molding 6, the external lead 3B is cut from the lead frame 3 and the external lead 3B is molded.
【００２７】前記ＴＳＯＰ構造を採用する樹脂封止型半
導体装置１は、その外部リード３Ｂと外部機器に組込ま
れるプリント配線基板８の端子８Ａとの間に半田接着層
７を介在し、このプリント配線基板８に実装される。In the resin-encapsulated semiconductor device 1 adopting the TSOP structure, the solder adhesive layer 7 is interposed between the external lead 3B and the terminal 8A of the printed wiring board 8 incorporated in the external equipment, and the printed wiring is formed. It is mounted on the substrate 8.
【００２８】このように構成されるＴＳＯＰ構造を採用
する樹脂封止型半導体装置１は、図１及び図２（要部拡
大断面図）に示すように、外部リード３Ｂの高さ寸法ｈ
１が樹脂封止体６の厚さ寸法ｈ２に比べて大きく構成さ
れる。高さ寸法ｈ１は、プリント配線基板８の実装面か
らの垂線と一致する方向において、プリント配線基板８
の端子８Ａに取り付けられる取付け下面（実装時基準面
又はシーティングプレーン：sheeting plane）から樹脂
封止体６の境界部までの間の寸法である。厚さ寸法ｈ２
は、高さ寸法ｈ１と一致する方向において、樹脂封止体
６の上面とそれに対向する下面との間の寸法である。具
体的に、高さ寸法ｈ１は １.２〔ｍｍ〕、厚さ寸法ｈ２
は １.０〔ｍｍ〕の夫々に設定される。また、別の表現
をすれば、樹脂封止体６のそれと外部リード３Ｂとの境
界部の外部リード３Ｂよりも上側の部分（図２中、外部
リード３Ｂの位置Ｈを基準にこの位置Ｈよりも上側に存
在する樹脂封止体６の厚さであるが、本実施例では０
〔ｍｍ〕）の厚さ寸法ｈ３は、樹脂封止体６とプリント
配線基板８の実装面との間の隙間寸法ｈ４に対して小さ
く設定される。この寸法に設定される外部リード３Ｂは
そのリード長さを長くできる。As shown in FIGS. 1 and 2 (enlarged cross-sectional view of an essential part), the resin-sealed semiconductor device 1 adopting the TSOP structure configured as described above has a height dimension h of the external lead 3B.
1 is larger than the thickness dimension h2 of the resin sealing body 6. The height dimension h1 is in the direction that coincides with a perpendicular line from the mounting surface of the printed wiring board 8
Is a dimension from a mounting lower surface (a mounting reference surface or a sheeting plane) mounted to the terminal 8A to a boundary portion of the resin sealing body 6. Thickness dimension h2
Is a dimension between the upper surface of the resin sealing body 6 and the lower surface facing the same in the direction coinciding with the height dimension h1. Specifically, the height dimension h1 is 1.2 [mm], and the thickness dimension h2
Are set to 1.0 [mm], respectively. In other words, a portion of the boundary of the resin sealing body 6 and the external lead 3B above the external lead 3B (from the position H on the basis of the position H of the external lead 3B in FIG. 2). Is also the thickness of the resin sealing body 6 existing on the upper side, but in this embodiment, it is 0.
The thickness dimension h3 of [mm]) is set smaller than the clearance dimension h4 between the resin sealing body 6 and the mounting surface of the printed wiring board 8. The external lead 3B set to this dimension can have a long lead length.
【００２９】また、外部リード３Ｂは、図１及び図２
中、樹脂封止体６の上面の一部に沿って（樹脂封止体６
の上面の一部と外部リード３Ｂの上側表面とを一致させ
て）延在し、この樹脂封止体６の上面において内部リー
ド３Ａに一体に構成される。この外部リード３Ｂは、樹
脂封止体６の上側表面を延在した分、内部リード３Ａの
リード長さを短くできるので、内部リード３Ａで形成さ
れる熱放出経路の熱抵抗成分を低減できる。また、外部
リード３Ｂは、樹脂封止体６の上側表面を延在した分、
リード長さを長くできるので、及び高さ寸法ｈ１を高く
した分、リード長さを長くできるので、熱放出面積を増
加できる。The external lead 3B is shown in FIGS.
Inside, along a part of the upper surface of the resin sealing body 6 (the resin sealing body 6
A part of the upper surface of the outer lead 3B and the upper surface of the outer lead 3B are aligned with each other, and the upper surface of the resin encapsulant 6 is integrally formed with the inner lead 3A. Since the outer leads 3B extend the upper surface of the resin encapsulant 6, the lead length of the inner leads 3A can be shortened, so that the thermal resistance component of the heat dissipation path formed by the inner leads 3A can be reduced. In addition, the external lead 3B extends the upper surface of the resin sealing body 6,
Since the lead length can be increased and the height h1 can be increased, the lead length can be increased, so that the heat radiation area can be increased.
【００３０】このように、半導体ペレット２を封止する
樹脂封止体６の外部側面周囲の少なくとも一部の領域に
前記半導体ペレット２の外部端子２Ａに電気的に接続さ
れる外部リード３Ｂが複数本配列されるＴＳＯＰ構造を
採用する樹脂封止型半導体装置１において、前記外部リ
ード３Ｂの一端側の実装時にリードを取り付けるリード
取付け下面から他端側の樹脂封止体６との境界部までの
間のリード高さ寸法ｈ１が、前記樹脂封止体６の前記リ
ード高さの方向と一致する方向の厚さ寸法ｈ２に比べて
大きく構成される。この構成により、以下の作用効果が
得られる。（Ａ）前記外部リード３Ｂのリード取付け面
から樹脂封止体６の境界部までの間のリード長さを長く
したので、この外部リード３Ｂに機械的応力の吸収作用
を付加できる。この結果、樹脂封止型半導体装置１の外
部リード３Ｂを半田接着層７を介在してプリント配線基
板８に実装した際、樹脂封止型半導体装置１の半導体ペ
レット２、樹脂封止体６、内部リード３Ａ、外部リード
３Ｂ、プリント配線基板８の夫々の熱膨張係数差に起因
して発生する応力が、樹脂封止型半導体装置１の外部リ
ード３Ｂで吸収できるので、温度サイクル（試験時、実
使用時のいずれも含む）による半田接着層７の損傷や破
壊を防止し、半田断線不良若しくは実装不良を防止でき
る。（Ｂ）前記外部リード３Ｂのリード長さを外部リー
ド３Ｂの高さ方向に稼ぐので、樹脂封止体６の占有面積
及び外部リード３Ｂの配置の占有面積を含む樹脂封止型
半導体装置１の全体の占有面積を縮小し、樹脂封止型半
導体装置１の小型化を図れる。（Ｃ）前記外部リード３
Ｂのリード長さを長くするだけで、外部リード３Ｂの板
厚を薄くする加工、外部リード３Ｂを軟化する加工等の
加工を行う必要がないので、これらの加工コストに相当
する分、樹脂封止型半導体装置１の製造コストを低減で
きる。また、外部リード３Ｂにこれらの加工を施さない
ので、外部リード３Ｂの根本的な機械的強度の不足を防
止できる。As described above, a plurality of external leads 3B electrically connected to the external terminals 2A of the semiconductor pellet 2 are provided in at least a partial region around the outer side surface of the resin encapsulant 6 for encapsulating the semiconductor pellet 2. In the resin-encapsulated semiconductor device 1 which adopts the TSOP structure arranged in this arrangement, from the lead mounting lower surface to which the lead is mounted at the time of mounting one end of the external lead 3B to the boundary with the resin sealing body 6 on the other end. The lead height dimension h1 between them is configured to be larger than the thickness dimension h2 of the resin sealing body 6 in the direction coinciding with the direction of the lead height. With this configuration, the following operational effects can be obtained. (A) Since the lead length from the lead mounting surface of the external lead 3B to the boundary of the resin encapsulation body 6 is increased, a mechanical stress absorbing action can be added to the external lead 3B. As a result, when the external leads 3B of the resin-encapsulated semiconductor device 1 are mounted on the printed wiring board 8 with the solder adhesive layer 7 interposed, the semiconductor pellets 2 of the resin-encapsulated semiconductor device 1, the resin encapsulant 6, The stress generated due to the difference in thermal expansion coefficient between the internal lead 3A, the external lead 3B, and the printed wiring board 8 can be absorbed by the external lead 3B of the resin-sealed semiconductor device 1, so that the temperature cycle (during the test, It is possible to prevent the solder adhesive layer 7 from being damaged or destroyed due to the actual use (including any cases), and to prevent solder disconnection failure or mounting failure. (B) Since the lead length of the external lead 3B is earned in the height direction of the external lead 3B, the resin-encapsulated semiconductor device 1 including the area occupied by the resin encapsulant 6 and the area occupied by the external lead 3B is disposed. The overall occupied area can be reduced and the resin-encapsulated semiconductor device 1 can be downsized. (C) External lead 3
It is not necessary to perform processing such as thinning the plate thickness of the external lead 3B and processing for softening the external lead 3B by simply increasing the lead length of B. The manufacturing cost of the static semiconductor device 1 can be reduced. Further, since the external leads 3B are not subjected to these processes, it is possible to prevent the underlying lead 3B from having insufficient fundamental mechanical strength.
【００３１】また、前記外部リード３Ｂの他端側は、樹
脂封止体６の外部側面周囲から樹脂封止体６の外部上面
に沿って延在され、樹脂封止体６の外部上面において内
部リード３Ａに電気的に接続される。この構成により、
前記樹脂封止体６の外部上面に沿って延在する分、外部
リード３Ｂのリード長さを長くでき、半導体ペレット２
に搭載されたＤＲＡＭの回路動作で発生する熱の放熱面
積を増加できるので、又前記樹脂封止体６の外部上面に
沿って延在する分、内部リード３Ａの長さ（外部までの
熱放出経路の長さ）を短くでき、半導体ペレット２に搭
載されたＤＲＡＭと外部リード３Ｂの他端側までの間の
熱抵抗を小くできるので、樹脂封止型半導体装置１の放
熱効果を向上できる。The other end side of the external lead 3B extends along the outer upper surface of the resin encapsulation body 6 from the periphery of the outer side surface of the resin encapsulation body 6 and the inner surface on the outer upper surface of the resin encapsulation body 6. It is electrically connected to the lead 3A. With this configuration,
The extension length of the external lead 3B can be increased by the amount of extending along the outer upper surface of the resin encapsulant 6, and the semiconductor pellet 2
Since the heat radiation area of the heat generated by the circuit operation of the DRAM mounted on the can be increased, the length of the internal lead 3A (the amount of heat released to the outside is extended by the amount of the extension along the outer upper surface of the resin sealing body 6). Since the length of the path) can be shortened and the thermal resistance between the DRAM mounted on the semiconductor pellet 2 and the other end of the external lead 3B can be reduced, the heat dissipation effect of the resin-sealed semiconductor device 1 can be improved. ..
【００３２】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。The inventions made by the present inventors are as follows.
Although the specific description has been given based on the above-mentioned embodiment, the present invention is not limited to the above-mentioned embodiment, and needless to say, various modifications can be made without departing from the scope of the invention.
【００３３】例えば、本発明は、ＴＳＯＪ（Ｔhin Ｓma
ll Ｏutline Ｊtype lead Ｐackage）構造を採用する樹
脂封止型半導体装置に適用できる。この外部リードはＪ
形状に成型される。For example, according to the present invention, the TSOJ ( T hin S ma
ll O utline J type lead Package) can be applied to the resin-sealed semiconductor device employing the structure. This external lead is J
It is molded into a shape.
【００３４】また、本発明は、面実装型のセラミック封
止型（ガラス封止型）半導体装置に適用できる。Further, the present invention can be applied to a surface-mounting ceramic-sealed (glass-sealed) semiconductor device.
【００３５】[0035]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows.
【００３６】面実装型半導体装置において、応力の吸収
作用を付加できる。In the surface mount type semiconductor device, a stress absorbing action can be added.
【００３７】面実装型半導体装置において、実装時の断
線不良若しくは実装不良を防止できる。In the surface mount type semiconductor device, it is possible to prevent disconnection failure or mounting failure during mounting.
【００３８】面実装型半導体装置において、放熱効果を
向上できる。In the surface mount type semiconductor device, the heat dissipation effect can be improved.
【図１】 本発明の一実施例の樹脂封止型半導体装置の
断面図。FIG. 1 is a cross-sectional view of a resin-sealed semiconductor device according to an embodiment of the present invention.
【図２】 前記樹脂封止型半導体装置の要部拡大断面
図。FIG. 2 is an enlarged cross-sectional view of a main part of the resin-sealed semiconductor device.
１…樹脂封止型半導体装置、２…半導体ペレット、２Ａ
…外部端子、３…リード、３Ａ…内部リード、３Ｂ…外
部リード、５…ワイヤ、６…樹脂封止体、７…半田接着
層、８…プリント配線基板、８Ａ…端子。1 ... Resin-encapsulated semiconductor device, 2 ... Semiconductor pellet, 2A
External terminals, 3 leads, 3A internal leads, 3B external leads, 5 wires, 6 resin encapsulant, 7 solder adhesive layer, 8 printed wiring board, 8A terminals.
Claims (2)
側面周囲の少なくとも一部の領域に前記半導体ペレット
の外部端子に電気的に接続される外部リードが複数本配
列される面実装型半導体装置において、前記外部リード
の一端側の実装時にリードを取り付けるリード取付け下
面から他端側の封止体との境界部までの間のリード高さ
寸法が、前記封止体の前記リード高さの方向と一致する
方向の厚さ寸法に比べて大きく構成されることを特徴と
する。1. A surface mount semiconductor in which a plurality of external leads electrically connected to external terminals of the semiconductor pellet are arranged in at least a part of the area around the outer side surface of a sealing body for sealing the semiconductor pellet. In the device, a lead height dimension from a lead mounting lower surface to which a lead is mounted when mounting one end side of the external lead to a boundary portion with the sealing body on the other end side is equal to the lead height of the sealing body. It is characterized in that it is configured to be larger than the thickness dimension in the direction coinciding with the direction.
側は、封止体の外部側面周囲から封止体の外部上面に沿
って延在され、封止体の外部上面において内部リードに
電気的に接続される。2. The other end side of the external lead according to claim 1, extends from the periphery of the outer side surface of the encapsulant along the outer upper surface of the encapsulant, and the inner lead on the outer upper surface of the encapsulant. Electrically connected to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3310783A JPH05152495A (en) | 1991-11-26 | 1991-11-26 | Semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3310783A JPH05152495A (en) | 1991-11-26 | 1991-11-26 | Semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05152495A true JPH05152495A (en) | 1993-06-18 |
Family
ID=18009418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3310783A Pending JPH05152495A (en) | 1991-11-26 | 1991-11-26 | Semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05152495A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19507573A1 (en) * | 1994-03-30 | 1995-10-05 | Gold Star Electronics | Conductor structure for semiconductor housing |
| US5592019A (en) * | 1994-04-19 | 1997-01-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and module |
| EP0750342A3 (en) * | 1995-06-21 | 1997-10-08 | Oki Electric Ind Co Ltd | Semiconductor device having the inner end of connector leads placed onto the surface of semiconductor chip |
-
1991
- 1991-11-26 JP JP3310783A patent/JPH05152495A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19507573A1 (en) * | 1994-03-30 | 1995-10-05 | Gold Star Electronics | Conductor structure for semiconductor housing |
| DE19507573C2 (en) * | 1994-03-30 | 2002-11-21 | Gold Star Electronics | Conductor structure for a semiconductor package and semiconductor package with such a conductor structure |
| US5592019A (en) * | 1994-04-19 | 1997-01-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and module |
| EP0750342A3 (en) * | 1995-06-21 | 1997-10-08 | Oki Electric Ind Co Ltd | Semiconductor device having the inner end of connector leads placed onto the surface of semiconductor chip |
| US5874783A (en) * | 1995-06-21 | 1999-02-23 | Oki Electric Industry Co., Ltd. | Semiconductor device having the inner end of connector leads displaced onto the surface of semiconductor chip |
| EP1396886A3 (en) * | 1995-06-21 | 2004-07-07 | Oki Electric Industry Company, Limited | Semiconductor device having the inner end of connector leads placed onto the surface of semiconductor chip |
| KR100473464B1 (en) * | 1995-06-21 | 2005-05-17 | 오끼 덴끼 고오교 가부시끼가이샤 | A semiconductor device |
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