JP3510520B2 - Semiconductor package and manufacturing method thereof - Google Patents
Semiconductor package and manufacturing method thereofInfo
- Publication number
- JP3510520B2 JP3510520B2 JP08298999A JP8298999A JP3510520B2 JP 3510520 B2 JP3510520 B2 JP 3510520B2 JP 08298999 A JP08298999 A JP 08298999A JP 8298999 A JP8298999 A JP 8298999A JP 3510520 B2 JP3510520 B2 JP 3510520B2
- Authority
- JP
- Japan
- Prior art keywords
- pellet
- bonding
- semiconductor package
- resin
- pellets
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体パッケージ
及びその製造方法に関し、特に、上下２つのペレットを
積層した構造の半導体パッケージ及びその製造方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a manufacturing method thereof, and more particularly to a semiconductor package having a structure in which two upper and lower pellets are stacked and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】高演算速度のＬＳＩを回路基板に実装す
る場合、回路基板における配線長が信号遅延を招き、演
算速度を低下させる。そこで、特開昭６２−３５５２８
号公報に記載のように、１枚の回路基板上に第１のＬＳ
Ｉを実装した後、この第１のＬＳＩに第２のＬＳＩを向
かい合わせて両者をはんだバンプで接続する構成や、特
開平８−８８３１６号公報に記載のように、回路基板上
に第１のＬＳＩを搭載した後、この表面に樹脂封止を施
し、この封止樹脂を絶縁層にして第２のＬＳＩを積層状
態に実装し、ボンディング接続する構成が提案されてい
る。また、１枚の回路基板（素子搭載基板）上に第１の
ＬＳＩと第２のＬＳＩを密着状態に実装したスタックト
ＣＳＰ(Chip Size Package) も提案されている。これに
ついて以下に説明する。2. Description of the Related Art When a high-calculation-speed LSI is mounted on a circuit board, the wiring length on the circuit board causes a signal delay and reduces the calculation speed. Therefore, JP-A-62-35528
As described in the publication, the first LS is mounted on one circuit board.
After mounting I, the second LSI is faced to the first LSI and both are connected by solder bumps, or as described in JP-A-8-88316, the first LSI is mounted on the circuit board. A configuration has been proposed in which, after mounting the LSI, the surface is sealed with a resin, the sealing resin is used as an insulating layer to mount the second LSI in a stacked state, and bonding connection is performed. Further, a stacked CSP (Chip Size Package) in which a first LSI and a second LSI are mounted in close contact with each other on one circuit board (element mounting board) has also been proposed. This will be described below.
【０００３】図６及び図７は、スタックトＣＳＰ構造の
従来の半導体パッケージを示す。素子搭載基板１上に
は、第１のＬＳＩである下ペレット２が実装され、この
下ペレット２上には、接着剤等を介して第２のＬＳＩで
ある上ペレット３が積層状態に実装されている。下ペレ
ット２には、両端部に複数個のボンディングパッド４が
設けられている。また、上ペレット３は、下ペレット２
のボンディングパッド４が露出可能なように、下ペレッ
ト２よりも小さいサイズに設定されている。そして、下
ペレット２と同様に上ペレット３にも複数個のボンディ
ングパッド５がボンディングパッド４と同じ方向に設け
られている。ボンディングパッド４とボンディングパッ
ド５と素子搭載基板１側をボンディングワイヤ６，７で
接続するために、素子搭載基板１上のボンディングパッ
ド４，５の近傍には、基板電極８が設けられている。6 and 7 show a conventional semiconductor package having a stacked CSP structure. A lower pellet 2 which is a first LSI is mounted on the device mounting board 1, and an upper pellet 3 which is a second LSI is mounted in a stacked state on the lower pellet 2 with an adhesive or the like. ing. The lower pellet 2 is provided with a plurality of bonding pads 4 at both ends. The upper pellet 3 is the lower pellet 2
The size is set smaller than that of the lower pellet 2 so that the bonding pad 4 can be exposed. A plurality of bonding pads 5 are provided on the upper pellet 3 in the same direction as the bonding pads 4 as on the lower pellet 2. A substrate electrode 8 is provided in the vicinity of the bonding pads 4 and 5 on the element mounting substrate 1 in order to connect the bonding pads 4 and 5 to the element mounting substrate 1 side by the bonding wires 6 and 7.
【０００４】[0004]
【発明が解決しようとする課題】しかし、従来の半導体
パッケージ及びその製造方法によると、特開昭６２−３
５５２８号公報では１枚の素子搭載基板に２つのＬＳＩ
を搭載した場合、素子搭載基板とのワイヤボンディング
は１つのＬＳＩに限定され、配線の自由度が制限され
る。また、特開平８−８８３１６号公報の半導体パッケ
ージでは、同一サイズのＬＳＩを封止樹脂を介して積層
し、かつ各々でワイヤボンディングを行っているため、
実装高さが大きくなり、小型化が図り難い。However, according to the conventional semiconductor package and the method of manufacturing the same, Japanese Patent Application Laid-Open No. 62-3200 is disclosed.
No. 5528 discloses two LSIs on one device mounting board.
When the device is mounted, the wire bonding with the device mounting board is limited to one LSI, and the degree of freedom of wiring is limited. Further, in the semiconductor package disclosed in Japanese Unexamined Patent Publication No. 8-88316, since LSIs of the same size are laminated with a sealing resin and wire bonding is performed on each of them.
The mounting height is large and it is difficult to achieve miniaturization.
【０００５】更に、図６及び図７の半導体パッケージで
は、上ペレット３は下ペレット２のボンディングパッド
４を隠さないサイズにする必要がある。そのため、ペレ
ットのサイズに厳しい制限が課され、ペレットの選択の
自由度が低いという問題がある。Further, in the semiconductor package of FIGS. 6 and 7, the upper pellet 3 needs to have a size that does not hide the bonding pad 4 of the lower pellet 2. Therefore, there is a problem that the size of the pellet is severely limited and the degree of freedom in selecting the pellet is low.
【０００６】また、図８及び図９に示す様に上ペレット
が下ペレットより大きい場合、上ペレット３のボンディ
ングパッド５の下側部分に空間９が形成されるため、ボ
ンディングを行えない場合がある。つまり、ボンディン
グ時には、Ａｕボンディングボールをボンディングツー
ルでボンディングパッド５に押し付けながら超音波パワ
ーを付与し、ＡｌのボンディングパッドとＡｕのボンデ
ィングボールとの共晶を作るという工程が存在するが、
このとき、上ペレット３の下に空間があると、ボンディ
ングボールをボンディングツールによりボンディングパ
ッド５に押し付けた際、上ペレット３に欠損が生じる。
また、上ペレット３の張出部の下が固定されていないた
めに超音波パワーが分散し、ボンディング部に超音波パ
ワーが十分にかからず、ボンディング強度が弱くなると
いう問題が生じる。If the upper pellet is larger than the lower pellet as shown in FIGS. 8 and 9, the space 9 is formed in the lower portion of the bonding pad 5 of the upper pellet 3, so that the bonding may not be performed. . That is, at the time of bonding, there is a step of applying ultrasonic power while pressing the Au bonding ball against the bonding pad 5 with a bonding tool to form a eutectic crystal of the Al bonding pad and the Au bonding ball.
At this time, if there is a space below the upper pellet 3, the upper pellet 3 will be damaged when the bonding ball is pressed against the bonding pad 5 by the bonding tool.
Further, since the lower portion of the overhanging portion of the upper pellet 3 is not fixed, the ultrasonic power is dispersed, the ultrasonic power is not sufficiently applied to the bonding portion, and the bonding strength becomes weak.
【０００７】したがって、本発明は、２つのペレットを
積層配置した場合でも、上下のペレットのサイズの制限
を緩和することのできる半導体パッケージ及びその製造
方法の提供を目的とする。Therefore, it is an object of the present invention to provide a semiconductor package and a method of manufacturing the same which can relax the restrictions on the size of upper and lower pellets even when two pellets are stacked.
【０００８】[0008]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明は、第１の特徴として、電極が設けられて
いる基板上に第１のペレットを搭載し、ボンディング部
の一部が前記第１のペレットからはみ出るようにして前
記第１のペレット上に第２のペレットを積層状態に搭載
し、前記電極と前記第１，第２のペレットのボンディン
グパッドとをボンディングワイヤで接続した半導体パッ
ケージにおいて、前記第２のペレットが前記第１のペレ
ットよりはみ出した部分と前記基板との間に形成された
空間に絶縁材が充填されていることを特徴とする半導体
パッケージを提供する。In order to achieve the above object, the present invention has, as a first feature, mounting a first pellet on a substrate provided with an electrode and forming a part of a bonding portion. The second pellet is mounted on the first pellet in a stacked state so that the electrode protrudes from the first pellet, and the electrode and the bonding pad of the first and second pellets are connected by a bonding wire. In the semiconductor package, there is provided a semiconductor package characterized in that a space formed between a portion of the second pellet protruding from the first pellet and the substrate is filled with an insulating material.
【０００９】この構成によれば、前記第２のペレットが
前記第１のペレットよりはみ出した部分と前記基板との
間に形成された空間内に充填された絶縁材は、前記第１
のペレットよりはみ出した部分に対して充填された絶縁
材が補強部材として機能し、ボンディング時に前記第２
のペレット前記はみ出し部をボンディングツールが押圧
しても、前記はみ出し部に撓みが生ぜず、欠損を生じな
い。また、超音波パワーが分散することがないため、ボ
ンディング強度を弱くすることもない。According to this structure, the insulating material filled in the space formed between the portion of the second pellet protruding from the first pellet and the substrate is the first insulating material.
The insulating material filled in the portion protruding from the pellets of No. 2 functions as a reinforcing member, and the second
Even if the bonding tool presses the protruding portion, the protruding portion is not bent and is not damaged. Moreover, since the ultrasonic power is not dispersed, the bonding strength is not weakened.
【００１０】上記の目的を達成するために、本発明は、
第２の特徴として、電極が設けられている基板上に第１
のペレットを搭載し、ボンディング部の一部が前記第１
のペレットからはみ出るようにして前記第１のペレット
上に第２のペレットを積層状態に搭載し、前記第１のペ
レットからはみ出た部分と前記基板との間に形成された
空間に絶縁材を充填又は介挿し、前記第１，第２のペレ
ットのそれぞれのボンディングパッドと前記基板上の前
記電極とをボンディングワイヤにより接続し、前記第
１，第２のペレット及び前記ボンディングワイヤによる
ボンディング部を樹脂封止することを特徴とする半導体
パッケージの製造方法を提供する。この方法によれば、
ペレットを搭載した後、前記第１のペレットからはみ出
た部と前記基板との間に形成された空間に充填された絶
縁材が前記はみ出し部の撓みを防止する補強材として機
能する。この結果、次のボンディング工程においてボン
ディングツールが前記はみ出し部を押圧しても、曲げに
よる欠損や超音波パワーの分散を生じることがない。In order to achieve the above object, the present invention provides
The second feature is that the first substrate is provided on the substrate on which the electrodes are provided.
The pellets are mounted and part of the bonding part is the first
The second pellet is mounted in a stacked state on the first pellet so as to protrude from the first pellet, and an insulating material is filled in the space formed between the portion protruding from the first pellet and the substrate. Alternatively, the bonding pads of the first and second pellets are connected to the electrodes on the substrate by bonding wires, and the bonding portions of the first and second pellets and the bonding wires are sealed with resin. A method for manufacturing a semiconductor package, which is characterized by stopping. According to this method
After mounting the pellets, the insulating material filled in the space formed between the portion protruding from the first pellet and the substrate functions as a reinforcing material that prevents the protruding portion from bending. As a result, even if the bonding tool presses the protruding portion in the next bonding step, there will be no damage due to bending and no dispersion of ultrasonic power.
【００１１】[0011]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面をもとに説明する。
〔第１の実施の形態〕図１及び図２は本発明による半導
体パッケージを示す。素子搭載基板１１上には、第１の
ＬＳＩである下ペレット１２が実装されている。この下
ペレット１２上には、接着剤等を介して第２のＬＳＩで
ある上ペレット１３が積層状態に実装されている。この
２つのペレットは、一般に異なる機能を持つ素子になっ
ており、ほぼ１つ分のペレット面積によって２つのペレ
ットを実装できるため、高密度化を実現できる。DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIGS. 1 and 2 show a semiconductor package according to the present invention. A lower pellet 12, which is a first LSI, is mounted on the device mounting board 11. On the lower pellet 12, an upper pellet 13 which is a second LSI is mounted in a stacked state via an adhesive agent or the like. These two pellets are generally elements having different functions, and since the two pellets can be mounted with a pellet area corresponding to almost one pellet, high density can be realized.
【００１２】下ペレット１２には、両端部に複数個のボ
ンディングパッド１４が設けられている。また、上ペレ
ット１３は、下ペレット１２のボンディングパッド１４
が露出可能なように、下ペレット１２よりも小さい幅に
設定されている。そして、下ペレット１２と同様に、上
ペレット１３にも複数個のボンディングパッド１５が、
ボンディングパッド１４と同じ側に設けられている。さ
らに、ボンディングパッド１４，１５と素子搭載基板１
１側とをボンディングワイヤ１６，１７で接続するため
に、素子搭載基板１１上のボンディングパッド１４，１
５のそれぞれの近傍には、複数の基板電極１８が設けら
れている。The lower pellet 12 is provided with a plurality of bonding pads 14 at both ends. In addition, the upper pellet 13 is the bonding pad 14 of the lower pellet 12.
Is set to have a width smaller than that of the lower pellet 12 so as to be exposed. And, like the lower pellet 12, the upper pellet 13 also has a plurality of bonding pads 15.
It is provided on the same side as the bonding pad 14. Further, the bonding pads 14 and 15 and the device mounting board 1
In order to connect the first side to the bonding wires 16 and 17, the bonding pads 14 and 1 on the device mounting board 11 are connected.
A plurality of substrate electrodes 18 are provided in the vicinity of each of the electrodes 5.
【００１３】上ペレット１３は、下ペレット１２よりサ
イズが大きく、下ペレット１２の両側（ボンディングパ
ッド１４の非搭載辺）から突出している。したがって、
上ペレット１３のボンディングパッド１５が非搭載の両
辺部の下部には、空間が生じている。この空間内には、
熱硬化性のエポキシ樹脂等による樹脂１９が充填されて
いる。樹脂１９を充填する段階は、素子搭載基板１１に
下ペレット１２と上ペレット１３を搭載した後である。
この樹脂１９は、上ペレット１３の上記両辺部の固定部
材として機能する。さらに、ボンディングパッド１４，
１５と基板電極１８とをボンディングワイヤ１６，１７
で接続した後、素子搭載基板１１の全体及びボンディン
グワイヤ１６，１７を覆うようにして樹脂封止部２０が
設けられる。The upper pellet 13 is larger in size than the lower pellet 12 and protrudes from both sides of the lower pellet 12 (non-mounting side of the bonding pad 14). Therefore,
A space is formed below both sides of the upper pellet 13 where the bonding pad 15 is not mounted. In this space,
A resin 19 made of a thermosetting epoxy resin or the like is filled. The step of filling the resin 19 is after mounting the lower pellet 12 and the upper pellet 13 on the element mounting substrate 11.
The resin 19 functions as a fixing member for the both sides of the upper pellet 13. Furthermore, the bonding pad 14,
15 and the substrate electrode 18 with bonding wires 16 and 17
After the connection, the resin sealing portion 20 is provided so as to cover the entire element mounting substrate 11 and the bonding wires 16 and 17.
【００１４】つまり、本実施例においては、素子搭載基
板１１上に下ペレット１２、上ペレット１３が積層配置
され、上ペレット１３が下ペレット１２からはみ出した
部分は、樹脂１９により固定されている。その結果、上
ペレット１３が下ペレット１２よりも大きく、上ペレッ
ト１３が下ペレット１２からはみ出した積層構造であっ
ても、必要にして十分な固定をすることができる。な
お、ボンディングワイヤ１６は、例えば、金などからな
る金属細線であり、さらに、樹脂１９は、熱硬化性のエ
ポキシ樹脂のほか、硬化性のある絶縁ペースト等の材料
を用いることもできる。That is, in this embodiment, the lower pellets 12 and the upper pellets 13 are stacked on the element mounting substrate 11, and the portion of the upper pellets 13 protruding from the lower pellets 12 is fixed by the resin 19. As a result, even if the upper pellet 13 is larger than the lower pellet 12 and the upper pellet 13 has a laminated structure protruding from the lower pellet 12, it can be fixed as necessary and sufficient. The bonding wire 16 is, for example, a fine metal wire made of gold or the like, and the resin 19 may be a thermosetting epoxy resin or a curable insulating paste.
【００１５】次に、本発明の半導体装置の製造方法につ
いて、図３を参照して説明する。まず、基板電極１８が
所定の箇所に設けられた素子搭載基板１１を用意し、こ
の素子搭載基板１１の片面に絶縁ぺーストなどのペレッ
ト付け剤を用いて下ペレット１２を所定の位置に搭載す
る。ついで、絶縁性の接着剤ポリイミドテープ（あるい
は、ポリイミド系の接着剤等）を介して下ペレット１２
の上面に上ペレット１３を積層する。この状態では、図
３の（ａ）に示すように、上ペレット１３のボンディン
グパッド１４の非搭載辺は、下ペレット１２の両端部か
らはみ出し、この部分の下部には空間２１が形成されて
いる。Next, a method of manufacturing the semiconductor device of the present invention will be described with reference to FIG. First, the element mounting substrate 11 having the substrate electrodes 18 provided at predetermined positions is prepared, and the lower pellet 12 is mounted at a predetermined position on one surface of the element mounting substrate 11 using a pelletizing agent such as an insulating paste. . Then, the lower pellet 12 is bonded through an insulating adhesive polyimide tape (or a polyimide adhesive, etc.).
The upper pellet 13 is laminated on the upper surface of the. In this state, as shown in FIG. 3A, the non-mounting side of the bonding pad 14 of the upper pellet 13 protrudes from both ends of the lower pellet 12, and a space 21 is formed below this portion. .
【００１６】ついで、図３の（ｂ）に示すように、空間
２１内にポッティング等の方法により、樹脂１９を充填
し、上ペレット１３と素子搭載基板１１の間に介在させ
る。その後、図３の（ｃ）に示すように、下ペレット１
２と上ペレット１３のそれぞれのボンディングパッド１
５，１６と、これらに対応する素子搭載基板１１上の基
板電極１８とを金等のボンディングワイヤ１６，１７に
より電気的に接続する。さらに、ボンディング後、下ペ
レット１２と上ペレット１３の表面、ボンディングワイ
ヤ１６、及びその周辺部を樹脂封止し、樹脂封止部２０
を形成する（図３の（ｄ））。ここで、樹脂封止部２０
の樹脂封止は、ディスペンサなどのポッティング装置を
用いたポッティングによって行ってもよいし、また、モ
ールド装置を用いたモールド技術によって行ってもよ
い。Next, as shown in FIG. 3B, the space 21 is filled with the resin 19 by a method such as potting, and the resin 19 is interposed between the upper pellet 13 and the element mounting substrate 11. Then, as shown in FIG. 3C, the lower pellet 1
Bonding pad 1 for each of 2 and upper pellet 13
5, 16 and the corresponding substrate electrodes 18 on the element mounting substrate 11 are electrically connected by bonding wires 16, 17 made of gold or the like. Further, after bonding, the surfaces of the lower pellet 12 and the upper pellet 13, the bonding wire 16, and the peripheral portion thereof are resin-sealed to form a resin-sealed portion 20.
Are formed ((d) of FIG. 3). Here, the resin sealing portion 20
The resin sealing may be performed by potting using a potting device such as a dispenser, or by a molding technique using a molding device.
【００１７】上記した本実施の形態によれば、下ペレッ
ト１２に積層された上ペレット１３の下ペレット１２か
らはみ出した部分には、樹脂１９が充填されているた
め、ボンディング時の荷重や振動によるペレット欠け、
或いは、ペレット支持が不十分なために生じるボンディ
ング強度不足のような不具合が防止される。これによ
り、下ペレット１２と上ペレット１３を積層する際のペ
レットサイズによる制限が緩和される。According to the present embodiment described above, since the resin 19 is filled in the portion protruding from the lower pellet 12 of the upper pellet 13 laminated on the lower pellet 12, the resin 19 is filled, so Chipped pellet,
Alternatively, problems such as insufficient bonding strength caused by insufficient pellet support can be prevented. This alleviates the limitation due to the pellet size when the lower pellet 12 and the upper pellet 13 are stacked.
【００１８】〔第２の実施の形態〕図４は本発明の半導
体装置の第２の実施の形態を示す。また、図５は図４の
実施の形態の製造方法の一工程における状態を示す。本
実施の形態においても、下ペレット１２と上ペレット１
３を素子搭載基板１１上に積層配置して構成される。第
１の実施の形態との相違点は、下ペレット１２と上ペレ
ット１３のボンディング時における上ペレットの固定方
法にある。[Second Embodiment] FIG. 4 shows a semiconductor device according to a second embodiment of the present invention. FIG. 5 shows a state in one step of the manufacturing method of the embodiment shown in FIG. Also in this embodiment, the lower pellet 12 and the upper pellet 1
3 are stacked and arranged on the device mounting board 11. The difference from the first embodiment lies in the method of fixing the upper pellet during the bonding of the lower pellet 12 and the upper pellet 13.
【００１９】まず、第１の実施の形態と同様に、素子搭
載基板１１の片面に下ペレット１２と上ペレット１３を
順次積層する。このとき、上ペレット１３の下ペレット
１２からはみ出している部位と素子搭載基板１１との間
には、空間２２が生じている。ついで、素子搭載基板１
１の基板電極１８が存在しない方向（ボンディングパッ
ド１４の非搭載辺の方向）から、スペーサ２３を空間２
２に挿入する。スペーサ２３は、空間２２の高さに等し
い厚さにする。これにより、上ペレット１３の端に位置
するボンディングパッド１５は、上ペレット１３の裏面
にスペーサ２３が介在して土台となり、押圧力が加わっ
ても変形が生じない。First, similarly to the first embodiment, the lower pellet 12 and the upper pellet 13 are sequentially laminated on one surface of the device mounting board 11. At this time, a space 22 is formed between the portion protruding from the lower pellet 12 of the upper pellet 13 and the element mounting board 11. Next, the device mounting board 1
1 from the direction in which the substrate electrode 18 does not exist (the direction of the non-mounting side of the bonding pad 14), the spacer 23
Insert in 2. The spacer 23 has a thickness equal to the height of the space 22. As a result, the bonding pad 15 located at the end of the upper pellet 13 serves as a base with the spacer 23 interposed on the back surface of the upper pellet 13, and is not deformed even when a pressing force is applied.
【００２０】スペーサ２３は、ボンディングワイヤ１６
によりボンディングパッド１５と基板電極１８との間の
接続を行った後、半導体パッケージから取り除く。そし
て、下ペレット１２と上ペレット１３の表面、ボンディ
ングワイヤ１６、及びその周辺部を樹脂封止し、図３の
（ｄ）に示した様に、樹脂封止部２０を形成する。樹脂
封止部２０の樹脂封止は、ディスペンサなどのポッティ
ング装置を用いたポッティングや、モールド装置を用い
たモールド技術によって行うことができる。The spacer 23 is composed of the bonding wire 16
After the connection between the bonding pad 15 and the substrate electrode 18 is made by, the semiconductor device is removed from the semiconductor package. Then, the surfaces of the lower pellet 12 and the upper pellet 13, the bonding wire 16, and the peripheral portion thereof are resin-sealed to form the resin sealing portion 20 as shown in FIG. The resin sealing of the resin sealing portion 20 can be performed by potting using a potting device such as a dispenser or a molding technique using a molding device.
【００２１】第２の実施の形態による半導体装置によれ
ば、第１の実施の形態と同様に、ボンディング作業時
に、下ペレット１２からはみ出した上ペレット１３のボ
ンディングパッド１５の部分がスペーサ２２により固定
されているので、ボンディング時における荷重や振動に
よるペレット欠け、或いは、ペレット支持が不十分なた
めに生じるボンディング強度不足のような不具合を防止
することができる。これにより、下ペレット１２、上ペ
レット１３のペレットサイズによる制限を緩和したペレ
ットの採用により積層構造の高密度実装が可能になる。
その結果、下ペレット１２及び上ペレット１３に採用す
る製品の選択肢が増え、自由度の高いスタックトＣＳＰ
を実現できる。According to the semiconductor device of the second embodiment, similarly to the first embodiment, the portion of the bonding pad 15 of the upper pellet 13 protruding from the lower pellet 12 is fixed by the spacer 22 during the bonding work. Therefore, it is possible to prevent defects such as pellet chipping due to load and vibration during bonding, or insufficient bonding strength due to insufficient pellet support. As a result, by adopting the pellets in which the restrictions on the pellet size of the lower pellet 12 and the upper pellet 13 are relaxed, it is possible to achieve high-density mounting of the laminated structure.
As a result, the choice of products used for the lower pellet 12 and the upper pellet 13 is increased, and the stacked CSP has a high degree of freedom.
Can be realized.
【００２２】以上、本発明の実施例に基づき具体的に説
明したが、本発明は前記実施例に限定されるものではな
く、その要旨を逸脱しない範囲で種々変更可能であるこ
とは言うまでもない。例えば、前記実施例で説明した半
導体装置は、下ペレット１２からはみ出した上ペレット
１３を固定する材質は樹脂に限定するものではなく、絶
縁ぺーストなどのような材料を使用することもできる。Although the present invention has been specifically described based on the embodiments of the present invention, it is needless to say that the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. For example, in the semiconductor device described in the above embodiment, the material for fixing the upper pellet 13 protruding from the lower pellet 12 is not limited to the resin, and a material such as an insulating paste may be used.
【００２３】[0023]
【発明の効果】以上説明した通り、本発明の半導体パッ
ケージ及びその製造方法によれば、下ペレットに上ペレ
ットを、一部がはみ出した状態で積層した場合でも、は
み出し部分が絶縁材によって保持固定されているため、
ボンディング時における荷重、振動によるペレット欠
け、或いは、不十分なペレット支持により生じるボンデ
ィング強度不足等の不具合の発生を防止することができ
る。As described above, according to the semiconductor package and the method of manufacturing the same of the present invention, even when the upper pellet is stacked on the lower pellet, the protruding portion is held and fixed by the insulating material even if a part of the upper pellet is stacked. Because it has been
It is possible to prevent problems such as pellet chipping due to load and vibration during bonding, or insufficient bonding strength caused by insufficient pellet support.
【図１】本発明による半導体パッケージの第１の実施の
形態を示す平面図である。FIG. 1 is a plan view showing a first embodiment of a semiconductor package according to the present invention.
【図２】図１の半導体パッケージの断面図である。2 is a cross-sectional view of the semiconductor package of FIG.
【図３】本発明の第１の実施の形態の製造工程を示す説
明図である。FIG. 3 is an explanatory diagram showing a manufacturing process according to the first embodiment of the present invention.
【図４】本発明による半導体パッケージの第２の実施の
形態を示す平面図である。FIG. 4 is a plan view showing a second embodiment of a semiconductor package according to the present invention.
【図５】図４の半導体パッケージの正面図である。5 is a front view of the semiconductor package of FIG.
【図６】スタックトＣＳＰ構造の従来の半導体パッケー
ジを示す平面図である。FIG. 6 is a plan view showing a conventional semiconductor package having a stacked CSP structure.
【図７】図６の半導体パッケージの正面図である。FIG. 7 is a front view of the semiconductor package of FIG.
【図８】上ペレットが下ペレットより大きい場合の半導
体パッケージを示す平面図である。FIG. 8 is a plan view showing a semiconductor package when the upper pellet is larger than the lower pellet.
【図９】図８の半導体パッケージの正面図である。9 is a front view of the semiconductor package of FIG.
１，１１ 素子搭載基板 ２，１２ 下ペレット ３，１３ 上ペレット ４，５，１４，１５ ボンディングパッド ６，７ ボンディングワイヤ ８，１８ 基板電極 １６，１７ ボンディングワイヤ １９ 樹脂 ２０ 樹脂封止部 ２１，２２ 空間 ２３ スペーサ 1,11 element mounting board 2,12 Lower pellet 3,13 Upper pellet 4, 5, 14, 15 Bonding pad 6,7 Bonding wire 8,18 Substrate electrode 16,17 Bonding wire 19 resin 20 Resin sealing part 21,22 space 23 Spacer
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 25/065 H01L 21/60 301 H01L 23/28 H01L 25/07 H01L 25/18 ─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 25/065 H01L 21/60 301 H01L 23/28 H01L 25/07 H01L 25/18
Claims (6)
第１のペレットを搭載し、ボンディング部の一部が前記
第１のペレットからはみ出るようにして前記第１のペレ
ット上に第２のペレットを積層状態に搭載し、前記電極
と前記第１，第２のペレットのボンディングパッドとを
ボンディングワイヤで接続した半導体パッケージにおい
て、 前記第２のペレットが前記第１のペレットよりはみ出た
部分と前記基板との間に形成された空間に絶縁材が充填
されていることを特徴とする半導体パッケージ。1. A first pellet is mounted on a substrate on which a connecting electrode is provided, and a part of a bonding portion protrudes from the first pellet, and a second pellet is formed on the first pellet. In a semiconductor package in which the above-mentioned pellets are mounted in a stacked state and the electrodes and the bonding pads of the first and second pellets are connected by a bonding wire, and a portion in which the second pellets protrude from the first pellets. A semiconductor package, wherein an insulating material is filled in a space formed between the substrate and the substrate.
異なる材料であることを特徴とする請求項１記載の半導
体パッケージ。2. The semiconductor package according to claim 1, wherein the insulating material is a material different from a resin material for resin encapsulation.
あることを特徴とする請求項１又は２記載の半導体パッ
ケージ。3. The semiconductor package according to claim 1, wherein the insulating material is resin or insulating paste.
第１のペレットを搭載し、 ボンディング部の一部が前記第１のペレットからはみ出
るようにして前記第１のペレット上に第２のペレットを
積層状態に搭載し、 前記第１のペレットからはみ出た部分と前記基板との間
に形成された空間に絶縁材を充填又は介挿し、 前記第１，第２のペレットのそれぞれのボンディングパ
ッドと前記基板上の前記電極とをボンディングワイヤに
より接続し、 前記第１，第２のペレット及び前記ボンディングワイヤ
によるボンディング部を樹脂封止することを特徴とする
半導体パッケージの製造方法。4. A first pellet is mounted on a substrate provided with an electrode for connection, and a second bonding layer is formed on the first pellet so that a part of a bonding portion protrudes from the first pellet. Pellets are stacked, and an insulating material is filled or inserted in a space formed between the portion protruding from the first pellet and the substrate, and each of the first and second pellets is bonded. A method of manufacturing a semiconductor package, comprising: connecting a pad and the electrode on the substrate with a bonding wire, and sealing the first and second pellets and a bonding portion with the bonding wire with a resin.
あることを特徴とする請求項４記載の半導体パッケージ
の製造方法。5. The method of manufacturing a semiconductor package according to claim 4, wherein the insulating material is resin or insulating paste.
前記樹脂封止を行う前に除去することを特徴とする請求
項４記載の半導体パッケージの製造方法。6. The insulating material is a plate-shaped spacer,
The method of manufacturing a semiconductor package according to claim 4, wherein the resin is removed before the resin sealing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08298999A JP3510520B2 (en) | 1999-03-26 | 1999-03-26 | Semiconductor package and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08298999A JP3510520B2 (en) | 1999-03-26 | 1999-03-26 | Semiconductor package and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000277559A JP2000277559A (en) | 2000-10-06 |
| JP3510520B2 true JP3510520B2 (en) | 2004-03-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP08298999A Expired - Fee Related JP3510520B2 (en) | 1999-03-26 | 1999-03-26 | Semiconductor package and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3510520B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002222889A (en) | 2001-01-24 | 2002-08-09 | Nec Kyushu Ltd | Semiconductor device and method of manufacturing the same |
| JP4633971B2 (en) * | 2001-07-11 | 2011-02-16 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP3776427B2 (en) | 2003-11-17 | 2006-05-17 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| US7629695B2 (en) * | 2004-05-20 | 2009-12-08 | Kabushiki Kaisha Toshiba | Stacked electronic component and manufacturing method thereof |
-
1999
- 1999-03-26 JP JP08298999A patent/JP3510520B2/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| JP2000277559A (en) | 2000-10-06 |
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