JPH0437050A - Resin seal type semiconductor device - Google Patents
Resin seal type semiconductor deviceInfo
- Publication number
- JPH0437050A JPH0437050A JP2143965A JP14396590A JPH0437050A JP H0437050 A JPH0437050 A JP H0437050A JP 2143965 A JP2143965 A JP 2143965A JP 14396590 A JP14396590 A JP 14396590A JP H0437050 A JPH0437050 A JP H0437050A
- Authority
- JP
- Japan
- Prior art keywords
- tab
- resin
- semiconductor device
- sealed
- sealed semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 94
- 229920005989 resin Polymers 0.000 title claims abstract description 49
- 239000011347 resin Substances 0.000 title claims abstract description 49
- 239000008188 pellet Substances 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000012212 insulator Substances 0.000 claims description 12
- 239000000725 suspension Substances 0.000 claims description 12
- 230000002093 peripheral effect Effects 0.000 abstract description 18
- 238000000034 method Methods 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 6
- 239000010410 layer Substances 0.000 abstract description 5
- 230000000149 penetrating effect Effects 0.000 abstract description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 4
- 239000012790 adhesive layer Substances 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229920005749 polyurethane resin Polymers 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- -1 and the tab Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に、被覆ワイヤを使用
する樹脂封止型半導体装置に適用して有効な技術に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a technique that is effective when applied to a resin-sealed semiconductor device using a covered wire.
QFP(Quad Flat Package)等の樹
脂封止型(レジンモールド型)半導体装置はセラミック
封止型に比べて低価格で形成され、その需要は高い。Resin-molded semiconductor devices such as QFP (Quad Flat Package) can be formed at a lower cost than ceramic-encapsulated semiconductor devices, and are in high demand.
この種の樹脂封止型半導体装置は半導体ペレットの外部
端子(ポンディングパッド)、リードのインナーリード
の夫々をワイヤで接続する。半導体ぺレットは一般的に
タブの表面に搭載される。この半導体ペレット、タブ、
インナーリード及びワイヤは樹脂で気密封止(レジンモ
ールド)される。樹脂としては例えばエポキシ系樹脂を
使用する。In this type of resin-sealed semiconductor device, the external terminals (ponding pads) of the semiconductor pellet and the inner leads of the leads are connected by wires. Semiconductor pellets are typically mounted on the surface of the tab. This semiconductor pellet, tab,
The inner leads and wires are hermetically sealed with resin (resin mold). For example, epoxy resin is used as the resin.
本発明者が開発中の樹脂封止型半導体装置は特願昭62
−200561号に記載される被覆ワイヤ技術を採用す
る。この被覆ワイヤは金属線の表面に絶縁体を被覆した
ものである。被覆ワイヤの金属線としては金(Au)、
銅(Cu)又はアルミニウム(AQ)が使用される。絶
縁体としてはポリウレタン系樹脂、ポリイミド樹脂系等
の樹脂系絶縁材料が使用される。The resin-sealed semiconductor device currently being developed by the present inventor was patented in 1986.
-200561 is adopted. This coated wire is a metal wire whose surface is coated with an insulator. The metal wire of the coated wire is gold (Au),
Copper (Cu) or aluminum (AQ) is used. As the insulator, a resin-based insulating material such as polyurethane resin or polyimide resin is used.
この被覆ワイヤを使用する樹脂封止型半導体装置は、金
属線で形成された所謂裸ワイヤを使用する樹脂封止型半
導体装置に比べて、以下の点で優れている。A resin-sealed semiconductor device using this coated wire is superior to a resin-sealed semiconductor device using a so-called bare wire formed of a metal wire in the following points.
(1)被覆ワイヤは金属線を絶縁体で被覆するので、隣
接する被覆ワイヤ間の短絡、被覆ワイヤータブ間の短絡
、被覆ワイヤー半導体ペレット間の短絡がない。このた
め、樹脂封止型半導体装置の信頼性を向上できる。(1) Since the covered wire covers the metal wire with an insulator, there are no short circuits between adjacent covered wires, short circuits between covered wire tabs, and short circuits between covered wire semiconductor pellets. Therefore, the reliability of the resin-sealed semiconductor device can be improved.
(2)前記(1)に基き、被覆ワイヤのボンディングの
際のループは、タブの周囲(エッチ)に接触することを
許容できるので、ボンディングの自由度が増す。つまり
、1種類のリードフレームにサイズが異なる半導体ペレ
ットを自由に搭載できるので、リードフレームの種類を
削減できる。また。(2) Based on the above (1), the loop of the covered wire during bonding can be allowed to come into contact with the periphery (etch) of the tab, increasing the degree of freedom in bonding. In other words, since semiconductor pellets of different sizes can be freely mounted on one type of lead frame, the number of types of lead frames can be reduced. Also.
被覆ワイヤを交差させる所謂クロスボンディングを自由
に行え、半導体ペレットの品種の改良毎にリードフレー
ムの開発を行う必要がないので、同様にリードフレーム
の種類を削減できる。So-called cross bonding, in which covered wires are crossed, can be freely performed, and there is no need to develop a lead frame every time the type of semiconductor pellet is improved, so the types of lead frames can be similarly reduced.
(3)前記(1)に基き、被覆ワイヤの配列間隔を縮小
できるので、樹脂封止型半導体装置の多ビン化を図れる
。(3) Based on the above (1), since the arrangement interval of the covered wires can be reduced, the number of bottles of the resin-sealed semiconductor device can be increased.
しかしながら、本発明者は、前述の被覆ワイヤを使用す
る樹脂封止型半導体装置の開発に先き立ち、温度サイク
ル試験(加速試験)を行った結果、下記の問題点を見出
した。However, prior to developing a resin-sealed semiconductor device using the above-mentioned coated wire, the inventor conducted a temperature cycle test (accelerated test) and found the following problems.
前記樹脂封止型半導体装置のタブと樹脂との接合部は金
屑と樹脂との接合部であるので密着性が悪い。温度サイ
クル試験を行うと、タブ、樹脂の夫々は半導体ペレット
を中心に放射状方向に沿って膨張、収縮を繰返えす。こ
の膨張、収縮は、タブの周辺部分においてタブに対して
熱膨張係数差に基く樹脂の相対的な動き量を実質的に最
大とし、このタブの表面から樹脂を剥離する。一方、被
覆ワイヤの絶縁体は前述のように樹脂系材料で形成され
るので、封止材としての樹脂との密着性が高い。つまり
、タブの表面に対向する位置に配置された被覆ワイヤは
タブの周辺部分において樹脂の膨張、収縮とともに動き
を生じる。これに対して、タブのインナーリード側の外
側において、封止材としての樹脂は温度サイクルに基く
動きが小さい。The joint between the tab and the resin of the resin-sealed semiconductor device is a joint between metal chips and resin, and thus has poor adhesion. When a temperature cycle test is performed, each of the tab and resin repeatedly expands and contracts along the radial direction around the semiconductor pellet. This expansion and contraction substantially maximizes the amount of relative movement of the resin with respect to the tab based on the difference in thermal expansion coefficient in the peripheral portion of the tab, and peels the resin from the surface of the tab. On the other hand, since the insulator of the covered wire is made of a resin material as described above, it has high adhesion to the resin as the sealing material. In other words, the covered wire placed opposite the surface of the tab moves as the resin expands and contracts around the tab. On the other hand, on the outside of the tab on the inner lead side, the resin serving as the sealing material moves less due to temperature cycles.
つまり、タブ、インナーリードの夫々の間においては大
半に樹脂が充填され、タブの表面側(半導体ペレットの
搭載面側)、裏面側の夫々の樹脂が連結され、この領域
の樹脂は前記方射状方向の動きをタブの周辺端部で抑え
ている。また、インナーリードが配列された領域は、タ
ブに比べて1本のインナーリードと樹脂との接触面積が
小さく。In other words, most of the space between the tab and the inner lead is filled with resin, and the resin on the front side (semiconductor pellet mounting side) and back side of the tab are connected, and the resin in this area is Movement in the vertical direction is suppressed by the peripheral edge of the tab. Furthermore, in the region where the inner leads are arranged, the contact area between one inner lead and the resin is smaller than that in the tab.
このインナーリードの上側、下鍔の夫々の樹脂が相互に
連結されるので、この領域の樹脂は同様に前記方射状方
向の動きが小さい。このため、樹脂封止型半導体装置は
、被覆ワイヤに温度サイクルに基きタブの周辺部分で引
張り応力、圧縮応力が繰返し発生し、この領域で被覆ワ
イヤのWir線不良不良発する。本発明者は、このよう
なワイヤの断線不良は所謂裸ワイヤでは発生せず、被覆
ワイヤを使用する樹脂封止型半導体装置に特有のもので
あると考察している。Since the resin on the upper side and the lower flange of this inner lead are connected to each other, the movement of the resin in this region in the radial direction is also small. For this reason, in the resin-sealed semiconductor device, tensile stress and compressive stress are repeatedly generated in the covered wire in the peripheral portion of the tab due to temperature cycles, and Wir line defects of the covered wire occur in this region. The present inventor considers that such a wire breakage failure does not occur with so-called bare wires, but is unique to resin-sealed semiconductor devices that use coated wires.
本発明の目的は、被覆ワイヤを使用する樹脂封止型半導
体装置において、前記被覆ワイヤの断線不良を防止する
ことが可能な技術を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a technique capable of preventing disconnection of a covered wire in a resin-sealed semiconductor device using a covered wire.
本発明の他の目的は、被覆ワイヤを使用する樹脂封止型
半導体装置の信頼性を向上することが可能な技術を提供
することにある。Another object of the present invention is to provide a technique that can improve the reliability of a resin-sealed semiconductor device using covered wire.
本発明の他の目的は、前記目的を達成すると共に、この
目的を達成することによる弊害を低減することか可能な
技術を提供することにある。Another object of the present invention is to provide a technique capable of achieving the above object and reducing the adverse effects of achieving this object.
本発明の前記ならびにその他の目的と新規な特徴は5本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become clear from the description of the present specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
(1)タブ上に搭載された半導体ペレットの外部端子、
リードの夫々が金属線の表面に絶縁体を被覆した被覆ワ
イヤで接続され、前記タブ、半導体ペレット、リード及
び被覆ワイヤを樹脂で封止する樹脂封止型半導体装置に
おいて、前記タブの周囲にこのタブの表面から裏面に貫
通する開口を設ける。(1) External terminal of semiconductor pellet mounted on tab,
In a resin-sealed semiconductor device in which each lead is connected with a coated wire whose surface is coated with an insulator, and the tab, semiconductor pellet, lead, and coated wire are sealed with resin, this resin is placed around the tab. Provide an opening that penetrates from the front surface to the back surface of the tab.
(2)前記手段(1)のタブの周囲に設けた開口はこの
タブの周囲に沿って細長く伸びる平面形状をスリット形
状で構成する。(2) The opening provided around the tab of the means (1) has a slit-like planar shape that extends long and narrow along the periphery of the tab.
(3)前記手段(1)のタブの周囲に設けた開口はこの
タブの周囲に沿って複数個配列される。(3) A plurality of openings provided around the tab of the means (1) are arranged along the periphery of the tab.
(4)周囲にタブ吊りリードを連結するタブ上に搭載さ
れた半導体ペレットの外部端子、リードの夫々が金属線
の表面に絶縁体を被覆した被覆ワイヤで接続され、前記
タブ、半導体ペレット、リード及び被覆ワイヤを樹脂で
封止する樹脂封止型半導体装置において、前記タブとタ
ブ吊りリードとの連結部分を除き、前記タブの周囲にこ
のタブの表面から裏面に貫通する開口を設ける。(4) The external terminals and leads of the semiconductor pellet mounted on the tab that connect the tab hanging leads around the surroundings are connected by coated wires in which the surface of the metal wire is coated with an insulator. In a resin-sealed semiconductor device in which a coated wire is sealed with resin, an opening is provided around the tab, excluding a connecting portion between the tab and a tab suspension lead, and penetrating from the front surface to the back surface of the tab.
上述した手段(1)によれば、前記タブの周辺部分でこ
のタブの表面側(半導体ペレットの搭載面側)、裏面側
の夫々の樹脂を連結し、タブの周辺部分でこのタブと樹
脂との密着性を向上できるので、タブの周辺部分での温
度サイクルに基く樹脂の動きを低減し、被覆ワイヤに発
生する応力を低減できる。この結果、被覆ワイヤの断線
不良を防止し、樹脂封止型半導体装置の温度サイクルに
基く信頼性を向上できる。According to the above-mentioned means (1), the resin on the front side (semiconductor pellet mounting surface side) and the back side of the tab are connected at the peripheral part of the tab, and the tab and the resin are connected at the peripheral part of the tab. Since the adhesion of the tab can be improved, the movement of the resin due to temperature cycles around the tab can be reduced, and the stress generated in the coated wire can be reduced. As a result, breakage of the covered wire can be prevented, and reliability based on temperature cycles of the resin-sealed semiconductor device can be improved.
上述した手段(2)によれば、前記タブの周辺部分での
開口の開口面積を増加し、タブの周辺部分でのタブの表
面側、裏面側の夫々の樹脂の連結面積を増加できるので
、タブの周辺部分と樹脂との密着性をより高め、より樹
脂封止型半導体装置の信頼性を向上できる。According to the above-mentioned means (2), the opening area of the opening in the peripheral portion of the tab can be increased, and the connection area of the resin on the front side and the back side of the tab can be increased in the peripheral portion of the tab. It is possible to further improve the adhesion between the peripheral portion of the tab and the resin, thereby further improving the reliability of the resin-sealed semiconductor device.
上述した手段(3)によれば、前記タブの周辺部分でこ
のタブの開口の内側(半導体ペレット側)、外側(イン
ナーリード側)の夫々を連結する領域の面積を増加し、
タブ自体の機械的強度を向上できる。According to the above-mentioned means (3), the area of the area connecting the inner side (semiconductor pellet side) and the outer side (inner lead side) of the opening of the tab is increased in the peripheral portion of the tab,
The mechanical strength of the tab itself can be improved.
上述した手段(4)によれば、前記手段(1)の効果の
他に、前記タブのタブ吊りリードと連結される領域の機
械的強度を向上できる。According to the above-mentioned means (4), in addition to the effect of the above-mentioned means (1), the mechanical strength of the region of the tab connected to the tab suspension lead can be improved.
以下、本発明の構成について、被覆ワイヤを使用するQ
FP構造の樹脂封止型半導体装置に本発明を適用した一
実施例とともに説明する。Below, regarding the configuration of the present invention, Q
An embodiment in which the present invention is applied to a resin-sealed semiconductor device having an FP structure will be described.
なお、実施例を説明するための全図において、同一機能
を有するものは同一符号を付け、その繰り返しの説明は
省略する。In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.
(実施例I)
本発明の実施例IであるQFP構造の樹脂封止型半導体
装置の構成を第1図(要部断面図)及び第2図(部分平
面図)で示す。(Example I) The structure of a resin-sealed semiconductor device having a QFP structure, which is Example I of the present invention, is shown in FIG. 1 (cross-sectional view of main parts) and FIG. 2 (partial plan view).
第1図及び第2図に示すように、QFP構造の樹脂封止
型半導体装置1は半導体ペレット2の外部端子(ポンデ
ィングパッド)2C、インナーリード4Bの夫々を被覆
ワイヤ5で接続する。As shown in FIGS. 1 and 2, in a resin-sealed semiconductor device 1 having a QFP structure, an external terminal (ponding pad) 2C and an inner lead 4B of a semiconductor pellet 2 are connected with a covered wire 5, respectively.
半導体ペレット2は単結晶珪素基板2Aを主体に構成さ
れ、この単結晶珪素基板2Aの表面(素子形成面)には
システム回路が搭載される。このシステム回路は図示し
ない半導体素子で構成される。単結晶珪素基板2Aの表
面上には層間絶縁膜2Bを介在し配線層が設けられる。The semiconductor pellet 2 is mainly composed of a single crystal silicon substrate 2A, and a system circuit is mounted on the surface (element formation surface) of the single crystal silicon substrate 2A. This system circuit is composed of semiconductor elements (not shown). A wiring layer is provided on the surface of single crystal silicon substrate 2A with interlayer insulating film 2B interposed therebetween.
この配線層のうち基本的に最上層の配線層と同一層で外
部端子2Cが構成される。外部端子2Cは例えばアルミ
ニウム合金膜で構成される。前記外部端子2C上には、
符号を付けないが、最終保護膜(ファイナルバッジベー
ジ巨ン膜)に形成されたボンディング開口を通してバリ
アメタル膜が接続される。外部端子2Cにはこのバリア
メタル膜を介在し被覆ワイヤ5の一端側が接続される。Of these wiring layers, the external terminal 2C is basically formed in the same layer as the uppermost wiring layer. The external terminal 2C is made of, for example, an aluminum alloy film. On the external terminal 2C,
Although no reference numerals are given, the barrier metal film is connected through a bonding opening formed in the final protective film (final badge giant film). One end of the coated wire 5 is connected to the external terminal 2C with this barrier metal film interposed therebetween.
前記半導体ペレット2はタブ4Aの表面上(半導体ペレ
ット2の搭載面上)に接着層3を介在して固着される。The semiconductor pellet 2 is fixed onto the surface of the tab 4A (on the mounting surface of the semiconductor pellet 2) with an adhesive layer 3 interposed therebetween.
接着層3としては例えばAgペースト、Au−8i共晶
合金等を使用する。As the adhesive layer 3, for example, Ag paste, Au-8i eutectic alloy, etc. are used.
前記タブ4Aは第2図に示すように平面形状が方形状で
構成される。このタブ4Aは、品種や外形サイズが異な
る半導体ペレット2を自由に搭載し、リードフレーム4
の種類を低減する目的で、同第2図に示す半導体ペレッ
ト2の平面サイズに比べて大きい平面サイズで構成され
る。例えば、本実施例■の樹脂封止型半導体装置1は平
面サイズが7.2X7.2[mm]で形成されたタブ4
Aの表面上に平面サイズが2.IX2.1[mm]で形
成された半導体ペレット2を搭載する。タブ4Aは例え
ばFe−Ni系合金(例えば42[%コのNiを含有す
るFe系合金)で形成される。また、タブ4AはこのF
e−Ni系合金に限らずCu系材料で形成してもよい。The tab 4A has a rectangular planar shape as shown in FIG. This tab 4A can be freely loaded with semiconductor pellets 2 of different types and external sizes, and can be mounted on the lead frame 4.
In order to reduce the number of types of semiconductor pellets, the semiconductor pellet 2 is constructed with a larger planar size than that of the semiconductor pellet 2 shown in FIG. For example, the resin-sealed semiconductor device 1 of this embodiment (2) has a tab 4 having a planar size of 7.2×7.2 [mm]
On the surface of A, the plane size is 2. A semiconductor pellet 2 formed of IX2.1 [mm] is mounted. The tab 4A is formed of, for example, a Fe-Ni alloy (for example, an Fe-based alloy containing 42% Ni). Also, tab 4A is this F
It is not limited to the e-Ni alloy, but may be made of a Cu-based material.
タブ4Aは、第2図に示すように、その周囲の平面形状
が方形状の各角部分の近傍においてタブ吊りリード4E
に連結される。つまり、本実施例Iの樹脂封止型半導体
装[1は4本のタブ吊りリード4Eで支持される。As shown in FIG. 2, the tab 4A has a tab suspension lead 4E near each corner of a rectangular planar shape.
connected to. That is, the resin-sealed semiconductor device [1 of Example I] is supported by the four tab suspension leads 4E.
このタブ4Aには、同第2図に示すように、その周囲に
沿って細長く伸びる平面形状がスリット形状の開口4D
が構成される。開口4Dは、基本的に、タブ4Aの表面
側からその裏面側に向って貫通した貫通穴で構成され、
タブ4Aの周辺部分において、タブ4Aの表面側、裏面
側の夫々の樹脂(6)を連結する。開口4Dはタブ4A
の周囲に沿って複数個配列される。この間口4Dの配列
方向においてタブ4Aの開口4D間は、タブ4Aの開口
4Dの内側(半導体ペレット2側)、外側(インナーリ
ード4B側)の夫々を連結する連結領域として使用され
る。つまり、この連結領域は、タブ4Aの開口4Dの内
側、外側の夫々の機械的強度を確保し、タブ4A自体の
機械的強度を確保する。また、前記開口4Dはタブ4A
のタブ吊りリード4Eとの連結部分(第2図中、符号4
Fを付けて一点鎖線で囲まれた領域)以外の領域に構成
される。このタブ4Aのタブ吊りリード4Eとの連結部
分は、タブ4Aを支持する最大の応力が加わるので、機
械的強度を確保する目的で開口4Dを配置しない。As shown in FIG. 2, this tab 4A has an opening 4D having a slit-shaped planar shape extending long and narrow along its periphery.
is configured. The opening 4D basically consists of a through hole penetrating from the front side of the tab 4A to the back side thereof,
At the peripheral portion of the tab 4A, the resins (6) on the front and back sides of the tab 4A are connected. Opening 4D is tab 4A
Multiple pieces are arranged along the periphery of the . In the arrangement direction of the openings 4D, the space between the openings 4D of the tabs 4A is used as a connection area for connecting the inside (semiconductor pellet 2 side) and outside (inner lead 4B side) of the openings 4D of the tabs 4A. In other words, this connecting region ensures mechanical strength on the inside and outside of the opening 4D of the tab 4A, and also ensures the mechanical strength of the tab 4A itself. Further, the opening 4D is a tab 4A.
The connection part with the tab suspension lead 4E (in Figure 2, reference numeral 4)
It is configured in an area other than the area marked with F and surrounded by a dashed line. Since the maximum stress for supporting the tab 4A is applied to the connecting portion of the tab 4A with the tab suspension lead 4E, the opening 4D is not provided for the purpose of ensuring mechanical strength.
前記開口4Dは、平面サイズが大きな半導体ペレット2
を搭載可能とする目的で、占有面積を小さくするために
、幅寸法(スリット幅寸法)を小さくする。一方、開口
4Dの幅寸法が小さすぎると、応力集中によりタブ4A
に割れが発生するので、これらを考慮のうえ、開口4D
の幅寸法を設定する。本実施例Iの樹脂封止型半導体装
置1は、タブ4Aに設けた開口4Dの幅寸法を約Q、2
[mm]とし、タブ4Dの周囲の端面から内側に向って
約1.5[mm]の位置から開口4Dを配置する。The opening 4D is formed by a semiconductor pellet 2 having a large planar size.
The width dimension (slit width dimension) is made smaller in order to reduce the occupied area in order to make it possible to mount the slit. On the other hand, if the width of the opening 4D is too small, stress concentration will cause the tab 4A to
Since cracks will occur in the opening 4D, take these into consideration.
Set the width dimension of In the resin-sealed semiconductor device 1 of Example I, the width dimension of the opening 4D provided in the tab 4A is approximately Q,2
[mm], and the opening 4D is arranged from a position of about 1.5 [mm] inward from the end surface around the tab 4D.
また、前記タブ4Aの平面方形状の各辺の中央部分は被
覆ワイヤ5に発生する応力が大きくなるので、この領域
には開口4Dを積極的に配置し、開口4D間の連結領域
は配置しない。In addition, since the stress generated in the covered wire 5 is large in the central portion of each side of the tab 4A having a rectangular planar shape, the openings 4D are positively arranged in this area, and the connection area between the openings 4D is not arranged. .
前記被覆ワイヤ5は第1図に示すように金属線5Aの表
面に絶縁体5Bを被覆し構成される。金属線5Aは本実
施例IにおいてAuを使用)−る。The coated wire 5 is constructed by coating the surface of a metal wire 5A with an insulator 5B, as shown in FIG. In this embodiment I, the metal wire 5A is made of Au.
また、金属!!5Aは前記以外の材料としてCu、AΩ
、AQ系合金等で形成してもよい。絶縁体5Bは本実施
例Iにおいてポリウレタン系樹脂或はポリイミド系樹脂
を使用する。また、絶縁体5Bは前記以外の材料として
エステルイミド系樹脂、エステルアミド系樹脂等の樹脂
材で形成してもよい。Also, metal! ! 5A is Cu, AΩ as materials other than the above.
, AQ alloy, or the like. In this embodiment I, the insulator 5B is made of polyurethane resin or polyimide resin. Further, the insulator 5B may be formed of a resin material other than the above-mentioned materials, such as an esterimide resin or an esteramide resin.
前記被覆ワイヤ5はこれに限定されないがボール&ウェ
ッジボンディング法或はウェッジ&ウェッジボンディン
グ法によってボンディングされる。The covered wire 5 may be bonded by a ball and wedge bonding method or a wedge and wedge bonding method, but is not limited thereto.
つまり、被覆ワイヤ5は基本的に熱圧着に超音波振動を
併用したボンディング法により半導体ペレット2の外部
端子2C、インナーリード4Bの夫々にボンディングさ
れる。That is, the coated wire 5 is bonded to each of the external terminal 2C and the inner lead 4B of the semiconductor pellet 2 basically by a bonding method using thermocompression bonding in combination with ultrasonic vibration.
前記インナーリード4B、アウターリード4cの夫々は
一体に構成され、これらはタブ4Aと同一のリードフレ
ーム4から切断及び成型される。The inner lead 4B and outer lead 4c are each integrally constructed, and are cut and molded from the same lead frame 4 as the tab 4A.
つまり、タブ4A、インナーリード4B、アウタ−リー
ド4C、タブ吊りリード4Eの夫々は同一の材料から構
成される。That is, the tab 4A, inner lead 4B, outer lead 4C, and tab suspension lead 4E are each made of the same material.
前述の半導体ペレット2.タブ4A、タブ吊りリード4
E、インナーリード4B、被覆ワイヤ5の夫々は樹脂(
レジン)6で気密封止される。樹脂6は例えば熱硬化性
或は熱可塑性のエポキシ系樹脂を使用する。The aforementioned semiconductor pellet 2. Tab 4A, tab hanging lead 4
E, inner lead 4B, and coated wire 5 are each made of resin (
It is hermetically sealed with resin) 6. As the resin 6, for example, a thermosetting or thermoplastic epoxy resin is used.
このように、タブ4A上に搭載された半導体ペレット2
の外部端子2C、インナーリード4Bの夫々が金属線5
Aの表面に絶縁体5Bを被覆した被覆ワイヤ5で接続さ
れ、前記タブ4A、半導体ペレット2、インナーリード
4B及び被覆ワイヤ5を樹脂6で封止する樹脂封止型半
導体装置1において、前記タブ4Aの周囲にこのタブ4
Aの表面から裏面に貫通する開口4Dを設ける。この構
成により、前記タブ4Aの周辺部分でこのタブ4Aの表
面側(半導体ペレット2の搭載面側)、裏面側の夫々の
樹脂6を連結し、タブ4Aの周辺部分でこのタブ4Aと
樹脂6との密着性を向上できるので、タブ4Aの周辺部
分での温度サイクルに基く樹脂6の動きを低減し、被覆
ワイヤ5に発生する応力(引張り応力、圧縮応力)を低
減できる。この結果、被覆ワイヤ5の断線不良を防止し
、樹脂封止型半導体装置6の温度サイクルに基く信頼性
を向上できる。In this way, the semiconductor pellet 2 mounted on the tab 4A
The external terminal 2C and the inner lead 4B are each connected to the metal wire 5.
In the resin-sealed semiconductor device 1, the tab 4A, the semiconductor pellet 2, the inner lead 4B, and the coated wire 5 are sealed with a resin 6. This tab 4 around 4A
An opening 4D penetrating from the front surface to the back surface of A is provided. With this configuration, the resin 6 on the front side (the mounting surface side of the semiconductor pellet 2) and the back side of the tab 4A are connected at the peripheral portion of the tab 4A, and the resin 6 and the tab 4A are connected at the peripheral portion of the tab 4A. Since the adhesion with the tab 4A can be improved, the movement of the resin 6 due to temperature cycles around the tab 4A can be reduced, and the stress (tensile stress, compressive stress) generated in the covered wire 5 can be reduced. As a result, breakage of the covered wire 5 can be prevented, and the reliability of the resin-sealed semiconductor device 6 based on temperature cycles can be improved.
また、前記タブ4Aの周囲に設けた開口4Dはこのタブ
4Aの周囲に沿って細長く伸びる平面形状をスリット形
状で構成する。この構成により、前記タブ4Aの周辺部
分での開口4Dの開口面積を増加し、タブ4Aの周辺部
分でのタブ4Aの表面側、裏面側の夫々の樹脂6の連結
面積を増加できるので、タブ4Aの周辺部分と樹脂6と
の密着性をより高め、より樹脂封止型半導体装置1の信
頼性を向上できる。Further, the opening 4D provided around the tab 4A has a slit-like planar shape that extends long and narrow along the periphery of the tab 4A. With this configuration, the opening area of the opening 4D in the peripheral portion of the tab 4A can be increased, and the connection area of the resin 6 on the front side and the back side of the tab 4A can be increased in the peripheral portion of the tab 4A. The adhesion between the peripheral portion of 4A and the resin 6 can be further improved, and the reliability of the resin-sealed semiconductor device 1 can be further improved.
また、周囲にタブ吊りリード4Eを連結するタブ4A上
に搭載された半導体ペレット2の外部端子2C、インナ
ーリード4Bの夫々が金属線5Aの表面に絶縁体5Bを
被覆した被覆ワイヤ5で接続され、前記タブ4A、半導
体ペレット2、インナーリード4B及び被覆ワイヤ5を
樹脂6で封止する樹脂封止型半導体装置1において、前
記タブ4Aとタブ吊りリード4Eとの連結部分(4F)
を除き、前記タブ4Aの周囲にこのタブ4Aの表面から
裏面に貫通する開口4Dを設ける。この構成により、前
記効果の他に、前記タブ4Aのタブ吊りリード4Eと連
結される連結領域(4F)の機械的強度を向上できる。Further, the external terminal 2C and the inner lead 4B of the semiconductor pellet 2 mounted on the tab 4A around which the tab suspension lead 4E is connected are connected by a coated wire 5 in which the surface of the metal wire 5A is coated with an insulator 5B. , in the resin-sealed semiconductor device 1 in which the tab 4A, the semiconductor pellet 2, the inner lead 4B, and the covered wire 5 are sealed with a resin 6, a connecting portion (4F) between the tab 4A and the tab suspension lead 4E;
An opening 4D is provided around the tab 4A, penetrating from the front surface to the back surface of the tab 4A. With this configuration, in addition to the above effects, the mechanical strength of the connection region (4F) connected to the tab suspension lead 4E of the tab 4A can be improved.
明細書の末尾に掲載した第1表に、本発明者が行った温
度サイクル試験の結果を示す。第1表は、本実施例Iの
タブ4Aの周辺部分に開口4Dを設けた樹脂封止型半導
体装置1、タブの周辺部分に開口を設けない従来の樹脂
封止型半導体装置の夫々の試験結果を示す、樹脂封止型
半導体装W1は、いずれも被覆ワイヤ5を強制的にタブ
4Aの周囲の端部に接触させ、この後樹脂封止を行い、
り一部フレーム4の切断成型を行った。温度サイクル試
験は、ペーパーリフロー後に、−50[”Cコ、155
[’C]の夫々の温度をいずれも30[分コつづ繰返し
与えた。第1表に示すように、従来の樹脂封止型半導体
装置は、100回の温度サイクルにおいては500個の
サンプル中1つも被覆ワイヤ5が断線する不良品が発生
しないが、1000回の温度サイクルにおいては30個
もの不良品が発生した。これに対して、本実施例Iの樹
脂封止型半導体装置1は、100回から1000回まで
の温度サイクル中、1つも不良品が発生しない結果を得
た。Table 1 listed at the end of the specification shows the results of a temperature cycle test conducted by the present inventor. Table 1 shows the tests of the resin-sealed semiconductor device 1 in which an opening 4D is provided around the tab 4A of Example I, and the conventional resin-sealed semiconductor device that does not have an opening around the tab. In each of the resin-sealed semiconductor devices W1 shown in the results, the coated wire 5 is forcibly brought into contact with the edge around the tab 4A, and then resin-sealed.
A part of the frame 4 was cut and molded. The temperature cycle test was performed after paper reflow at -50["Cco, 155
Each temperature ['C] was applied repeatedly for 30 [minutes]. As shown in Table 1, in the conventional resin-sealed semiconductor device, there is no defective product in which the coated wire 5 is broken in 500 samples after 100 temperature cycles, but after 1000 temperature cycles. There were as many as 30 defective products. In contrast, the resin-sealed semiconductor device 1 of Example I did not produce any defective products during the temperature cycles from 100 to 1000 times.
(実施例■)
本実施例■は、前記実施例Iの樹脂封止型半導体装置に
おいて、タブの周辺部分に開口を構成したことによる弊
害を低減した、本発明の第2実施例である。(Example 2) This example 2 is a second example of the present invention in which the disadvantages caused by forming an opening in the peripheral portion of the tab in the resin-sealed semiconductor device of Example I are reduced.
本発明の実施例■であるQFP構造の樹脂封止型半導体
装置を第3図(部分平面図)で示す。FIG. 3 (partial plan view) shows a resin-sealed semiconductor device having a QFP structure, which is Embodiment 2 of the present invention.
本実施例■の樹脂封止型半導体装tiは、前記実施例I
のスリット形状の開口4Dに変えて、タブ4Aの周辺部
分に平面形状が円形状の開口4Dを設ける。開口4Dは
タブ4Aの平面方形状の各辺に沿って複数個(前述のス
リットの個数に比べて多くの個数)配列される。開口4
Dの断面構造は前述と同様にタブ4Aの表面側から裏面
側に貫通する構造で構成される。この間口4Dは、その
配列方向において、開口4D間の連結領域の占有面積を
増加できる。The resin-sealed semiconductor device ti of this embodiment (2) is the same as that of the embodiment I
Instead of the slit-shaped opening 4D, an opening 4D having a circular planar shape is provided around the tab 4A. A plurality of openings 4D (a larger number than the number of slits described above) are arranged along each side of the planar rectangular shape of the tab 4A. opening 4
The cross-sectional structure of D is configured to penetrate from the front side to the back side of the tab 4A as described above. This frontage 4D can increase the area occupied by the connecting region between the openings 4D in the arrangement direction.
このように、被覆ワイヤ5を使用する樹脂封止型半導体
装置1において、タブ4Aにその周囲に沿って複数個の
開口4Dを配列する。この構成により、前記タブ4Aの
周辺部分でこのタブ4Aの開口4Dの内側(半導体ペレ
ット2側)、外側(インナーリード4B側)の夫々を連
結する連結領域の面積を増加し、タブ4A自体の機械的
強度を向上できる。In this way, in the resin-sealed semiconductor device 1 using the coated wire 5, a plurality of openings 4D are arranged in the tab 4A along its periphery. With this configuration, the area of the connection region that connects the inside (semiconductor pellet 2 side) and outside (inner lead 4B side) of the opening 4D of the tab 4A in the peripheral portion of the tab 4A is increased, and Mechanical strength can be improved.
なお、前記タブ4Aの周囲に配列される開口4Dは、平
面形状が円形状に限定されず、方形状、楕円形状等で構
成してもよい。Note that the planar shape of the openings 4D arranged around the tab 4A is not limited to a circular shape, but may be formed in a rectangular shape, an elliptical shape, or the like.
また、前記タブ4Aの周囲の端部等、被覆ワイヤ5が接
触する可能性がある領域(タッチを許容する領域)には
面取り或はアール(丸み付け)を付け、被覆ワイヤ5に
加わる応力集中を分散することにより、被覆ワイヤ5の
断線不良をより一層防止できる。In addition, areas where the covered wire 5 may come into contact (areas that allow touch), such as the edges around the tab 4A, are chamfered or rounded to reduce stress concentration on the covered wire 5. By dispersing the wires, breakage defects in the covered wire 5 can be further prevented.
以上、本発明者によってなされた発明を、前記実施例に
基き具体的に説明したが、本発明は、前記実施例に限定
されるものではなく、その要旨を逸脱しない範囲におい
て種々変更可能であることは勿論である。As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.
例えば、本発明は、QFP構造以外のDIP構造、LC
C構造、ZIP構造等の樹脂封止型半導体装置に適用で
きる。For example, the present invention applies to DIP structures other than QFP structures, LC
It can be applied to resin-sealed semiconductor devices such as C structure and ZIP structure.
また1本発明は、TAB構造等、被覆ワイヤを使用しか
つ一部分を樹脂で封止する樹脂封止型半導体装置に適用
できる。Furthermore, the present invention can be applied to a resin-sealed semiconductor device, such as a TAB structure, which uses a covered wire and partially seals it with resin.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
被覆ワイヤを使用する樹脂封止型半導体装置において、
前記被覆ワイヤの断線不良を防止できる。In resin-sealed semiconductor devices that use coated wire,
Breakage defects of the covered wire can be prevented.
被覆ワイヤを使用する樹脂封止型半導体装置の温度サイ
クルに対する信頼性を向上できる。The reliability against temperature cycles of a resin-sealed semiconductor device using covered wire can be improved.
前記効果の他に、前記効果を得ることによる弊害を低減
できる。In addition to the above-mentioned effects, the adverse effects caused by obtaining the above-mentioned effects can be reduced.
第1表Table 1
第1図は、本発明の実施例IであるQFP構造の樹脂封
止型半導体装置の要部断面図。
第2図は、前記樹脂封止型半導体装置の部分平面図、
第3図は、本発明の実施例■であるQFP構造の樹脂封
止型半導体装置の部分平面図である。
図中、1・・・樹脂封止型半導体装置、2・・・半導体
ペレット、2C・・・外部端子、4A・・・タブ、4B
・・・インナーリード、4D・・・開口、4E・・・タ
ブ吊りリード、4F・・・連結領域、5・・・被覆ワイ
ヤ、6・・・樹脂である。FIG. 1 is a sectional view of a main part of a resin-sealed semiconductor device having a QFP structure, which is Example I of the present invention. FIG. 2 is a partial plan view of the resin-sealed semiconductor device, and FIG. 3 is a partial plan view of the resin-sealed semiconductor device of the QFP structure, which is Embodiment (2) of the present invention. In the figure, 1...Resin-sealed semiconductor device, 2...Semiconductor pellet, 2C...External terminal, 4A...Tab, 4B
... Inner lead, 4D... Opening, 4E... Tab suspension lead, 4F... Connection area, 5... Covered wire, 6... Resin.
Claims (1)
ードの夫々が金属線の表面に絶縁体を被覆した被覆ワイ
ヤで接続され、前記タブ、半導体ペレット、リード及び
被覆ワイヤを樹脂で封止する樹脂封止型半導体装置にお
いて、前記タブの周囲にこのタブの表面から裏面に貫通
する開口を設けたことを特徴とする樹脂封止型半導体装
置。 2、前記タブの周囲に設けた開口はこのタブの周囲に沿
って細長く伸びる平面形状をスリット形状で構成したこ
とを特徴とする請求項1に記載の樹脂封止型半導体装置
。 3、前記タブの周囲に設けた開口はこのタブの周囲に沿
って複数個配列したことを特徴とする請求項1に記載の
樹脂封止型半導体装置。 4、周囲にタブ吊りリードを連結するタブ上に搭載され
た半導体ペレットの外部端子、リードの夫々が金属線の
表面に絶縁体を被覆した被覆ワイヤで接続され、前記タ
ブ、半導体ペレット、リード及び被覆ワイヤを樹脂で封
止する樹脂封止型半導体装置において、前記タブとタブ
吊りリードとの連結部分を除き、前記タブの周囲にこの
タブの表面から裏面に貫通する開口を設けたことを特徴
とする樹脂封止型半導体装置。[Claims] 1. Each of the external terminals and leads of the semiconductor pellet mounted on the tab is connected with a coated wire in which the surface of the metal wire is coated with an insulator, and the tab, the semiconductor pellet, the lead, and the coated wire What is claimed is: 1. A resin-sealed semiconductor device in which the tab is sealed with a resin, the resin-sealed semiconductor device being characterized in that an opening is provided around the tab to penetrate from the front surface to the back surface of the tab. 2. The resin-sealed semiconductor device according to claim 1, wherein the opening provided around the tab has a slit-like planar shape that extends long and narrow along the periphery of the tab. 3. The resin-sealed semiconductor device according to claim 1, wherein a plurality of openings are arranged around the tab. 4. External terminals and leads of the semiconductor pellet mounted on the tab that connect the tab hanging lead around the tab are connected to each other with a coated wire that is coated with an insulator on the surface of the metal wire, and the tab, semiconductor pellet, lead, and A resin-sealed semiconductor device in which a coated wire is sealed with resin, characterized in that an opening is provided around the tab to penetrate from the front surface to the back surface of the tab, except for the connecting portion between the tab and the tab suspension lead. A resin-sealed semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2143965A JPH0437050A (en) | 1990-05-31 | 1990-05-31 | Resin seal type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2143965A JPH0437050A (en) | 1990-05-31 | 1990-05-31 | Resin seal type semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0437050A true JPH0437050A (en) | 1992-02-07 |
Family
ID=15351174
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2143965A Pending JPH0437050A (en) | 1990-05-31 | 1990-05-31 | Resin seal type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0437050A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1994014194A1 (en) * | 1992-12-17 | 1994-06-23 | Vlsi Technology, Inc. | Void-free thermally enhanced plastic package |
FR2764115A1 (en) * | 1997-06-02 | 1998-12-04 | Sgs Thomson Microelectronics | SEMICONDUCTOR DEVICE AND METHOD FOR CONNECTING INTERNAL GROUND WIRES OF SUCH A DEVICE |
WO2003073500A1 (en) * | 2002-02-28 | 2003-09-04 | Infineon Technologies Ag | A substrate for a semiconductor device |
WO2024057838A1 (en) * | 2022-09-14 | 2024-03-21 | ローム株式会社 | Semiconductor device |
-
1990
- 1990-05-31 JP JP2143965A patent/JPH0437050A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1994014194A1 (en) * | 1992-12-17 | 1994-06-23 | Vlsi Technology, Inc. | Void-free thermally enhanced plastic package |
FR2764115A1 (en) * | 1997-06-02 | 1998-12-04 | Sgs Thomson Microelectronics | SEMICONDUCTOR DEVICE AND METHOD FOR CONNECTING INTERNAL GROUND WIRES OF SUCH A DEVICE |
EP0883181A1 (en) * | 1997-06-02 | 1998-12-09 | STMicroelectronics S.A. | Semiconductor device and process for connecting internal ground wires with such a device |
WO2003073500A1 (en) * | 2002-02-28 | 2003-09-04 | Infineon Technologies Ag | A substrate for a semiconductor device |
WO2024057838A1 (en) * | 2022-09-14 | 2024-03-21 | ローム株式会社 | Semiconductor device |
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