JPH0567708A - Packaging method for semiconductor integrated circuit - Google Patents
Packaging method for semiconductor integrated circuitInfo
- Publication number
- JPH0567708A JPH0567708A JP3229016A JP22901691A JPH0567708A JP H0567708 A JPH0567708 A JP H0567708A JP 3229016 A JP3229016 A JP 3229016A JP 22901691 A JP22901691 A JP 22901691A JP H0567708 A JPH0567708 A JP H0567708A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- element chip
- resin material
- sealing resin
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電子機器等に使用され
る半導体デバイスのパッケージ方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of packaging a semiconductor device used in electronic equipment or the like.
【０００２】[0002]
【従来の技術】従来の半導体デバイスのパッケージ方法
は、半導体素子チップとリードフレームのサイズが一致
したものを使用し、封止樹脂材料を出来る限り空洞が少
なくなるように完全封止していた。2. Description of the Related Art In a conventional semiconductor device packaging method, a semiconductor element chip and a lead frame having the same size are used, and a sealing resin material is completely sealed so as to have as few cavities as possible.
【０００３】[0003]
【発明が解決しようとする課題】最近の半導体集積回路
は、微細化、多層化、大チップ化が進んで来た。また、
半導体素子チップを収容するパッケージも大型化、多ピ
ン化、微細ピッチ化が進んできた。リードフレームのリ
ード端子の微細加工は限界に近い状態になっており、リ
ードフレームのアイランドのサイズも大きくなってしま
うという現象が起きている。しかし半導体素子チップ
は、微細化によりチップサイズが小さくなってきている
にも係わらず、リードフレームのアイランドサイズが大
きくなってしまっている為、半導体素子チップを大きく
しなければならないという時代に逆行する様な現象にな
ってしまっている。もし、アイランドサイズの大きいリ
ードフレームにチップサイズが小さい半導体素子チップ
を搭載する場合は、ボンディングワイヤを長く張らなけ
ればならず、樹脂封止する際にボンディングワイヤが流
れてしまい、ボンディングワイヤ同志の接触およびボン
ディングワイヤとアイランドの接触を起こし、製品の信
頼性が損なわれる原因となる。In recent semiconductor integrated circuits, miniaturization, multi-layering, and large chips have been advanced. Also,
The packages that accommodate semiconductor element chips have become larger, have more pins, and have finer pitches. The microfabrication of the lead terminals of the lead frame has reached the limit, and the size of the lead frame islands is increasing. However, the semiconductor element chip is becoming smaller due to the miniaturization, but the island size of the lead frame is becoming larger, which goes against the times when the semiconductor element chip must be made larger. It has become such a phenomenon. If a semiconductor element chip with a small chip size is to be mounted on a lead frame with a large island size, the bonding wire must be stretched for a long time. In addition, contact between the bonding wire and the island may occur, resulting in impaired product reliability.
【０００４】また、パッケージの大型化すると封止樹脂
材料の伸縮による破壊応力も著しく増加する。使用され
る周辺温度環境の変化が大きいほど、封止樹脂材料から
発生する破壊応力は大きくなる。さらには、半導体素子
チップも大きくなるに従い、半導体素子チップの収縮お
よび封止樹脂材料から発生する破壊応力を受ける度合が
増し、樹脂収縮時の応力が半導体素子チップの表面破壊
強度を越えた時、半導体素子チップの保護膜にクラック
等が発生し動作不良を起こす原因となる。また、封止樹
脂材料に吸収される水分による配線材の腐食、半導体素
子チップの配線材のスライド、断線、及び素子特性の劣
化が誘発され、半導体集積回路としての信頼性が損なわ
れるという課題があった。また、封止樹脂材料が伸縮す
ると、半導体素子チップの表面と封止樹脂材料の接触面
がズレるため、ボンディングワイヤが外れてしまう課題
もあった。さらには、封止樹脂材料の伸縮による破壊応
力が、半導体素子チップの保護膜を破壊するのを防止す
るために、半導体素子チップのコーナー部の配線にスリ
ットを入れ応力を吸収していた。しかし、配線材にスリ
ットを入れる方法では、スリットを入れた事により配線
幅が狭くなり電流容量が減ってしまう、あるいはチップ
サイズが大きくなってしまうという課題があった。そこ
で本発明は、前記課題を解決することにある。Further, as the package becomes larger, the breaking stress due to the expansion and contraction of the sealing resin material increases remarkably. The greater the change in the ambient temperature environment used, the greater the fracture stress generated from the sealing resin material. Furthermore, as the size of the semiconductor element chip also increases, the degree to which the semiconductor element chip contracts and the fracture stress generated from the encapsulating resin material increases, and when the stress during resin contraction exceeds the surface fracture strength of the semiconductor element chip, This may cause a crack or the like in the protective film of the semiconductor element chip to cause a malfunction. In addition, there is a problem that the corrosion of the wiring material due to the moisture absorbed by the sealing resin material, the sliding of the wiring material of the semiconductor element chip, the disconnection, and the deterioration of the element characteristics are induced, and the reliability as the semiconductor integrated circuit is impaired. there were. Further, when the encapsulating resin material expands and contracts, the contact surface between the surface of the semiconductor element chip and the encapsulating resin material deviates, and there is a problem that the bonding wire comes off. Further, in order to prevent the breaking stress due to the expansion and contraction of the sealing resin material from breaking the protective film of the semiconductor element chip, a slit is formed in the wiring at the corner of the semiconductor element chip to absorb the stress. However, the method of forming a slit in the wiring material has a problem that the wiring width is narrowed due to the slit and the current capacity is reduced, or the chip size is increased. Therefore, the present invention is to solve the above problems.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決するた
め、本発明の半導体集積回路のパッケージ方法は、リー
ドフレームのアイランドに半導体素子チップを搭載する
とともに、この半導体素子チップに設けたパッドをボン
ディングワイヤにより複数本のリードに接続し、これら
を封止樹脂材料により封止してなる半導体集積回路にお
いて、前記半導体素子チップおよびボンディングワイヤ
を絶縁材料により覆った後、封止樹脂材料により封止し
たことを特徴とする。In order to solve the above problems, a semiconductor integrated circuit packaging method according to the present invention mounts a semiconductor element chip on an island of a lead frame and bonds pads provided on the semiconductor element chip. In a semiconductor integrated circuit in which a plurality of leads are connected with wires and these are sealed with a sealing resin material, the semiconductor element chip and the bonding wires are covered with an insulating material and then sealed with a sealing resin material. It is characterized by
【０００６】[0006]
【実施例】以下に本発明の実施例を図面に基づいて説明
する。Embodiments of the present invention will be described below with reference to the drawings.
【０００７】図１は、本発明のパッケージ方法の一実施
例を示す断面図である。図１において、半導体素子チッ
プ１１はアイランド１２に接着剤で接着する。接着した
半導体素子チップ１１のパッドとリード部１３をボンデ
ィングワイヤ１４にて接続する。できた製品の半導体素
子チップ１１とリード部１３の周囲を軟粘性の絶縁材料
１５を塗布し乾燥して仮封止する。その後、封止樹脂材
料１７で封止して製品になる。FIG. 1 is a sectional view showing an embodiment of the packaging method of the present invention. In FIG. 1, the semiconductor element chip 11 is bonded to the island 12 with an adhesive. The bonded pad of the semiconductor element chip 11 and the lead portion 13 are connected by a bonding wire 14. A soft viscous insulating material 15 is applied to the periphery of the semiconductor element chip 11 and the lead portion 13 of the finished product, which is dried and temporarily sealed. After that, the product is sealed with the sealing resin material 17.
【０００８】図２は、本発明のパッケージ方法の他の実
施例を示す断面図である。図２において、半導体素子チ
ップ２１はアイランド２２に接着剤で接着する。接着し
た半導体素子チップ２１のパッドとリード部２３をボン
ディングワイヤ２４にて接続する。できた製品の半導体
素子チップ２１とリード部２３の周囲を液体もしくは霧
状の絶縁材料２５を塗布し乾燥した後、封止樹脂材料２
７で封止して製品になる。FIG. 2 is a sectional view showing another embodiment of the packaging method of the present invention. In FIG. 2, the semiconductor element chip 21 is bonded to the island 22 with an adhesive. The bonded pad of the semiconductor element chip 21 and the lead portion 23 are connected by a bonding wire 24. A liquid or mist-like insulating material 25 is applied around the semiconductor element chip 21 and the lead portion 23 of the finished product and dried, and then the sealing resin material 2
The product is sealed with 7.
【０００９】以上により、半導体素子チップおよびボン
ディングワイヤを絶縁材料により覆った後、封止樹脂材
料により封止したことにより前記課題を防止している。As described above, the above problem is prevented by covering the semiconductor element chip and the bonding wire with the insulating material and then sealing with the sealing resin material.
【００１０】[0010]
【発明の効果】本発明により、樹脂封止する際に発生す
るボンディングワイヤ同志の接触およびボンディングワ
イヤとアイランドの接触を防止できる。また、半導体素
子チップとリードフレームのサイズが一致したものを使
用しなくても良くなるため、リードフレームの品種削減
になる。さらには、半導体素子チップのチップサイズが
小さいまま使用できるため、封止樹脂材料から発生する
破壊応力による半導体素子チップの破壊を減少すること
ができ、信頼性が向上し、納期およびコストなどを削減
することができるという効果もある。According to the present invention, it is possible to prevent the bonding wires from coming into contact with each other and the bonding wires from coming into contact with each other when the resin is sealed. Further, since it is not necessary to use a semiconductor element chip and a lead frame having the same size, it is possible to reduce the types of lead frames. Furthermore, since the semiconductor element chip can be used with its small size, it is possible to reduce the damage of the semiconductor element chip due to the fracture stress generated from the encapsulating resin material, improve the reliability, and reduce the delivery time and cost. There is also an effect that can be done.
【図１】本発明の半導体集積回路のパッケージ方法の一
実施例を示す断面図。FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor integrated circuit packaging method according to the present invention.
【図２】本発明の半導体集積回路のパッケージ方法の他
の実施例を示す断面図。FIG. 2 is a sectional view showing another embodiment of the semiconductor integrated circuit packaging method of the present invention.
１１‥‥半導体素子チップ １２‥‥アイランド １３‥‥リード端子 １４‥‥ボンディングワイヤ １５‥‥軟粘性の絶縁材料を塗布後、乾燥した仮封止材
料 １６‥‥樹脂封止材料 ２１‥‥半導体素子チップ ２２‥‥アイランド ２３‥‥リード端子 ２４‥‥ボンディングワイヤ ２５‥‥液体もしくは霧状の絶縁材料を塗布後、乾燥し
た仮封止絶縁材料 ２６‥‥樹脂封止材料11: Semiconductor element chip 12: Island 13: Lead terminal 14: Bonding wire 15: Temporary encapsulating material dried after applying a soft-viscosity insulating material 16: Resin encapsulating material 21: Semiconductor element Chip 22 ... Island 23 ... Lead terminal 24 ... Bonding wire 25 ... Dry or temporary insulating material applied after applying liquid or mist-like insulating material 26 ... Resin sealing material
Claims (1)
チップを搭載するとともに、この半導体素子チップに設
けたパッドをボンディングワイヤにより複数本のリード
に接続し、これらを封止樹脂材料により封止してなる半
導体集積回路において、前記半導体素子チップおよびボ
ンディングワイヤを絶縁材料により覆った後、封止樹脂
材料により封止したことを特徴とする半導体集積回路の
パッケージ方法。1. A semiconductor element chip is mounted on an island of a lead frame, pads provided on the semiconductor element chip are connected to a plurality of leads by bonding wires, and these are sealed by a sealing resin material. In a semiconductor integrated circuit, the semiconductor element chip and the bonding wire are covered with an insulating material, and then sealed with a sealing resin material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3229016A JPH0567708A (en) | 1991-09-09 | 1991-09-09 | Packaging method for semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3229016A JPH0567708A (en) | 1991-09-09 | 1991-09-09 | Packaging method for semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0567708A true JPH0567708A (en) | 1993-03-19 |
Family
ID=16885439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3229016A Pending JPH0567708A (en) | 1991-09-09 | 1991-09-09 | Packaging method for semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0567708A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6818968B1 (en) * | 2000-10-12 | 2004-11-16 | Altera Corporation | Integrated circuit package and process for forming the same |
| US7202109B1 (en) * | 2004-11-17 | 2007-04-10 | National Semiconductor Corporation | Insulation and reinforcement of individual bonding wires in integrated circuit packages |
| CN104392969A (en) * | 2014-10-13 | 2015-03-04 | 华东光电集成器件研究所 | Impact-resistant packaging structure of multi-chip integrated circuit |
-
1991
- 1991-09-09 JP JP3229016A patent/JPH0567708A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6818968B1 (en) * | 2000-10-12 | 2004-11-16 | Altera Corporation | Integrated circuit package and process for forming the same |
| US7202109B1 (en) * | 2004-11-17 | 2007-04-10 | National Semiconductor Corporation | Insulation and reinforcement of individual bonding wires in integrated circuit packages |
| CN104392969A (en) * | 2014-10-13 | 2015-03-04 | 华东光电集成器件研究所 | Impact-resistant packaging structure of multi-chip integrated circuit |
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