JP2894007B2 - Flat package type semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat package type semiconductor device having a capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art An LSI for a high-speed logic circuit consumes a large amount of power, and noise is induced in a power supply system every time circuit operation is switched, and the circuit often malfunctions.

There is known a flat package type semiconductor device in which a capacitor is mounted near an IC chip on a package in order to absorb noise generated in the power supply system and prevent malfunction.

A conventional flat package type semiconductor device will be described along a method of manufacturing the same.

As shown in FIG. 10, a cavity 11 for mounting an IC chip, capacitor connection pads 12-1 and 12-2 disposed around the cavity 11, and external lead electrodes 13 disposed around the periphery are formed. A lead of a lead frame is attached to the ceramic substrate 1 having the IC chip (not shown) mounted in the cavity 11, and an electrode pad of the IC chip is bonded to a pad formed around the cavity 11 by bonding. Cover and seal.

Next, the capacitor connection pads 12-1 and 12-1
2-2. Place solder cream on top and heat with chip capacitor 4 placed on top to melt solder cream.
The capacitor electrodes 41-1 and 41-2 are connected to the capacitor connection pads 12-1 and 12-2, respectively.

Next, as shown in FIG. 11, the leads 22 are separated from the frame 21.

[0008]

In this conventional flat package type semiconductor device, a solder cream is placed on a capacitor connection pad, and a capacitor is placed on the solder cream.
When the solder cream is melted by heating to connect the capacitor electrode and the capacitor connection pad, there is a problem that the solder is scattered and adheres to the leads, and the leads are short-circuited, resulting in a defect.

Also, as shown in FIG. 11, an electrical test is performed after the lead is separated from the frame, and then the lead is handed over to the user. When the diameter of the frame becomes narrow, it is easily deformed during the transporting operation, and an external shape defect or a short-circuit defect occurs. Therefore, in order to avoid the defect as much as possible, it is necessary to trade with the frame left as shown in FIG. Some things have to be done. Even if the characteristics of the IC chip are checked, the reliability is inevitably reduced.

[0010]

According to the present invention, there is provided a flat package type semiconductor device comprising a cavity for mounting an IC chip, a capacitor connection pad disposed around the cavity, and an external lead electrode disposed around the periphery. Having a ceramic substrate and an I connected to a pad mounted on the cavity and formed around the cavity.
A C chip, a cap sealed over the cavity, a capacitor connected to the capacitor connection pad, a lead bonded to the external lead electrode, and an insulating film or insulating material attached to the lead And a tape. Further, a method of manufacturing a flat package type semiconductor device according to the present invention is directed to a ceramic substrate having a cavity for mounting an IC chip, a capacitor connection pad disposed around the cavity, and an external lead electrode disposed around the periphery. Bonding a lead of a lead frame to the external lead electrode, mounting an IC chip in the cavity, covering the cavity with a cap, and sealing a hole corresponding to the ceramic substrate. A step of attaching an insulating film having the following to the lead, and a step of placing a capacitor on the capacitor connection pad via a solder cream and then heating to connect the electrode of the capacitor to the capacitor connection pad. It is.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a first embodiment of the present invention, referring to FIG. 1, a lead 22 of a lead frame 2 is joined to an external lead electrode of a package 1, and An IC chip (not shown) is mounted, bonded, covered with a cap 3, and sealed.

Next, as shown in FIG.
a is attached to the lead frame 2.

The insulating 5a film is an approximately square polyimide film having a thickness of 100 μm, and has a square hole 51a at the center. The size of the hole 51a is substantially the same as that of the ceramic substrate 1. Also, a cut 55a is provided along the outer side. That is, the insulating film main body 52a and the insulating outer frame 53a are connected by the connecting piece 54a. In order to attach the insulating film 5a to the lead frame 2, for example, thermocompression bonding is performed at about 150 ° C.
An appropriate adhesive may be used.

Next, the capacitor connection pads 12-1, 1
2-2. A solder cream is placed on the chip 2-2, and the chip capacitor 4 is placed on the solder cream.
1-1 and 41-2 are connected to the capacitor connection pads 12-1 and 1
2-2 is soldered. Even if the solder cream is scattered in this step, most of the lead surface is covered with the insulating film, so that a short circuit does not occur.

Next, as shown in FIG. 3, the connecting piece 54a and the lead 22 are cut at the cut position. Since it is held by the insulating film 52a at the time of this cutting process, it is possible to prevent the lead pitch from becoming uneven.

The insulating film 52a may be removed at any stage before checking electrical characteristics, before mounting, or after mounting. Alternatively, it may be left after mounting.

Next, a second embodiment will be described.
As shown in FIG. 4, the connecting piece 6 is attached to the insulating film main body 52a.
An insulating tape 6a connected by 1a is provided. next,
As shown in FIG. 5, separate from the frame.

Before checking the electrical characteristics, the insulating film 5
b can be removed and the insulating tape 6a can be left. In this case, the insulating tape 6a can be left after mounting. Therefore, compared to the first embodiment, it is possible to more reliably prevent the lead pitch from being uneven.

Next, a third embodiment will be described.
As shown in FIG. 6, an insulating film 5c having a wide cut 56a is used on the frame side of the lead, and the length of the lead is shortened as shown in FIG. As compared with the first embodiment, the present invention can be applied to the case where the lead length is short.

Next, a fourth embodiment will be described.
As shown in FIG. 8, the lead is cut short using an insulating film 5d provided with an insulating tape 6b next to the wide cut 56b, as shown in FIG. The present invention can be applied to a device having a shorter lead than that of the second embodiment.

[0021]

As described above, the present invention provides a chip capacitor on a capacitor connection pad by forming an insulating film made of polyimide or the like on a lead frame bonded to a ceramic substrate on which an IC chip is mounted. Can be prevented from being scattered at the time of solder connection and short-circuiting between leads. In addition, since a part of the insulating film has a cut for cutting the lead, the lead can be cut with the insulating film adhered to the lead frame. This has the effect of improving yield and reliability.

[Brief description of the drawings]

FIG. 1 is a plan view used for explaining a first embodiment of the present invention.

FIG. 2 is a plan view used for explaining the first embodiment of the present invention.

FIG. 3 is a plan view used for explaining the first embodiment of the present invention.

FIG. 4 is a plan view used for explaining a second embodiment.

FIG. 5 is a plan view used for describing a second embodiment.

FIG. 6 is a plan view used for describing a third embodiment.

FIG. 7 is a plan view used for describing a third embodiment.

FIG. 8 is a plan view used for describing a fourth embodiment.

FIG. 9 is a plan view used for explaining a fourth embodiment.

FIG. 10 is a plan view used for explaining a conventional technique.

FIG. 11 is a plan view used for explaining a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Ceramic substrate 11 Cavity 12-1 and 12-2 Capacitor connection electrode 13 External lead electrode 2 Lead frame 21 Frame 22 Lead 3 Cap 4 Chip capacitor 5a-5d Insulation film 51a-51d Hole 52a-52d Insulation film main body 53a-53d Insulating film outer frame 54a-54d Connecting piece 55a-55d Cut 56a, 56b Wide cut 6a, 6b Insulating tape 61a, 61b Connecting piece

Claims (2)

(57) [Claims] 1. A ceramic substrate having a cavity for mounting an IC chip, a capacitor connection pad disposed around the cavity, and an external lead electrode disposed on the periphery, and the cavity mounted on the cavity. An IC chip connected to pads formed in the periphery, a cap sealed to cover the cavity, a capacitor connected to the capacitor connection pad, and a lead bonded to the external lead electrode; A flat package type semiconductor device comprising an insulating film or an insulating tape attached to a lead. 2. A lead frame lead to the external lead electrode of a ceramic substrate having a cavity on which an IC chip is mounted, a capacitor connection pad disposed around the cavity, and an external lead electrode disposed around the periphery. Bonding, mounting an IC chip in the cavity, covering the cavity with a cap, and attaching an insulating film having a hole corresponding to the ceramic substrate to the lead. Manufacturing a flat package type semiconductor device, comprising the steps of: placing a capacitor on the capacitor connection pad via a solder cream, and then heating to connect the electrode of the capacitor to the capacitor connection pad. Method.