JP2003218316A - Multichip package structure and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multichip package structure and a manufacturing method. <P>SOLUTION: The structure is provided with a substrate and multiple chips positioned above the substrate. The respective chips are electrically connected with the substrate by a bonding system and several adhesive layers are positioned between the two chips. They are made into a sandwiched shape and few spaces are covered into the adhesive layers. They support the respective chips and they are covered with sealing resin so as to protect multichip package structure. A space does not exist between the chips and wire bonding can easily be controlled. Wire bonding can precisely be performed and the yield of a process improves. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip package structure and a manufacturing method, and more particularly, two or more chips having the same or different functions are stacked in the same package, and a suspension area is provided between two chips. No multi-chip package structure and manufacturing method.

[0002]

2. Description of the Related Art The current trend in semiconductor manufacturing is how to reduce the cost while pushing many logic circuits into a small semiconductor package. is there. Therefore, research and competition in this area are extremely fierce. In addition to research on reducing the minimum element size of chip circuit design, there is a method of directly doubling the storage capacity of a single semiconductor package at the lowest cost by pushing two or more chips into the same package.

The most common multi-chip package structure is the side-by-side multi-chip package structure, which mounts two or more chips in parallel with each other on the main mounting surface of the joint board. The connection between the chip and the conductive circuit on the common substrate is generally achieved by wire bonding. However, a drawback of this parallel-type multi-chip package structure is that the package efficiency is too low, which increases the area of the substrate due to the increase in the number of chips.

FIG. 1 is a multi-chip stack device described in US Pat. No. 5,323,060, which is
The semiconductor chip 110 is provided on the substrate 120 and electrically connected to the substrate 120, and the second semiconductor chip 130 is stacked on the first semiconductor chip 110 and electrically connected to the substrate 120. The feature is that one resin layer 140 provided between two chips is used.
The bonding wire arc (the loo
It is to provide the clearance required by ps of the bonding wires. In addition, the thickness of the resin layer 140 must be greater than the loop height of the bonding wire, which is the distance between the front surface of the first semiconductor chip 110 and the wire arc apex of the bonding wire 150. This prevents the second semiconductor chip 130 from coming into contact with the wire arc of the bonding wire 150.

Known wire bonding techniques for forming a wire connection between a chip bonding pad and a substrate bonding pad generally include (a) ball bonding to the chip bonding pad,
(B) Line arc formation between chip bonding pad and substrate bonding pad, and (c) stitch bond to substrate bonding pad.
The bonding wire connection is completed by d). Generally, the arc height is about 10 to 15 mil. By adjusting the wire arc variables, geometry and type, known wire bonding techniques can reduce arc height to about 6 mils. However, lowering it further damaged the wire and lowered its pulling force.

Therefore, according to the well-known bonding wire technique, the thickness of the resin layer 140 must be greater than 8 mil, so that the second semiconductor chip 130 can be completely in contact with the wire arc of the bonding wire 150. Can be prevented. The material of the resin layer 140 is generally epoxy resin or tape. However, it is very difficult to form an epoxy resin layer having a thickness of 8 mil. In addition, the use of a tape having a thickness of 8 mils significantly increases the manufacturing cost on the one hand, and on the other hand, the thermal expansion coefficient mismatch (CTE mism) between the resin layer 140 and the silicon chip.
The reliability of the package structure manufactured by ATC has been severely impaired.

Therefore, the US patent No. 6 shown in FIG.
Another type of multi-chip package stack device described in No. 005778 was provided. That is, the first semiconductor chip 110 is provided on the substrate 120 and electrically connected to the substrate 120, and the second semiconductor chip 130 is stacked on the first semiconductor chip 110 and the substrate 1
It is electrically connected to 20. This US Patent No. 6
The characteristic of No. 57878 is that the spacers 160 provided between the two chips cause the loops of the bonding wire 150.
The void (c) required by the bonding wires
It is to provide (learance). In addition, the spacer 160 made of a metal conductive material can be used as a ground plane of a semiconductor chip and is also used for mounting a capacitor. However, US Patent No. 6005778 spacer 160 is already US Patent No. 5323060.
Although it solves the drawbacks of the resin layer 140 of No. 1), the spacer needs to be smaller than the actual chip size, so that when the chips of the upper layer are stacked, that is, the spacer and the suspended area can be generated. This structure causes difficulty in the process of wire bonding to the upper layer chip, and the bonding wire is apt to move, its accuracy is affected, the process yield is lowered, and the competitiveness is affected. Gave.

[0008]

SUMMARY OF THE INVENTION A main object of the present invention is to provide a multi-chip package structure and a manufacturing method capable of easily controlling wire bonding.

Another object of the present invention is to provide a multi-chip package structure and a manufacturing method capable of accurately performing wire bonding.

Still another object of the present invention is to provide a multi-chip package structure and a manufacturing method capable of effectively increasing the yield of the wire bonding process.

[0011]

According to a first aspect of the present invention, there are provided a substrate, a plurality of chips located above the substrate and electrically connected to the substrate by a wire bonding method, and two chips each. The multi-chip package structure is characterized in that it has a few adhesive layers that are sandwiched between them to form a sandwich, and some spacers that are coated in each adhesive layer and support each chip. . The invention according to claim 2 provides the multi-chip package structure according to claim 1, wherein the multi-chip package structure is covered with a sealing resin to protect the multi-chip package structure. According to a third aspect of the present invention, in the method of manufacturing a multi-chip package structure, (a) a step of joining the first chip onto the substrate, (b) a step of electrically connecting the first chip to the substrate by a wire bonding method. , (C) first spacer smaller than the size of the first chip
Step of bonding on the first chip with an adhesive layer, (d) coating with a second adhesive layer, bonding a second chip with the second adhesive layer, of which the spacer is the first adhesive layer and the second adhesive layer A step of forming an adhesive layer that covers the inside of the substrate, and forming a sandwich with the first chip, the adhesive layer and the second chip, (e) a second chip and a substrate by a wire bonding method. The method of manufacturing a multi-chip package structure is characterized by including electrically connecting steps and the above steps. According to a fourth aspect of the present invention, in the method of manufacturing the multi-chip package structure,
4. The method for manufacturing a multi-chip package structure according to claim 3, wherein after the step (e), the steps (c) to (e) are repeated to complete the multi-chip package. I am trying. According to a fifth aspect of the present invention, in the method for manufacturing a multi-chip package structure, after the step (e), (f) a step of molding the multi-chip package structure with a sealing resin to protect the multi-chip package structure, The method of manufacturing a multi-chip package structure according to claim 3 or 4, further comprising:

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention provides a kind of multi-chip package structure, which comprises a substrate, a plurality of chips located above the substrate, and each chip is electrically connected to the substrate by a wire bonding method. Connected, some adhesive layers are located between each two chips, sandwich it, some spacers are coated in each adhesive layer,
Support each chip.

The present invention provides a method of manufacturing a multi-chip package structure, which includes the following steps:
That is, (a) a step of bonding the first chip onto the substrate, (b) a step of electrically connecting the first chip to the substrate by a wire bonding method, and (c) a spacer smaller than the size of the first chip. Step of bonding on the first chip with the first adhesive layer, (d) coating with the second adhesive layer, bonding the second chip, of which the first adhesive layer and the second adhesive layer cover the spacer inside Forming one adhesive layer and forming a sandwich with the first chip, the adhesive layer and the second chip, (e) electrically connecting the second chip to the substrate by a wire bonding method. Steps to take.

Preferably, step (c) and step (e) are further repeated to complete more multi-chip packages.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a multi-chip package structure and manufacturing method, in which two or more chips having the same or different functions are stacked in the same package and a suspended area is eliminated between each two chips. The package structure and the manufacturing method. The multi-chip package structure of the present invention includes a substrate, a plurality of chips located above the substrate and electrically connected to the substrate by a wire bonding method, and sandwiched between two chips. It comprises a few adhesive layers to be formed and a few spacers coated in each adhesive layer to support each chip.

Please refer to FIG. FIG. 3 shows a first embodiment of the multi-chip package structure of the present invention. 4 to 9 show an embodiment of the manufacturing steps of the first embodiment of FIG.

According to the first embodiment of the present invention shown in FIG. 3, the multi-chip package structure 2 includes a plurality of chips,
It comprises one substrate 23, some adhesive layers and some spacers. The plurality of chips are located above the substrate 23 and include a first chip 21 and a second chip 22 in the present embodiment, and each of the chips 21 and 22 has an operating surface 210, 220 (A).
active side) and non-actuating surface 211, 221
(Inactive Side). The operating surfaces 210 and 220 are one side surface on which the circuit design of the chips 21 and 22 is provided, and a plurality of connecting pads 2 are provided at predetermined positions of the operating surfaces 210 and 220 of the chips 21 and 22, respectively.
12, 222 are provided to serve as an interface for connecting the circuits of the chips 21 and 22 to the outside world. In this embodiment, the connection pads 212 and 222 are metal pads or aluminum pads (Al Pads).

A plurality of connecting pads 212, 2 on the working surface 210 of the first chip 21 and the working surface 220 of the second chip 22.
22 is electrically connected to the substrate 23 by the bonding wires 213 and 223, and the non-operating surface 21 of the first chip 21.
1 is bonded to the substrate 23. In this embodiment, the first
The non-operating surface 211 of the chip 21 is bonded to the substrate 23 by the chip adhesive layer 24, and the chip adhesive layer 24 has a hot-melt double-sided adhesive tape (Dual-Sided Adhesives).
iv Tape), silver wax, epoxy resin and other materials having adhesiveness.

The slight adhesive layer is located between the two chips and forms a sandwich, and the adhesive layer 2 in this embodiment is
5 includes a first adhesive layer 250 and a second adhesive layer 251, of which the first adhesive layer 250 is used to adhere the spacer 26, and the second adhesive layer 251 includes the first chip 21 and the second chip 22. Fill the void positions between the two
The chip 22 adheres tightly and flatly to the second adhesive layer 251. In practice, the first adhesive layer 250 and the second adhesive layer 251 may be made of a hot-melt double-sided tape, silver wax, epoxy resin or other adhesive material, and therefore, it can be seen from the whole adhesive layer 25. Then, a spacer 26 is covered in the adhesive layer 25 and is used to support the second chip 22.

Due to the sandwich-like structure shown in FIG. 3, there is no gap between the first chip 21 and the second chip 22. Therefore, the multi-chip package structure 2 of the present invention can easily control the wire bonding, In addition, the wire bonding can be performed accurately, and the process yield can be effectively increased. The first chip 21 and the second chip 22 may be chips having different functions. For example, the first chip 21 is a logic circuit chip, and the second chip 22 is
Can be a chip of a memory circuit. As a result, chips having several different functions can be provided in the same IC, and the IC design and use elasticity can be increased to a large extent. Of course, the first chip 21 and the second chip 22 may be chips having the same function, as those skilled in the semiconductor can easily think of by the above description.

4 to 9 are preferred step embodiments of the method of manufacturing the multi-chip package structure of the first embodiment shown in FIG. It involves the following steps: (A) The non-operating surface 211 of the first chip 21 is bonded onto the substrate 23 by the chip adhesive layer 24. (B) By the wire bonding method, the connecting pad 212 on the operating surface 210 of the first chip 21 is connected to the substrate 23 by the gold wire 213, and the circuit of the first chip 21 is connected to the substrate 23 via the gold wire 213. The substrate 23 is electrically connected to the outside world. (C) The gold wire 2 provided to be smaller than the size of the first chip 21.
The spacer 26, which is prevented from contacting with the spacer 13, is bonded to the working surface 210 of the first chip 21 by the first adhesive layer 250. (D) Covering with the second adhesive layer 251, covering the exposed portion of the operating surface 210 of the first chip 21 and the exposed portion of the spacer 26 and the first adhesive layer 250, and applying the second adhesive layer to the second adhesive layer.
Used to bond the non-actuating surface 221 of the chip 22, of which the first adhesive layer 250 and the second adhesive layer 251 form one adhesive layer 25 that internally coats the spacer 26,
In addition, the first chip 21, the adhesive layer 25, and the second chip 22 form a sandwich structure. (E) Using the wire bonding method, the connecting pad 222 on the operating surface 220 of the second chip 22 is connected to the substrate 2 by the gold wire 223.
3, the circuit of the second chip 22 is electrically connected to the substrate 23 by the gold wire 223, and the multi-chip package structure 2 is completed. (F) Further, the multi-chip package is protected by molding with a sealing resin 27 to form a complete multi-chip package structure 2.

In the second embodiment shown in FIG. 10, in the multi-chip package structure 3, the first chip 31 is bonded to the substrate 33 by the chip adhesive layer 34, and then the circuit of the first chip 31 is formed by the wire bonding method. Is electrically connected to the substrate 33, and thereafter, steps (c) to (e) of the first embodiment are repeated, and the spacer 36a is attached to the first adhesive layer 35.
0a and the adhesive layer 35a composed of the second adhesive layer 351a, and the second chip 32 is bonded by the adhesive layer 35a, and the spacer 36b is composed of the first adhesive layer 350b and the second adhesive layer 351b. And the third chip 37 is joined by the adhesive layer 35b, and the spacer 36c
Is covered with a pressure-sensitive adhesive layer 35c composed of a first pressure-sensitive adhesive layer 350c and a second pressure-sensitive adhesive layer 351c, and a fourth chip 38 is bonded by the pressure-sensitive adhesive layer 35c, and finally molded with a sealing resin 39 to form the multi-chip package. Cover and protect the structure. There is still no gap between the chips,
Therefore, even if more chips are packaged, the control of wire bonding is not affected, the accuracy of wire bonding does not decrease, and the process yield and speed can be effectively increased.

FIG. 11 shows a first embodiment of the present invention and an embodiment of external coupling, in which a plurality of solder bumps 4 are provided on the substrate 23 of the multi-chip package structure 2 and the solder bumps 4 are provided. It is used to combine with other substrates to complete electrical connection. FIG. 12 shows the first of the present invention.
7 shows another embodiment of the coupling of the embodiment with the outside world, of which
The substrate of the multi-chip package structure 2 is combined with another substrate by inserting the pin 5 to complete electrical connection. Naturally, as those skilled in the semiconductor can easily think of based on the above description, the above-mentioned method is also used for coupling the second embodiment with the outside world, or other conventional method is used. can do.

[0024]

In summary, according to the multi-chip package structure and the manufacturing method of the present invention, not only the control of the wire bonding method is facilitated, but also the wire bonding can be performed more accurately, and the process yield is effectively increased. Increase. In addition, the multi-chip package structure and the manufacturing method of the present invention can include several kinds of chips having different functions or chips having the same functions at the same time in the same IC, greatly increasing the design and use elasticity of the IC, and the overall structure is very large. Easy to
Both volume area and length are relatively small, the process is simple and the manufacturing cost is very low.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an example of a multi-chip package structure according to a known technique.

FIG. 2 is a diagram illustrating another embodiment of a multi-chip package structure according to a known technique.

FIG. 3 is a diagram of a first embodiment of a multi-chip package structure of the present invention.

FIG. 4 is a schematic view showing a preferred manufacturing method step embodiment of the manufacturing method of the multi-chip package structure of the embodiment of FIG. 3;

5 is a schematic view showing a preferred manufacturing method step embodiment of the manufacturing method of the multi-chip package structure of the embodiment of FIG. 3; FIG.

FIG. 6 is a schematic view showing a preferred manufacturing method step embodiment of the manufacturing method of the multi-chip package structure of the embodiment of FIG. 3;

FIG. 7 is a view showing a preferred manufacturing method step embodiment of the manufacturing method of the multi-chip package structure of the embodiment of FIG. 3;

FIG. 8 is a view showing a preferred manufacturing method step embodiment of the manufacturing method of the multi-chip package structure of the embodiment of FIG. 3;

FIG. 9 is a schematic view showing a preferred manufacturing method step embodiment of the manufacturing method of the multi-chip package structure of the embodiment of FIG. 3;

FIG. 10 is a second multi-chip package structure of the present invention.
FIG.

FIG. 11 is a schematic view showing a preferred embodiment of the coupling between the first embodiment of the present invention and the outside world.

FIG. 12 is a schematic view of another preferred embodiment of the external connection according to the first embodiment of the present invention.

[Explanation of symbols]

2 Multi-chip package structure 23 board 21 First Chip 22 Second chip 210, 220 working surface 211,221 Non-operating surface 212, 222 Connection pad 213, 223 Bonding wire (or gold wire) 24 chip adhesive layer 25 Adhesive layer 250 First adhesive layer 251 second adhesive layer 26 Spacer 27 Sealing resin 3 Multi-chip package structure 31 First chip 34 Chip adhesive layer 33 substrate 36a spacer 350a First adhesive layer 351a Second adhesive layer 35a adhesive layer 32 Second chip 36b spacer 350b First adhesive layer 351b Second adhesive layer 35b adhesive layer 37 Third Chip 36c spacer 350c First adhesive layer 351c Second adhesive layer 35c adhesive layer 38 4th chip 39 Sealing resin 4 Solder bump 5 pin

Claims (5)

[Claims] 1. A substrate, a plurality of chips located above the substrate and electrically connected to the substrate by a wire bonding method, and a sandwich formed between each two chips. A multi-chip package structure, comprising: an adhesive layer of, and a plurality of spacers that are coated in each adhesive layer and support each chip. 2. The multi-chip package structure according to claim 1, wherein the multi-chip package structure is covered with a sealing resin to protect the multi-chip package structure. 3. A method of manufacturing a multi-chip package structure, comprising the steps of: (a) bonding a first chip onto a substrate; (b) electrically connecting the first chip to the substrate by wire bonding. c) bonding a spacer smaller than the size of the first chip onto the first chip with a first adhesive layer, (d) covering with a second adhesive layer and bonding a second chip with the second adhesive layer, A first adhesive layer and a second adhesive layer of which form one adhesive layer that internally coats the spacer, and
A step of forming a sandwich with the chip, the adhesive layer and the second chip; (e) a step of electrically connecting the second chip to a substrate by a wire bonding method; A method of manufacturing a multi-chip package structure. 4. The method of manufacturing a multi-chip package structure according to claim 4, wherein after step (e), steps (c) to (e) are repeated to complete the multi-chip package. The method of manufacturing the multi-chip package structure according to claim 3. 5. The method for manufacturing a multi-chip package structure, comprising the step of (e) after the step of (e) molding the multi-chip package structure with a sealing resin to protect the multi-chip package structure. The method of manufacturing a multi-chip package structure according to claim 3 or 4, characterized in that.