JP2004158747A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device Download PDF

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Publication number
JP2004158747A
JP2004158747A JP2002324841A JP2002324841A JP2004158747A JP 2004158747 A JP2004158747 A JP 2004158747A JP 2002324841 A JP2002324841 A JP 2002324841A JP 2002324841 A JP2002324841 A JP 2002324841A JP 2004158747 A JP2004158747 A JP 2004158747A
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Prior art keywords
semiconductor
semiconductor device
manufacturing
semiconductor element
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JP2002324841A
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Japanese (ja)
Inventor
Hitoshi Kawaguchi
均 川口
Toyomasa Takahashi
高橋　　豊誠
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Sumitomo Bakelite Co Ltd
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Sumitomo Bakelite Co Ltd
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Priority to JP2002324841A priority Critical patent/JP2004158747A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which is not restricted by the size of a plurality of laminated semiconductor elements in a semiconductor package, having such semiconductor elements. <P>SOLUTION: In the method for manufacturing a semiconductor device, a plurality of semiconductor elements are stacked and sealed in a single semiconductor package, and at least one of the elements is connected between the elements and to the exterior of the package by wire bonding via gold wires. A spacer, having a height higher than the highest point of loops of the golden wire, is formed on the entire element functional surface other than input/output terminals of the elements connected by the golden wires and a wire bonding interference zone. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、複数個の半導体素子を積み重ねてパッケージングする際に半導体パッケージの生産性を向上させる技術を提供するものである。
【０００２】
【従来の技術】
近年の電子機器の高機能化並びに軽薄短小化の要求に伴い、電子部品の高密度集積化、さらには高密度実装化が進んできている。これらの電子機器に使用される半導体パッケージは、小型化かつ多ピン化してきており、また、半導体パッケージを含めた電子部品を実装する、実装用基板も小型化してきている。さらには電子機器への収納性を高めるため、リジット基板とフレキシブル基板を積層し一体化して、折り曲げを可能としたリジットフレックス基板が、実装用基板として使われるようになってきている。
【０００３】
半導体パッケージはその小型化に伴って、従来のようなリードフレームを使用した形態のパッケージでは、小型化に限界がきているため、最近では回路基板上にチップを実装したものとして、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）や、ＣＳＰ（Ｃｈｉｐ Ｓｃａｌｅ Ｐａｃｋａｇｅ）と言った、エリア実装型の新しいパッケージ方式が提案されている。これらの半導体パッケージにおいて、半導体チップの電極と従来型半導体パッケージのリードフレームの機能を有する、半導体パッケージ用基板と呼ばれる、プラスチックやセラミックス等各種材料を使って構成される、サブストレートの端子との電気的接続方法として、ワイヤーボンディング方式やＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）方式、さらにはＦＣ（Ｆｒｉｐ Ｃｈｉｐ）方式などが知られているが、最近では、半導体パッケージの小型化に有利なＦＣ接続方式を用いた、ＢＧＡやＣＳＰの構造が盛んに提案されている。
【０００４】
しかしながら、上記工法では一つの半導体パッケージに対し半導体素子を一つしか収納できないため、半導体パッケージの小型化には自ずと限界がある。このため、一つの半導体パッケージの内部に複数個の半導体素子を積み重ねて収納することにより、実装密度を向上させる手法が提案されている。この際に、半導体素子は何らかの手法でリードフレームもしくはサブストレートと接続する必要があるが、現在の主流はワイヤーボンディングによるものであり、一部では最下層の半導体素子をサブストレートにフリップチップ方式で接続している。しかしながら、上記の技術では下層のワイヤーボンディングによる金線接合と上層の半導体素子の干渉を避けるため、積層される半導体素子は、より下層の半導体素子よりも小さいことが必要であり、実装上の制約が大きくなっている。
【０００５】
この問題を回避するため、半導体素子の形状が長方形の場合は積層方向を９０度変えながら積層していく方法や（図２参照）、２枚の半導体素子の間にスペーサーとしてシリコンチップをはさみこむ方法（図１参照）、厚みの厚いフィルム状の接着剤により半導体素子を積層する方式などが提案されている。しかし、パッケージサイズが大きくなる、プロセスが複雑になる、材料コストが上昇するなどの問題点を抱えている。
【０００６】
【発明が解決しようとする課題】
そこで、本発明者は種々検討の結果、光解像可能な感光性樹脂層を、半導体素子面上にスペーサーとして形成することにより、半導体素子積層時に半導体素子のサイズ的制約をなくすための技術を開発した。
【０００７】
【課題を解決するための手段】
即ち本発明は、半導体素子の集合体である半導体ウェハー表面全体に光解像可能な感光性樹脂層を、その上面に積層する半導体素子がワイヤーボンディングに干渉しない厚みだけ形成し、半導体素子の入出力端子周辺部をフォトリソグラフィーの手法で除去、個片化した後に半導体素子のワイヤーボンディングによる接続工程へと供し、更に上記スペーサー上に、半導体素子を積層することにより、金線ループの干渉を抑え、半導体素子の制約を受けることなく、半導体素子を積層し、一つの半導体パッケージに封入することを可能とするものである。
【０００８】
【発明の実施の形態】
本発明では、まず半導体ウェハー表面全面に、感光性樹脂層を形成する。感光性樹脂層の形成方法は、ドライフィルムのラミネート・印刷・スピンコート・カーテンコートと言った厚み制御が可能な既存の方法の中から、必要とする樹脂厚みに適した方法を選択することができる。
【０００９】
次に、上記感光性樹脂はフォトリソグラフの手法により、半導体素子のワイヤーボンディングパッド周辺部の樹脂がワイヤーボンディングの際に干渉しないよう除去される。 続いて、パターニングが完了した感光性樹脂層は加熱され、完全硬化することにより所定の特性を得る。この際のスペーサーの高さは、該半導体素子を外部端子もしくは他のチップと接続するために用いるワイヤーボンディングの金線ループ最後部よりも高い必要がある。好ましくは金線ループ最後部より５０μｍ以上厚いことが望ましい。
【００１０】
このようにして得られた、スペーサー付半導体ウェハーはダイシングマシンにより個片化され、サブストレートもしくはリードフレームのアイランド上に位置決めマウントされ、金線により、外部端子もしくは他のチップと電気的に接合される。
【００１１】
次に半導体素子上のスペーサーに、半導体素子を積層するが、スペーサーにより十分なスタンドオフが確保されているため、金線ループへの干渉を考慮することなく、半導体素子のサイズを選択し積層することができる。この際、半導体素子積層、固定用の材料としてはフィルム状、液状等の既存の材料を用いることができる。
【００１２】
更に、複数の半導体素子を積層する場合には、積層する半導体素子のすべてに感光性樹脂からなる、スペーサーを形成しておくことにより対応することが可能である。
【００１３】
【実施例】
以下、実施例により本発明を具体的に説明するが、本発明はこれによって何ら限定されるものではない。
【００１４】
（実施例１）
図３に示すように、半導体ウェハー表面２に、ノボラック系ポジ型感光性樹脂のＭＥＫ溶液を、スピンコーターにより１０８μｍ厚に塗工し、７０℃で２０分間乾燥した。乾燥した膜７を所定のマスクを用いて露光し、ワイヤーボンディングパッド周辺の樹脂を２．３８％ＴＭＡＨ水溶液により溶解除去した。この際、樹脂厚は減膜し、１０５μｍとなった。更にパターニングされた感光性樹脂は１５０℃で１時間加熱することにより、完全硬化した。
【００１５】
次に、その表面にパターニングされた感光性樹脂からなるスペーサーを有するウェハーは、ダイシングダイアタッチフィルム８をその裏面全面に貼り付けた後、ダイシングマシンにより個片化され、ＦＲ−４基板を母材とするプリント配線板５に位置決めマウントされた。さらに、金線１により外部端子と半導体素子が電気的に接続された。
【００１６】
加えて、もう一つの上記半導体素子をスペーサー上に位置決めマウントし金線により、外部端子と電気的に接続して、第２層の半導体素子を得た。また、同じ工程を繰り返すことにより第３層の半導体素子を得た。
【００１７】
最後に、上記プロセスにより、プリント配線板上に電気的に接続された半導体素子が３層積層された構造物は、エポキシ封止樹脂により封止され、半導体素子搭載面とは逆の面に、半田ボールを搭載し、ＢＧＡパッケージとした。このようにして得られた半導体素子は、実際にプリント配線板に実装され、半導体装置としての動作に支障のないことが確認された。
【００１８】
【発明の効果】
本発明によれば、複数の半導体素子が積層されてなる半導体パッケージを積層する半導体素子のサイズの制約なく、効率よく製造することが可能となる。
【図面の簡単な説明】
【図１】半導体素子と半導体素子の間にスペーサーを挿入する従来の半導体素子積層方法を示す概略図。
【図２】積層する半導体素子を９０°回転させて積層する従来の半導体素子積層方法を示す概略図。
【図３】本発明の半導体積層方法の一例を示す工程概略図。
【符号の説明】
１ 金線
２ 半導体素子
３ スペーサー（ポリイミドフィルムなど）
４ 積層、固定用樹脂
５ プリント配線板
６ 半田ボール
７ スペーサー用感光性樹脂
８ ダイシングダイアタッチフィルム[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention provides a technique for improving the productivity of a semiconductor package when a plurality of semiconductor elements are stacked and packaged.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and high-density mounting of electronic components have been progressing. Semiconductor packages used in these electronic devices have become smaller and have more pins, and mounting substrates for mounting electronic components including the semiconductor packages have also become smaller. Furthermore, in order to enhance the storage in electronic devices, a rigid-flex board, in which a rigid board and a flexible board are laminated and integrated to be bent, has been used as a mounting board.
[0003]
As the size of a semiconductor package has been reduced, the size of a conventional package using a lead frame has reached its limit. Therefore, recently, a BGA (Ball Grid) has been used in which a chip is mounted on a circuit board. A new area mounting type packaging method such as Array (Array) or CSP (Chip Scale Package) has been proposed. In these semiconductor packages, the electrical connection between the electrodes of the semiconductor chip and the terminals of the substrate made of various materials such as plastics and ceramics, which are called semiconductor package substrates and have the function of the lead frame of the conventional semiconductor package. As a typical connection method, a wire bonding method, a TAB (Tape Automated Bonding) method, an FC (Flip Chip) method, and the like are known. Recently, an FC connection method that is advantageous for miniaturization of a semiconductor package is used. , BGA and CSP structures have been actively proposed.
[0004]
However, since only one semiconductor element can be accommodated in one semiconductor package by the above-mentioned method, there is naturally a limit to miniaturization of the semiconductor package. For this reason, a method has been proposed in which a plurality of semiconductor elements are stacked and housed in one semiconductor package to improve the mounting density. At this time, it is necessary to connect the semiconductor element to the lead frame or substrate by some method, but the current mainstream is by wire bonding, and in some cases the lowermost semiconductor element is flip-chip mounted on the substrate. Connected. However, in order to avoid interference between the gold wire bonding by the lower wire bonding and the upper semiconductor element in the above technique, the stacked semiconductor elements need to be smaller than the lower semiconductor elements, and mounting restrictions are imposed. Is getting bigger.
[0005]
In order to avoid this problem, when the shape of the semiconductor element is rectangular, the stacking direction is changed while changing the stacking direction by 90 degrees (see FIG. 2), or a method in which a silicon chip is inserted as a spacer between two semiconductor elements. (See FIG. 1), a method of laminating semiconductor elements with a thick film adhesive has been proposed. However, there are problems such as an increase in package size, a complicated process, and an increase in material cost.
[0006]
[Problems to be solved by the invention]
The present inventor has conducted various studies and found that a photosensitive resin layer capable of resolving light is formed as a spacer on the surface of a semiconductor element, and a technique for eliminating the size limitation of the semiconductor element when stacking the semiconductor element. developed.
[0007]
[Means for Solving the Problems]
That is, in the present invention, a photosensitive resin layer that can be photo-resolved is formed on the entire surface of a semiconductor wafer, which is an aggregate of semiconductor elements, in such a thickness that the semiconductor elements stacked on the upper surface do not interfere with wire bonding. The peripheral part of the output terminal is removed by photolithography and separated into individual pieces.Then, the semiconductor element is subjected to a wire bonding connection process.Furthermore, by stacking the semiconductor element on the spacer, interference of the gold wire loop is suppressed. It is possible to stack semiconductor elements and enclose them in one semiconductor package without being restricted by the semiconductor elements.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
In the present invention, first, a photosensitive resin layer is formed on the entire surface of a semiconductor wafer. For the method of forming the photosensitive resin layer, a method suitable for the required resin thickness can be selected from existing methods that can control the thickness such as lamination, printing, spin coating, and curtain coating of a dry film. it can.
[0009]
Next, the photosensitive resin is removed by a photolithographic method so that the resin around the wire bonding pad of the semiconductor element does not interfere with the wire bonding. Subsequently, the patterned photosensitive resin layer is heated and completely cured to obtain predetermined characteristics. At this time, the height of the spacer needs to be higher than the last part of the gold wire loop of wire bonding used to connect the semiconductor element to an external terminal or another chip. It is desirable that the thickness be 50 μm or more than the last part of the gold wire loop.
[0010]
The semiconductor wafer with spacers thus obtained is singulated by a dicing machine, positioned and mounted on a substrate or an island of a lead frame, and electrically connected to external terminals or other chips by gold wires. You.
[0011]
Next, the semiconductor element is stacked on the spacer on the semiconductor element. Since a sufficient standoff is secured by the spacer, the size of the semiconductor element is selected and stacked without considering interference with the gold wire loop. be able to. At this time, as a material for laminating and fixing the semiconductor elements, an existing material such as a film or a liquid can be used.
[0012]
Further, when a plurality of semiconductor elements are stacked, it is possible to cope by forming a spacer made of a photosensitive resin on all of the stacked semiconductor elements.
[0013]
【Example】
Hereinafter, the present invention will be described specifically with reference to Examples, but the present invention is not limited thereto.
[0014]
(Example 1)
As shown in FIG. 3, a MEK solution of a novolak-based positive photosensitive resin was applied to the semiconductor wafer surface 2 to a thickness of 108 μm by a spin coater, and dried at 70 ° C. for 20 minutes. The dried film 7 was exposed using a predetermined mask, and the resin around the wire bonding pad was dissolved and removed with a 2.38% TMAH aqueous solution. At this time, the resin thickness was reduced to 105 μm. Further, the patterned photosensitive resin was completely cured by heating at 150 ° C. for 1 hour.
[0015]
Next, a wafer having spacers made of a photosensitive resin patterned on the surface thereof is diced by a dicing machine after the dicing die attach film 8 is attached to the entire back surface thereof, and the FR-4 substrate is used as a base material. And mounted on the printed wiring board 5. Further, the external terminal and the semiconductor element were electrically connected by the gold wire 1.
[0016]
In addition, another semiconductor element was positioned and mounted on the spacer and electrically connected to an external terminal by a gold wire to obtain a second-layer semiconductor element. Further, by repeating the same steps, a third-layer semiconductor element was obtained.
[0017]
Finally, a structure in which three layers of semiconductor elements electrically connected to the printed wiring board are laminated on the printed wiring board by the above process is sealed with epoxy sealing resin, and the surface opposite to the semiconductor element mounting surface is Solder balls were mounted to form a BGA package. The semiconductor element thus obtained was actually mounted on a printed wiring board, and it was confirmed that there was no hindrance to the operation as a semiconductor device.
[0018]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to manufacture efficiently without restricting the size of the semiconductor element which laminates the semiconductor package which laminated | stacked several semiconductor elements.
[Brief description of the drawings]
FIG. 1 is a schematic view showing a conventional semiconductor element stacking method in which a spacer is inserted between semiconductor elements.
FIG. 2 is a schematic view showing a conventional semiconductor element stacking method for stacking semiconductor elements by rotating the semiconductor elements by 90 °;
FIG. 3 is a schematic process diagram showing an example of the semiconductor lamination method of the present invention.
[Explanation of symbols]
1 Gold wire 2 Semiconductor element 3 Spacer (polyimide film etc.)
4 Resin for lamination and fixing 5 Printed wiring board 6 Solder ball 7 Photosensitive resin for spacer 8 Dicing die attach film

Claims (5)

半導体素子を複数個積み重ねて、一つの半導体パッケージに封入する構造を有し、少なくとも一つの半導体素子がワイヤーボンディングによる金線を介して、半導体素子間及び半導体パッケージ外部と接続されている半導体装置の製造方法であって、前記金線により接続された半導体素子の入出力端子及びワイヤーボンディング干渉区域を除いた半導体素子機能面全面に前記金線のループの最高点よりも、高さのあるスペーサーが形成されている事を特徴とする、半導体装置の製造方法。A semiconductor device having a structure in which a plurality of semiconductor elements are stacked and sealed in one semiconductor package, and at least one semiconductor element is connected between semiconductor elements and the outside of the semiconductor package through gold wires by wire bonding. In the manufacturing method, a spacer having a height higher than the highest point of the loop of the gold wire is provided on the entire surface of the semiconductor device functional surface excluding the input / output terminals of the semiconductor device connected by the gold wire and the wire bonding interference area. A method for manufacturing a semiconductor device, wherein the method is formed. スペーサーが感光性樹脂からなり、更に半導体素子が個片化される前のウェハーの状態でウェハー全面に前記感光性樹が配置された後、フォトリソグラフィーの手法により、前記感光性樹の不要部が除去される工程を含む請求項１記載の半導体装置の製造方法。The spacer is made of a photosensitive resin, and further, after the photosensitive tree is arranged on the entire surface of the wafer in a state of the wafer before the semiconductor elements are singulated, unnecessary portions of the photosensitive tree are removed by a photolithography technique. 2. The method for manufacturing a semiconductor device according to claim 1, comprising a step of removing. 裏面全面に積層貼り付け用の樹脂層を形成された半導体素子を、スペーサー上に貼り付けることにより、被積層半導体素子の金線ループに干渉するエリアに空隙を設ける工程を含む請求項１又は２記載の半導体装置の製造方法。3. A step of providing a gap in an area that interferes with a gold loop of a semiconductor element to be laminated by adhering a semiconductor element having a resin layer for lamination on the entire back surface on a spacer. The manufacturing method of the semiconductor device described in the above. スペーサーの上に、液状の半導体素子積層・固定用樹脂を供給し、その上から半導体素子をマウントすることにより、液状樹脂がワイヤーボンディングの根元付近に流れ込むと共に複数の金線の間を充填する工程を含む請求項１又は２記載の半導体素子の製造方法。A step of supplying a liquid semiconductor element laminating / fixing resin onto the spacer, and mounting the semiconductor element from above, so that the liquid resin flows near the root of the wire bonding and fills a gap between the plurality of gold wires. The method for manufacturing a semiconductor device according to claim 1, comprising: 請求項１〜４いずれかに記載された半導体装置の製造方法により製造された半導体装置。A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1.
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Publication number Priority date Publication date Assignee Title
EP1675179A1 (en) * 2004-12-27 2006-06-28 Shinko Electric Industries Co., Ltd. Stacked-type semiconductor device
JP2006253175A (en) * 2005-03-08 2006-09-21 Nec Corp Semiconductor package and manufacturing method thereof
WO2008152730A1 (en) * 2007-06-15 2008-12-18 Kabushiki Kaisha Nihon Micronics Laminated package and method for forming the same
CN109192669A (en) * 2018-08-14 2019-01-11 苏州德林泰精工科技有限公司 A kind of stacked chip package structure and processing technology based on resin gasket
CN109192720A (en) * 2018-08-14 2019-01-11 苏州德林泰精工科技有限公司 A kind of staircase stack chip-packaging structure and processing technology based on resin gasket

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JPH0888316A (en) * 1994-09-16 1996-04-02 Nec Corp Hybrid ic and its manufacture
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JP2003218316A (en) * 2002-01-10 2003-07-31 Ficta Technology Inc Multichip package structure and manufacturing method therefor
JP2004006670A (en) * 2002-02-25 2004-01-08 Seiko Epson Corp Semiconductor wafer with spacer and manufacturing method thereof, semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus

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Publication number Priority date Publication date Assignee Title
JPH0888316A (en) * 1994-09-16 1996-04-02 Nec Corp Hybrid ic and its manufacture
JP2000340741A (en) * 1999-05-26 2000-12-08 Sony Corp Manufacturing method and device of multi-chip module
JP2003218316A (en) * 2002-01-10 2003-07-31 Ficta Technology Inc Multichip package structure and manufacturing method therefor
JP2004006670A (en) * 2002-02-25 2004-01-08 Seiko Epson Corp Semiconductor wafer with spacer and manufacturing method thereof, semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1675179A1 (en) * 2004-12-27 2006-06-28 Shinko Electric Industries Co., Ltd. Stacked-type semiconductor device
JP2006253175A (en) * 2005-03-08 2006-09-21 Nec Corp Semiconductor package and manufacturing method thereof
WO2008152730A1 (en) * 2007-06-15 2008-12-18 Kabushiki Kaisha Nihon Micronics Laminated package and method for forming the same
JPWO2008152730A1 (en) * 2007-06-15 2010-08-26 株式会社日本マイクロニクス Stacked package and method for forming the same
CN109192669A (en) * 2018-08-14 2019-01-11 苏州德林泰精工科技有限公司 A kind of stacked chip package structure and processing technology based on resin gasket
CN109192720A (en) * 2018-08-14 2019-01-11 苏州德林泰精工科技有限公司 A kind of staircase stack chip-packaging structure and processing technology based on resin gasket

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