JP2006253175A - Semiconductor package and manufacturing method thereof - Google Patents

Semiconductor package and manufacturing method thereof Download PDF

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JP2006253175A
JP2006253175A JP2005063463A JP2005063463A JP2006253175A JP 2006253175 A JP2006253175 A JP 2006253175A JP 2005063463 A JP2005063463 A JP 2005063463A JP 2005063463 A JP2005063463 A JP 2005063463A JP 2006253175 A JP2006253175 A JP 2006253175A
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semiconductor package
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semiconductor
wafer
chips
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Koji Furusawa
宏治 古澤
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NEC Corp
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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  • Engineering & Computer Science (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package which can be formed so that distance between chips can be small and exact in the stacked type semiconductor package. <P>SOLUTION: The semiconductor package 10 is a stacked type semiconductor package in which a plurality of semiconductor chips 16, 20 are successively stacked on an interposer substrate 11 and the substrate is housed in a single package. A spacer 18 formed in a wafer process is disposed on the semiconductor chip 16, between the two adjacent semiconductor chips 16, 20. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体パッケージ及びその製造方法に関し、更に詳細には、複数の半導体チップを積層してパッケージとして構成した、スタック型の半導体パッケージ及びその製造方法に関する。   The present invention relates to a semiconductor package and a manufacturing method thereof, and more particularly to a stacked semiconductor package in which a plurality of semiconductor chips are stacked to form a package and a manufacturing method thereof.

電子機器の小型化に伴い、電子機器に搭載する半導体チップの高密度実装化が要求されている。その一環として、複数の半導体チップを積層してパッケージとして構成した、スタック型の半導体パッケージが注目されている。スタック型の半導体パッケージでは、一般に、大きなサイズの半導体チップから順にピラミッド状に積層され、回路面の周辺領域で、ワイヤボンディング等の配線が行われている。ところが、メモリチップなどの同じサイズの半導体チップを、下段の半導体チップ上にオーバーラップさせて積層する場合があり、このような場合には、上段の半導体チップによって、下段の半導体チップの回路面に接続されたワイヤが押し潰されないように、一定の間隔（クリアランス）を確保する必要がある。   Along with miniaturization of electronic devices, there is a demand for high-density mounting of semiconductor chips mounted on electronic devices. As part of this, a stack type semiconductor package in which a plurality of semiconductor chips are stacked to form a package attracts attention. In a stack type semiconductor package, generally, semiconductor chips are stacked in order from a large size semiconductor chip, and wiring such as wire bonding is performed in the peripheral region of the circuit surface. However, semiconductor chips of the same size, such as memory chips, may be stacked on top of the lower semiconductor chip in such a case. In such a case, the upper semiconductor chip causes the circuit surface of the lower semiconductor chip to be stacked. It is necessary to ensure a certain interval (clearance) so that the connected wires are not crushed.

図３、４に、同じサイズの半導体チップを積層して半導体パッケージとした、２つの従来例の半導体パッケージをそれぞれ示す。図３に示した半導体パッケージ３０では、下段の半導体チップ１６は、接着剤１５を介して、フェースアップでインタポーザ基板１１上に配設される。また、回路面１６ａの周辺領域で、金ワイヤ２２を用いたワイヤボンディングによって、インタポーザ基板１１に接続される。   3 and 4 show two conventional semiconductor packages in which semiconductor chips having the same size are stacked to form a semiconductor package. In the semiconductor package 30 shown in FIG. 3, the lower semiconductor chip 16 is disposed on the interposer substrate 11 face-up via the adhesive 15. Further, it is connected to the interposer substrate 11 by wire bonding using the gold wire 22 in the peripheral region of the circuit surface 16a.

下段の半導体チップの回路面１６ａの中央部では、接着剤３１を介して、半導体チップ１６よりも小さな平面形状を有するシリコン片から成るスペーサ３２が配設される。スペーサ３２上に更に、接着剤３３を介して、上段の半導体チップ２０が配設され、回路面２０ａの周辺領域で、金ワイヤ２２を用いたワイヤボンディングによって、インタポーザ基板１１に接続される。半導体パッケージ３０では、スペーサ３２及び接着剤３１，３３の厚みによって、上段及び下段の半導体チップ間の間隔を確保している。   In the central part of the circuit surface 16 a of the lower semiconductor chip, a spacer 32 made of a silicon piece having a planar shape smaller than that of the semiconductor chip 16 is disposed via an adhesive 31. Further, an upper semiconductor chip 20 is disposed on the spacer 32 via an adhesive 33, and is connected to the interposer substrate 11 by wire bonding using a gold wire 22 in the peripheral region of the circuit surface 20a. In the semiconductor package 30, the space between the upper and lower semiconductor chips is secured by the thickness of the spacer 32 and the adhesives 31 and 33.

図４に示した半導体パッケージ４０では、下段の半導体チップ１６は、図３の半導体パッケージ３０と同様の構成を有している。下段の半導体チップの回路面１６ａの中央部で、樹脂層４１を介して、上段の半導体チップ２０が配設される。樹脂層４１は、例えば、下段の半導体チップ１６上に塗布された後、上段の半導体チップ２０を積層する際の押し付け圧力によって、その厚さが設定される。上段の半導体チップ２０は、回路面２０ａの周辺領域で、金ワイヤ２２を用いたワイヤボンディングによって、インタポーザ基板１１に接続されている。半導体パッケージ４０では、樹脂層４１の厚みによって、上段及び下段の半導体チップ間の間隔を確保している。   In the semiconductor package 40 shown in FIG. 4, the lower semiconductor chip 16 has the same configuration as the semiconductor package 30 shown in FIG. The upper semiconductor chip 20 is disposed through the resin layer 41 at the center of the circuit surface 16a of the lower semiconductor chip. For example, the thickness of the resin layer 41 is set by a pressing pressure when the upper semiconductor chip 20 is stacked after being applied onto the lower semiconductor chip 16. The upper semiconductor chip 20 is connected to the interposer substrate 11 by wire bonding using a gold wire 22 in the peripheral region of the circuit surface 20a. In the semiconductor package 40, the space between the upper and lower semiconductor chips is secured by the thickness of the resin layer 41.

図３、４に示した半導体パッケージ３０，４０については、例えば特許文献１に記載されている。
特開２００４−２５３６９３号公報（図６，７） The semiconductor packages 30 and 40 shown in FIGS. 3 and 4 are described in Patent Document 1, for example.
Japanese Unexamined Patent Publication No. 2004-253893 (FIGS. 6 and 7)

ところで、図３の半導体パッケージ３０では、スペーサ３２を構成するシリコン片の割れを防止するため、スペーサ３２の厚みを少なくとも１００μｍ程度に設定する必要がある。この場合、スペーサ３２の上下に塗布される接着剤３１，３３の厚みは、何れも２５μｍ程度であるため、半導体チップ間の間隔は１５０μｍ程度以上となる。この間隔は、近年の半導体パッケージに要求される厚みの観点から、小さくすることが望まれる。   By the way, in the semiconductor package 30 of FIG. 3, it is necessary to set the thickness of the spacer 32 to at least about 100 μm in order to prevent the silicon pieces constituting the spacer 32 from cracking. In this case, since the thicknesses of the adhesives 31 and 33 applied to the upper and lower sides of the spacer 32 are both about 25 μm, the interval between the semiconductor chips is about 150 μm or more. This interval is desired to be reduced from the viewpoint of the thickness required for recent semiconductor packages.

一方、図４の半導体パッケージ４０では、樹脂層４１の粘度や塗布量、硬化による収縮など、樹脂層４１の厚みに影響を与えるパラメータが多く、誤差が生じ易い．このため、この半導体パッケージ４０では、厚み誤差を考慮して、樹脂層４１を厚めに形成する必要があり、半導体チップ間の間隔を十分に小さくすることが出来なかった。   On the other hand, in the semiconductor package 40 of FIG. 4, there are many parameters that affect the thickness of the resin layer 41, such as the viscosity of the resin layer 41, the coating amount, and shrinkage due to curing, and errors are likely to occur. For this reason, in this semiconductor package 40, it is necessary to form the resin layer 41 thick in consideration of the thickness error, and the interval between the semiconductor chips cannot be sufficiently reduced.

本発明は、上記に鑑み、スタック型の半導体パッケージにおいて、チップ間の間隔を小さく且つ正確に形成できる半導体パッケージ及びその製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a semiconductor package and a method of manufacturing the same that can be formed with a small and accurate gap between chips in a stacked semiconductor package.

上記目的を達成するために、本発明に係る半導体パッケージは、インタポーザ基板上に複数のチップを順次に積層し、単一のパッケージに収容して成るスタック型の半導体パッケージにおいて、
隣接する２つのチップの間には、該２つのチップの内の一方のチップに、ウエハプロセスで形成されたスペーサが配設されることを特徴とする。 In order to achieve the above object, a semiconductor package according to the present invention is a stacked semiconductor package in which a plurality of chips are sequentially stacked on an interposer substrate and housed in a single package.
Between two adjacent chips, one of the two chips is provided with a spacer formed by a wafer process.

また、本発明に係る半導体パッケージの製造方法は、ウエハの回路面に回路を形成する工程と、前記ウエハの回路面又は裏面に絶縁層を形成する工程と、前記絶縁層を選択的に除去してスペーサを形成する工程と、前記ウエハをチップに切断することによって、前記スペーサを備えるチップを得る工程とをこの順に有することを特徴とする。   The method of manufacturing a semiconductor package according to the present invention includes a step of forming a circuit on a circuit surface of a wafer, a step of forming an insulating layer on the circuit surface or the back surface of the wafer, and selectively removing the insulating layer. Forming a spacer, and cutting the wafer into chips to obtain a chip having the spacer in this order.

本発明の半導体パッケージによれば、スペーサがウエハプロセスで形成されることによって、スペーサを小さく且つ正確な厚みに形成することが出来る。これによって、チップ間の間隔を、小さく且つ正確に形成することが出来る。   According to the semiconductor package of the present invention, the spacer can be formed in a small and accurate thickness by forming the spacer by a wafer process. As a result, the distance between the chips can be formed small and accurately.

本発明の半導体パッケージでは、前記一方のチップをフェースアップで積層し、前記スペーサを、該一方のチップの回路面に形成することが出来る。一方のチップに接続されたワイヤが、上段のチップによって押し潰されることを回避しつつ、チップ間の間隔を小さくすることが出来る。   In the semiconductor package of the present invention, the one chip can be stacked face up, and the spacer can be formed on the circuit surface of the one chip. The distance between the chips can be reduced while avoiding the wires connected to one chip being crushed by the upper chip.

本発明の半導体パッケージでは、好適には、前記スペーサ及び該スペーサと前記２つのチップを接着する接着層の合計の厚みが、１００μｍ以上で１２０μｍ未満である。１００μｍ以上で、下段のチップに接続されたワイヤが、上段のチップによって押し潰されることを回避できる。１２０μｍ未満で、半導体パッケージの厚みを十分に小さくすることが出来る。   In the semiconductor package of the present invention, preferably, the total thickness of the spacer and the adhesive layer that bonds the spacer and the two chips is 100 μm or more and less than 120 μm. The wire connected to the lower chip at 100 μm or more can be prevented from being crushed by the upper chip. When the thickness is less than 120 μm, the thickness of the semiconductor package can be sufficiently reduced.

本発明の半導体パッケージの製造方法によれば、複数のチップに配設されるスペーサをウエハプロセスで一括に形成するので、スペーサの形成に必要なコストを低減することが出来る。   According to the semiconductor package manufacturing method of the present invention, the spacers disposed on the plurality of chips are collectively formed by the wafer process, so that the cost required for forming the spacers can be reduced.

本発明の半導体パッケージの製造方法の好適な実施態様では、前記ウエハの回路面に絶縁層を形成する工程に後続して、前記ウエハの裏面を研削する工程を有する。この場合、ウエハが絶縁層で補強されることによって、ウエハの割れを抑制することが出来る。   In a preferred embodiment of the method for manufacturing a semiconductor package of the present invention, the method further comprises a step of grinding the back surface of the wafer subsequent to the step of forming an insulating layer on the circuit surface of the wafer. In this case, cracking of the wafer can be suppressed by reinforcing the wafer with the insulating layer.

以下に、図面を参照し、本発明に係る実施形態に基づいて本発明を更に詳細に説明する。図１は、本発明の実施形態に係る半導体パッケージの構成を示す断面図である。半導体パッケージ１０は、スタック型のＣＳＰ（Chip Size Package）であって、内部に図示しない配線が形成されたインタポーザ基板１１を備える。インタポーザ基板１１の上面及び底面には、インタポーザ基板１１内部の配線に接続された電極パッド１２，１３がそれぞれ形成されている。インタポーザ基板１１の底面の電極パッド１３には半田ボール１４が配設され、半導体パッケージ１０は、半田ボール１４を介してマザーボード等に接続される。   Hereinafter, the present invention will be described in more detail based on embodiments according to the present invention with reference to the drawings. FIG. 1 is a cross-sectional view showing a configuration of a semiconductor package according to an embodiment of the present invention. The semiconductor package 10 is a stack type CSP (Chip Size Package), and includes an interposer substrate 11 in which wiring (not shown) is formed. Electrode pads 12 and 13 connected to wiring inside the interposer substrate 11 are formed on the top and bottom surfaces of the interposer substrate 11, respectively. Solder balls 14 are disposed on the electrode pads 13 on the bottom surface of the interposer substrate 11, and the semiconductor package 10 is connected to a mother board or the like via the solder balls 14.

インタポーザ基板１１上には、２５μｍ程度の厚みを有する接着剤１５を介して、１００μｍの厚みを有する第１の半導体チップ１６が、フェースアップで配設されている。第１の半導体チップ１６は、ＤＲＡＭとして構成され、回路面１６ａの周辺部に配列された複数の電極パッド１７と、回路面１６ａ上であって、これら複数の電極パッド１７の内側に形成されたスペーサ１８とを備える。   On the interposer substrate 11, a first semiconductor chip 16 having a thickness of 100 μm is arranged face up through an adhesive 15 having a thickness of about 25 μm. The first semiconductor chip 16 is configured as a DRAM, and is formed on a plurality of electrode pads 17 arranged in the peripheral portion of the circuit surface 16 a and on the circuit surface 16 a and inside the plurality of electrode pads 17. Spacer 18.

スペーサ１８は、ウエハプロセスで回路形成工程に後続して形成され、８０μｍの厚みを有するエポキシ樹脂から成る。第１の半導体チップの電極パッド１７と、インタポーザ基板の電極パッド１２との間は、ワイヤボンディングによって、金ワイヤ２２で接続されている。   The spacer 18 is formed subsequent to the circuit formation step in the wafer process, and is made of an epoxy resin having a thickness of 80 μm. The electrode pad 17 of the first semiconductor chip and the electrode pad 12 of the interposer substrate are connected by a gold wire 22 by wire bonding.

スペーサ１８上には、２５μｍ程度の厚みを有する接着剤１９を介して、第２の半導体チップ２０がフェースアップで配設されている。第２の半導体チップ２０は、ＤＲＡＭとして構成され、回路面２０ａの周辺部に配列された複数の電極パッド２１を備える。第２の半導体チップ２０は、第１の半導体チップ１６と同じ厚み及び平面形状を有し、垂直方向に見て第１の半導体チップ１６と重なるように配設されている。第２の半導体チップの電極パッド２１と、インタポーザ基板の電極パッド１２との間は、ワイヤボンディングによって、金ワイヤ２２で接続されている。   A second semiconductor chip 20 is disposed face up on the spacer 18 via an adhesive 19 having a thickness of about 25 μm. The second semiconductor chip 20 is configured as a DRAM and includes a plurality of electrode pads 21 arranged in the peripheral portion of the circuit surface 20a. The second semiconductor chip 20 has the same thickness and planar shape as the first semiconductor chip 16 and is disposed so as to overlap the first semiconductor chip 16 when viewed in the vertical direction. The electrode pad 21 of the second semiconductor chip and the electrode pad 12 of the interposer substrate are connected by a gold wire 22 by wire bonding.

第２の半導体チップ２０は、第１の半導体チップ１６上にスペーサ１８及び接着剤１９を介して配設されるため、半導体チップ間の間隔は１０５μｍ程度である。インタポーザ基板１１上の接着剤１５、第１の半導体チップ１６、スペーサ１８、接着剤１９、第２の半導体チップ２０、及び金ワイヤ２２の全体を封止するように樹脂２３が形成されている。   Since the second semiconductor chip 20 is disposed on the first semiconductor chip 16 via the spacer 18 and the adhesive 19, the interval between the semiconductor chips is about 105 μm. A resin 23 is formed so as to seal the entire adhesive 15, first semiconductor chip 16, spacer 18, adhesive 19, second semiconductor chip 20, and gold wire 22 on the interposer substrate 11.

本実施形態の半導体パッケージによれば、スペーサ１８がウエハプロセスで形成されるため、小さく且つ正確な厚みを有する。第１の半導体チップ１６と第２の半導体チップ２０との間隔が、上記スペーサ１８と厚み誤差が小さな接着剤１９とで構成されるので、第１の半導体チップ１６に接続された金ワイヤ２２が、第２の半導体チップ２０によって押し潰されることを回避しつつ、半導体チップ間の間隔を小さくすることが出来る。   According to the semiconductor package of this embodiment, since the spacer 18 is formed by a wafer process, it has a small and accurate thickness. Since the distance between the first semiconductor chip 16 and the second semiconductor chip 20 is constituted by the spacer 18 and the adhesive 19 having a small thickness error, the gold wire 22 connected to the first semiconductor chip 16 is The interval between the semiconductor chips can be reduced while avoiding being crushed by the second semiconductor chip 20.

なお、第１の半導体チップの回路面１６ａに形成されたスペーサ１８に代えて、第２の半導体チップの裏面２０ｂにスペーサが形成されても構わない。また、本実施形態では、２つの半導体チップを積層した半導体パッケージについて示したが、３つ以上の半導体チップを積層する半導体パッケージに本実施形態の構成を適用することによって、半導体パッケージの厚みを効果的に小さく出来る。   In place of the spacer 18 formed on the circuit surface 16a of the first semiconductor chip, a spacer may be formed on the back surface 20b of the second semiconductor chip. Further, in the present embodiment, a semiconductor package in which two semiconductor chips are stacked is shown, but the thickness of the semiconductor package is effectively obtained by applying the configuration of the present embodiment to a semiconductor package in which three or more semiconductor chips are stacked. Can be made small.

更に、３つ以上の半導体チップを積層する場合に、１段目の半導体チップをフェースダウンで配設し、インタポーザ基板に対してフリップチップ接続を行っても構わない。この場合、２段目の半導体チップの裏面を、１段目の半導体チップの裏面に対向させて配設し、２段目以降の半導体チップについて、本実施形態の半導体パッケージと同様の構成を採用することが出来る。   Further, when three or more semiconductor chips are stacked, the first-stage semiconductor chip may be disposed face down, and the flip chip connection may be made to the interposer substrate. In this case, the back surface of the second-stage semiconductor chip is disposed to face the back surface of the first-stage semiconductor chip, and the second and subsequent semiconductor chips have the same configuration as the semiconductor package of the present embodiment. I can do it.

図２（ａ）〜（ｃ）は、図１に示した半導体パッケージ１０を製造する製造方法について、各製造段階をそれぞれ順次に示す断面図である。先ず、ウエハ２４の主面上に図示しない種々の半導体素子及び回路を形成した後、これら半導体素子及び回路が形成されたウエハの回路面２４ａに電極パッド１７を形成する。次いで、図２（ａ）に示すように、スピンコート法によって、ウエハの回路面２４ａの全面に液状のエポキシ樹脂１８ａを塗布し、これを硬化させる。エポキシ樹脂１８ａを塗布する際には、硬化した後に、エポキシ樹脂１８ａの厚みが８０μｍになるように厚みを設定する。引き続き、ウエハ２４の厚みが１００μｍになるように、ウエハの裏面２４ｂを研削する。   2A to 2C are cross-sectional views sequentially showing each manufacturing stage in the manufacturing method for manufacturing the semiconductor package 10 shown in FIG. First, various semiconductor elements and circuits (not shown) are formed on the main surface of the wafer 24, and then electrode pads 17 are formed on the circuit surface 24a of the wafer on which these semiconductor elements and circuits are formed. Next, as shown in FIG. 2A, a liquid epoxy resin 18a is applied to the entire circuit surface 24a of the wafer by spin coating, and is cured. When applying the epoxy resin 18a, the thickness is set so that the thickness of the epoxy resin 18a is 80 μm after curing. Subsequently, the back surface 24b of the wafer is ground so that the thickness of the wafer 24 becomes 100 μm.

次いで、フォトリソグラフィ技術を用いて、電極パッド１７、ダイシング予定部位２５、及びそれらの近傍の回路面２４ａが露出するようにエポキシ樹脂１８ａを除去することによって、スペーサ１８を形成する。本実施形態では、ＷＬＣＳＰ（Wafer Level Chip Size Package）の再配線技術を用いて、スペーサ１８の形成を行う。引き続き、図２（ｃ）に示すように、ダイシングによりウエハ２４を切断し、半導体チップ１６に切り分ける。   Next, the spacer 18 is formed by removing the epoxy resin 18a using the photolithography technique so that the electrode pad 17, the dicing scheduled portion 25, and the circuit surface 24a in the vicinity thereof are exposed. In the present embodiment, the spacer 18 is formed using a rewiring technique of WLCSP (Wafer Level Chip Size Package). Subsequently, as shown in FIG. 2C, the wafer 24 is cut by dicing and cut into semiconductor chips 16.

更に、インタポーザ基板１１上に接着剤１５を塗布し、フェースアップで第１の半導体チップ１６を配設する。引き続き、ワイヤボンディングにより、第１の半導体チップの電極パッド１７と、インタポーザ基板の電極パッド１２との間の接続を行う。次いで、スペーサ１８上に接着剤１９を塗布し、フェースアップで第２の半導体チップ２０を配設する。引き続き、ワイヤボンディングにより、第２の半導体チップの電極パッド２１と、インタポーザ基板の電極パッド１２との間の接続を行う。   Further, an adhesive 15 is applied on the interposer substrate 11, and the first semiconductor chip 16 is disposed face up. Subsequently, connection between the electrode pad 17 of the first semiconductor chip and the electrode pad 12 of the interposer substrate is performed by wire bonding. Next, an adhesive 19 is applied on the spacer 18 and the second semiconductor chip 20 is disposed face up. Subsequently, the connection between the electrode pad 21 of the second semiconductor chip and the electrode pad 12 of the interposer substrate is performed by wire bonding.

引き続き、インタポーザ基板１１上の接着剤１５、第１の半導体チップ１６、スペーサ１８、接着剤１９、第２の半導体チップ２０、及び金ワイヤ２２の全体を封止する樹脂２３を形成する。更に、インタポーザ基板１１の裏面に半田ボール１４を形成することによって、図１に示した半導体パッケージ１０を完成することが出来る。   Subsequently, a resin 23 that seals the adhesive 15, the first semiconductor chip 16, the spacer 18, the adhesive 19, the second semiconductor chip 20, and the gold wire 22 on the interposer substrate 11 is formed. Furthermore, by forming solder balls 14 on the back surface of the interposer substrate 11, the semiconductor package 10 shown in FIG. 1 can be completed.

本実施形態に係る半導体パッケージの製造方法によれば、複数の第１の半導体チップ１６に配設されるスペーサ１８をウエハプロセスで一括に形成するので、スペーサ１８を低コストで製造することが出来る。また、ウエハプロセスの技術を用いてスペーサ１８を形成するので、所望で且つ正確な厚みを有するスペーサ１８を形成することが出来る。更に、ウエハの回路面２４ａにエポキシ樹脂１８ａが塗布され、硬化した後に、ウエハの裏面２４ｂの研削を行うので、ウエハ２４がエポキシ樹脂１８ａで補強され、ウエハ２４の割れを抑制することが出来る。   According to the method for manufacturing a semiconductor package according to the present embodiment, the spacers 18 disposed on the plurality of first semiconductor chips 16 are collectively formed by a wafer process, so that the spacers 18 can be manufactured at low cost. . Further, since the spacer 18 is formed by using a wafer process technique, the spacer 18 having a desired and accurate thickness can be formed. Furthermore, since the epoxy resin 18a is applied to the circuit surface 24a of the wafer and cured, the back surface 24b of the wafer is ground, so that the wafer 24 is reinforced with the epoxy resin 18a and cracking of the wafer 24 can be suppressed.

なお、スペーサ１８は、エポキシ樹脂に限定されず、様々な絶縁材料で構成することが出来る。また、スピンコート法以外にも、各種の塗布法やＣＶＤ法など、ウエハプロセスでの様々な絶縁膜の形成方法を用いて絶縁材料を形成することによって、スペーサ１８を小さく且つ正確な厚みに形成できる。   The spacer 18 is not limited to an epoxy resin, and can be made of various insulating materials. In addition to the spin coating method, the spacer 18 is formed in a small and accurate thickness by forming an insulating material using various insulating film forming methods in the wafer process such as various coating methods and CVD methods. it can.

以上、本発明をその好適な実施形態に基づいて説明したが、本発明に係る半導体パッケージ及びその製造方法は、上記実施形態の構成にのみ限定されるものではなく、上記実施形態の構成から種々の修正及び変更を施した半導体パッケージ及びその製造方法も、本発明の範囲に含まれる。   As described above, the present invention has been described based on the preferred embodiment. However, the semiconductor package and the manufacturing method thereof according to the present invention are not limited to the configuration of the above-described embodiment, and various modifications can be made from the configuration of the above-described embodiment. The semiconductor package and the manufacturing method thereof subjected to the above correction and change are also included in the scope of the present invention.

本発明の実施形態に係る半導体パッケージの構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor package which concerns on embodiment of this invention. 図２（ａ）〜（ｃ）は、図１の半導体パッケージを製造する各製造段階をそれぞれ順次に示す断面図である。2A to 2C are cross-sectional views sequentially showing respective manufacturing steps for manufacturing the semiconductor package of FIG. 一従来例の半導体パッケージの構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor package of one prior art example. 一従来例の半導体パッケージの構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor package of one prior art example.

符号の説明Explanation of symbols

１０：半導体パッケージ
１１：インタポーザ基板
１２：電極パッド
１３：電極パッド
１４：半田ボール
１５：接着剤
１６：第１の半導体チップ
１６ａ：（第１の半導体チップの）回路面
１６ｂ：（第１の半導体チップの）裏面
１７：電極パッド
１８：スペーサ
１８ａ：エポキシ樹脂
１９：接着剤
２０：第２の半導体チップ
２０ａ：（第２の半導体チップの）回路面
２０ｂ：（第２の半導体チップの）裏面
２１：電極パッド
２２：金ワイヤ
２３：樹脂
２４：ウエハ
２４ａ：（ウエハの）回路面
２４ｂ：（ウエハの）裏面
２５：ダイシング予定部位 10: semiconductor package 11: interposer substrate 12: electrode pad 13: electrode pad 14: solder ball 15: adhesive 16: first semiconductor chip 16a: circuit surface 16b (of the first semiconductor chip): (first semiconductor) Back surface 17: Electrode pad 18: Spacer 18a: Epoxy resin 19: Adhesive 20: Second semiconductor chip 20a: Circuit surface 20b (of the second semiconductor chip): Back surface 21 (of the second semiconductor chip) : Electrode pad 22: Gold wire 23: Resin 24: Wafer 24a: (Wafer) circuit surface 24b: (Wafer) back surface 25: Dicing scheduled part

Claims (5)

インタポーザ基板上に複数のチップを順次に積層し、単一のパッケージに収容して成るスタック型の半導体パッケージにおいて、
隣接する２つのチップの間には、該２つのチップの内の一方のチップに、ウエハプロセスで形成されたスペーサが配設されることを特徴とする半導体パッケージ。 In a stack type semiconductor package in which a plurality of chips are sequentially stacked on an interposer substrate and accommodated in a single package,
A semiconductor package characterized in that a spacer formed by a wafer process is disposed between two adjacent chips on one of the two chips. 前記一方のチップがフェースアップで積層され、前記スペーサは、該一方のチップの回路面に形成される、請求項１に記載の半導体パッケージ。   The semiconductor package according to claim 1, wherein the one chip is stacked face up, and the spacer is formed on a circuit surface of the one chip. 前記スペーサ及び該スペーサと前記２つのチップを接着する接着層の合計の厚みが、１００μｍ以上で１２０μｍ未満である、請求項２に記載の半導体パッケージ。   3. The semiconductor package according to claim 2, wherein a total thickness of the spacer and an adhesive layer that bonds the spacer and the two chips is 100 μm or more and less than 120 μm. ウエハの回路面に回路を形成する工程と、前記ウエハの回路面又は裏面に絶縁層を形成する工程と、前記絶縁層を選択的に除去してスペーサを形成する工程と、前記ウエハをチップに切断することによって、前記スペーサを備えるチップを得る工程とをこの順に有することを特徴とする半導体パッケージの製造方法。   Forming a circuit on a circuit surface of the wafer, forming an insulating layer on the circuit surface or the back surface of the wafer, forming a spacer by selectively removing the insulating layer, and forming the wafer on a chip. And a step of obtaining a chip provided with the spacer by cutting, in this order. 前記ウエハの回路面に絶縁層を形成する工程に後続して、前記ウエハの裏面を研削する工程を有する、請求項４に記載の半導体パッケージの製造方法。   The method of manufacturing a semiconductor package according to claim 4, further comprising a step of grinding a back surface of the wafer subsequent to the step of forming an insulating layer on the circuit surface of the wafer.
JP2005063463A 2005-03-08 2005-03-08 Semiconductor package and manufacturing method thereof Pending JP2006253175A (en)

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Cited By (1)

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JPH0555278A (en) * 1991-08-23 1993-03-05 Sony Corp Semiconductor device
JP2004006670A (en) * 2002-02-25 2004-01-08 Seiko Epson Corp Semiconductor wafer with spacer and manufacturing method thereof, semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
JP2004158747A (en) * 2002-11-08 2004-06-03 Sumitomo Bakelite Co Ltd Manufacture of semiconductor device
JP2004221555A (en) * 2002-12-27 2004-08-05 Sumitomo Bakelite Co Ltd Semiconductor element with film pasted, semiconductor device, and manufacturing method therefor

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JPH0555278A (en) * 1991-08-23 1993-03-05 Sony Corp Semiconductor device
JP2004006670A (en) * 2002-02-25 2004-01-08 Seiko Epson Corp Semiconductor wafer with spacer and manufacturing method thereof, semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
JP2004158747A (en) * 2002-11-08 2004-06-03 Sumitomo Bakelite Co Ltd Manufacture of semiconductor device
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8253250B2 (en) 2007-03-30 2012-08-28 Nec Corporation Interconnection structure of electronic device having multilayer interconnections structure with electrically conductive layers

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