JP2009049118A - Semiconductor element, and semiconductor package using the same - Google Patents

Semiconductor element, and semiconductor package using the same Download PDF

Info

Publication number
JP2009049118A
JP2009049118A JP2007212712A JP2007212712A JP2009049118A JP 2009049118 A JP2009049118 A JP 2009049118A JP 2007212712 A JP2007212712 A JP 2007212712A JP 2007212712 A JP2007212712 A JP 2007212712A JP 2009049118 A JP2009049118 A JP 2009049118A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor element
adhesive layer
insulating
insulating adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007212712A
Other languages
Japanese (ja)
Other versions
JP4496241B2 (en
Inventor
Ryoji Matsushima
良二 松嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2007212712A priority Critical patent/JP4496241B2/en
Priority to US12/191,574 priority patent/US7911045B2/en
Publication of JP2009049118A publication Critical patent/JP2009049118A/en
Application granted granted Critical
Publication of JP4496241B2 publication Critical patent/JP4496241B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
    • H01L2224/48479—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element which enables lowering the height of a connection member due to a metal wire or the like, when laminating a plurality of the semiconductor elements to package them. <P>SOLUTION: This semiconductor element 1 is equipped with an electrode pad 3 disposed on the surface of a semiconductor element body 2, an insulating protective film 12 covering the surface of the semiconductor element body 2 with the exception of its peripheral area while exposing the electrode pad 3, and an insulating adhesive layer 13 formed so as to at least cover the back and side faces of the semiconductor element body 2, and corner parts between the surface and the side faces. A plurality of the semiconductor elements 1 are laminated on a circuit base material, and are bonded through the insulating adhesive layer 13. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は半導体素子とそれを用いた半導体パッケージに関する。   The present invention relates to a semiconductor device and a semiconductor package using the same.

半導体装置の小型化や高密度実装化等を実現するために、１つのパッケージ内に複数の半導体素子を積層して封止した積層型の半導体パッケージが実用化されている。積層型の半導体パッケージにおいて、複数の半導体素子は配線基板やリードフレーム等の回路基材上に接着剤層を介して順に積層される。各半導体素子の電極パッドは、回路基材の接続パッドと金属ワイヤを介して電気的に接続される。このような積層体を樹脂封止することによって、積層型の半導体パッケージが構成される。   In order to realize miniaturization and high density mounting of a semiconductor device, a stacked semiconductor package in which a plurality of semiconductor elements are stacked and sealed in one package has been put into practical use. In a stacked semiconductor package, a plurality of semiconductor elements are sequentially stacked on a circuit substrate such as a wiring board or a lead frame via an adhesive layer. The electrode pads of each semiconductor element are electrically connected to the connection pads of the circuit base material via metal wires. By stacking such a stacked body with a resin, a stacked semiconductor package is formed.

半導体素子の表面は絶縁保護膜で覆われているものの、表面の外周部分には絶縁保護膜が形成されていないため、表面と側面との間の角部には半導体素子を構成する半導体基板や配線層等が露出している。このような半導体素子にワイヤボンディングを適用した場合、金属ワイヤは半導体素子の角部と接触しないようなループ高さを維持しつつワイヤリングする必要がある。積層型の半導体パッケージにおいては、複数の半導体素子の積層厚、ひいてはパッケージ厚さの削減が求められているものの、最上層の半導体素子に接続された金属ワイヤのループ高さがパッケージ厚さを厚くする要因となっている。   Although the surface of the semiconductor element is covered with an insulating protective film, since the insulating protective film is not formed on the outer peripheral portion of the surface, the semiconductor substrate constituting the semiconductor element is formed at the corner between the surface and the side surface. The wiring layer is exposed. When wire bonding is applied to such a semiconductor element, it is necessary to wire the metal wire while maintaining a loop height that does not contact the corner of the semiconductor element. In a stacked type semiconductor package, the stacking thickness of a plurality of semiconductor elements, and consequently the reduction of the package thickness, is required, but the loop height of the metal wire connected to the uppermost semiconductor element increases the package thickness. Is a factor.

すなわち、最上層の半導体素子に接続される金属ワイヤは、必然的に複数の半導体素子の積層厚を超えた部分を通過するように配置される。このようなワイヤ形状を有する複数の半導体素子の積層体を樹脂封止する場合、封止樹脂の厚さは最上層の半導体素子に接続されたワイヤの形状分だけ厚くする必要がある。これがパッケージ厚さを厚くする要因となっている。さらに、ループ高さを保ってワイヤリングされた金属ワイヤは、樹脂封止時にワイヤ流れを起こしやすいという問題を有している。ワイヤ流れは隣接する異電位ワイヤ間の接触によるショート不良等を引起す要因となる。   That is, the metal wire connected to the uppermost semiconductor element is inevitably disposed so as to pass through a portion exceeding the stack thickness of the plurality of semiconductor elements. In the case of resin-sealing a stacked body of a plurality of semiconductor elements having such a wire shape, the thickness of the sealing resin needs to be increased by the shape of the wire connected to the uppermost semiconductor element. This is a factor for increasing the package thickness. Furthermore, the metal wire wired while maintaining the loop height has a problem that it tends to cause a wire flow during resin sealing. The wire flow causes a short circuit failure due to contact between adjacent different potential wires.

特許文献１には半導体素子の角部と金属ワイヤとの接触を防止するために、半導体素子の電極形成面の一部と側面を覆うように樹脂ブロックを配置することが記載されている。樹脂ブロックは基板上に形成されるため、半導体素子を多段に積層する場合には金属ワイヤの半導体素子との接触防止効果を得ることができない。また、特許文献２にはフリップチップ実装用の半導体素子の側面や裏面（バンプ形成面とは反対側の面）に保護樹脂層を形成することが記載されている。ここではフリップチップ実装用の半導体素子を対象としているため、半導体素子を多段に積層することは考慮されていない。
特開２０００−３０７０３６号公報 特開２００１−２４４２８１号公報 Patent Document 1 describes that a resin block is disposed so as to cover a part and side surfaces of an electrode formation surface of a semiconductor element in order to prevent contact between a corner portion of the semiconductor element and a metal wire. Since the resin block is formed on the substrate, the effect of preventing the contact of the metal wire with the semiconductor element cannot be obtained when the semiconductor elements are stacked in multiple stages. Patent Document 2 describes that a protective resin layer is formed on the side surface and back surface (surface opposite to the bump forming surface) of a semiconductor element for flip chip mounting. Here, since semiconductor devices for flip chip mounting are targeted, it is not considered to stack semiconductor devices in multiple stages.
JP 2000-307036 A JP 2001-244281 A

本発明の目的は、複数の半導体素子を積層するにあたって、金属ワイヤ等による接続部材の高さを低くすることを可能にした半導体素子と、そのような半導体素子を用いることによって、封止材料の厚さひいてはパッケージ厚さを薄くすることを可能にした半導体パッケージを提供することにある。   An object of the present invention is to provide a semiconductor element that can reduce the height of a connecting member made of a metal wire or the like when laminating a plurality of semiconductor elements, and a sealing material by using such a semiconductor element. It is an object of the present invention to provide a semiconductor package that can reduce the thickness and thus the package thickness.

本発明の態様に係る半導体素子は、半導体素子本体と、前記半導体素子本体の表面に配置された電極パッドと、前記電極パッドを露出させつつ、前記表面をその外周領域を除いて覆う絶縁保護膜と、前記半導体素子本体の裏面、側面および前記表面と前記側面との間の角部を少なくとも覆うように形成された絶縁性接着剤層とを具備することを特徴としている。   A semiconductor element according to an aspect of the present invention includes a semiconductor element body, an electrode pad disposed on the surface of the semiconductor element body, and an insulating protective film that covers the surface except for an outer peripheral region while exposing the electrode pad. And an insulating adhesive layer formed so as to cover at least a back surface, a side surface, and a corner between the front surface and the side surface of the semiconductor element body.

本発明の態様に係る半導体パッケージは、素子搭載部と接続部とを有する回路基材と、前記回路基材の前記素子搭載部上に積層されて搭載された、本発明の態様に係る半導体素子を複数備える半導体素子群であって、前記複数の半導体素子は前記絶縁性接着剤層を介して接着されている半導体素子群と、前記回路基材の前記接続部と前記複数の半導体素子の前記電極パッドとを電気的に接続する接続部材と、前記複数の半導体素子を前記接続部材と共に封止する封止部とを具備することを特徴としている。   A semiconductor package according to an aspect of the present invention includes a circuit substrate having an element mounting portion and a connection portion, and a semiconductor element according to the aspect of the present invention, which is stacked and mounted on the element mounting portion of the circuit substrate. A plurality of semiconductor elements, wherein the plurality of semiconductor elements are bonded via the insulating adhesive layer, the connection portion of the circuit substrate, and the plurality of semiconductor elements. A connection member that electrically connects the electrode pad and a sealing portion that seals the plurality of semiconductor elements together with the connection member are provided.

本発明の態様に係る半導体素子は、半導体素子本体の裏面、側面および表面と側面との間の角部を絶縁性接着剤層で覆っているため、接続部材の高さを低くすることができる。その上で、絶縁性接着剤層を使用して複数の半導体素子を積層することができる。このような半導体素子を適用することによって、複数の半導体素子を積層して搭載した半導体パッケージの信頼性を保ちつつ、薄型化を実現することが可能となる。   Since the semiconductor element which concerns on the aspect of this invention has covered the corner | angular part between the back surface of a semiconductor element main body, a side surface, and the surface and a side surface with an insulating adhesive layer, it can make the height of a connection member low. . In addition, a plurality of semiconductor elements can be stacked using an insulating adhesive layer. By applying such a semiconductor element, it is possible to reduce the thickness while maintaining the reliability of a semiconductor package in which a plurality of semiconductor elements are stacked and mounted.

以下、本発明を実施するための形態について、図面を参照して説明する。図１および図２は本発明の実施形態による半導体素子の構成を示す図であり、図１は半導体素子の断面図、図２は図１の一部を拡大して示す断面図である。これらの図に示す半導体素子１は、半導体素子本体として半導体基板（Ｓｉ基板等）２を具備している。半導体基板２の表面２ａ側には電極パッド（Ａｌパッド等）３が配置されている。   Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. 1 and 2 are diagrams showing a configuration of a semiconductor device according to an embodiment of the present invention. FIG. 1 is a cross-sectional view of the semiconductor device, and FIG. 2 is a cross-sectional view showing a part of FIG. A semiconductor element 1 shown in these drawings includes a semiconductor substrate (Si substrate or the like) 2 as a semiconductor element body. An electrode pad (Al pad or the like) 3 is arranged on the surface 2 a side of the semiconductor substrate 2.

半導体素子１を構成する半導体基板２は、チップリング４で囲われた素子領域５と、その外周部分に当たる外周領域６とを有している。外周領域６は半導体ウェーハを切断して半導体素子１を個片化する際のダイシング領域に相当する。半導体基板２の素子領域５内には、図示を省略したトランジスタ等を含む素子構造体が形成されている。さらに、半導体基板２の表面２ａ上には、多層配線膜やパッシベーション膜等を構成する積層膜７が形成されている。チップリング４は積層膜７内に設けられている。   A semiconductor substrate 2 constituting the semiconductor element 1 has an element region 5 surrounded by a chip ring 4 and an outer peripheral region 6 corresponding to the outer peripheral portion thereof. The outer peripheral area 6 corresponds to a dicing area when the semiconductor element is cut into pieces by cutting the semiconductor wafer. In the element region 5 of the semiconductor substrate 2, an element structure including a transistor and the like (not shown) is formed. Furthermore, on the surface 2a of the semiconductor substrate 2, a laminated film 7 constituting a multilayer wiring film, a passivation film or the like is formed. The tip ring 4 is provided in the laminated film 7.

積層膜７はＣｕ配線等の金属配線８と絶縁膜９とで構成された多層構造の配線層１０とパッシベーション層１１とを有している。金属配線８は素子領域５内に設けられており、その一端は電極パッド３と接続されている。言い換えると、Ａｌパッド等からなる電極パッド３は金属配線８上に形成されている。絶縁膜９は金属配線８の層間絶縁膜として機能するものであり、例えばＳｉＯx膜や低誘電率絶縁膜等で構成される。低誘電率絶縁膜はフッ素がドープされた酸化ケイ素（ＳｉＯＦ）、炭素がドープされた酸化ケイ素（ＳｉＯＣ）、有機シリカ、これらの多孔質体等で構成される。配線層１０上にはＳｉＯx膜やＳｉＮx膜等の絶縁膜で構成されたパッシベーション層１１が設けられている。 The laminated film 7 has a wiring layer 10 and a passivation layer 11 having a multilayer structure composed of a metal wiring 8 such as a Cu wiring and an insulating film 9. The metal wiring 8 is provided in the element region 5, and one end thereof is connected to the electrode pad 3. In other words, the electrode pad 3 made of an Al pad or the like is formed on the metal wiring 8. The insulating film 9 functions as an interlayer insulating film of the metal wiring 8, and is composed of, for example, a SiO x film or a low dielectric constant insulating film. The low dielectric constant insulating film is composed of silicon oxide (SiOF) doped with fluorine, silicon oxide (SiOC) doped with carbon, organic silica, a porous body thereof, and the like. A passivation layer 11 made of an insulating film such as a SiO x film or a SiN x film is provided on the wiring layer 10.

パッシベーション層１１上には絶縁保護膜（素子保護膜）１２としてポリイミド樹脂等からなる絶縁樹脂層が設けられている。これらパッシベーション層１１や絶縁保護膜１２は電極パッド３が半導体素子１の表面に露出するように形成されている。積層膜７を構成するパッシベーション層１１は半導体基板２の表面２ａ全体に形成されているが、絶縁保護膜１２は素子領域５を覆うように形成されている。すなわち、絶縁保護膜１２は半導体基板２の表面２ａのうち外周領域６を除く部分を覆うように形成されている。   On the passivation layer 11, an insulating resin layer made of polyimide resin or the like is provided as an insulating protective film (element protective film) 12. The passivation layer 11 and the insulating protective film 12 are formed so that the electrode pad 3 is exposed on the surface of the semiconductor element 1. The passivation layer 11 constituting the laminated film 7 is formed on the entire surface 2 a of the semiconductor substrate 2, but the insulating protective film 12 is formed so as to cover the element region 5. That is, the insulating protective film 12 is formed so as to cover a portion of the surface 2 a of the semiconductor substrate 2 excluding the outer peripheral region 6.

このように、半導体基板２の外周領域６には絶縁保護膜１２が存在していない。これは外周領域６が半導体ウェーハのダイシング領域に相当するためである。外周領域（ダイシング領域）６まで絶縁保護膜（ポリイミド樹脂層等の絶縁樹脂層）１２が存在していると、半導体ウェーハをブレードダイシング（切断）する際に絶縁保護膜１２が剥離したり、またブレードが絶縁保護膜１２で目詰まりを起こして切断不良（チッピングや欠け等）が生じやすくなるためである。従来の半導体素子はこの状態でワイヤボンディングを実施していたため、ボンディングワイヤ（金属ワイヤ）は半導体素子の絶縁保護膜で覆われていない角部と接触しないようなループ高さを維持する必要があった。   Thus, the insulating protective film 12 does not exist in the outer peripheral region 6 of the semiconductor substrate 2. This is because the outer peripheral region 6 corresponds to a dicing region of the semiconductor wafer. If the insulating protective film (insulating resin layer such as a polyimide resin layer) 12 exists up to the outer peripheral region (dicing region) 6, the insulating protective film 12 may be peeled off when the semiconductor wafer is blade-diced (cut). This is because the blade is easily clogged with the insulating protective film 12, and cutting defects (such as chipping and chipping) are likely to occur. Since the conventional semiconductor element performs wire bonding in this state, it is necessary to maintain the loop height so that the bonding wire (metal wire) does not come into contact with the corners not covered with the insulating protective film of the semiconductor element. It was.

上述したような点に対して、この実施形態の半導体素子１は半導体基板２の裏面２ｂ、側面２ｃ、および表面２ａのうちの絶縁保護膜１２が配置されていない部分（外周領域６）を覆うように形成された絶縁性接着剤層１３を有している。絶縁性接着剤層１３は少なくとも半導体基板２の裏面２ｂから側面２ｃと表面２ａとの間の角部までを覆うように形成されていればよい。半導体基板２の裏面２ｂに配置された絶縁性接着剤層１３は、後述するように半導体素子１を回路基材上に積層して搭載する際に、回路基材と半導体素子１との間の接着剤や半導体素子１間の接着剤として使用されるものである。   In contrast to the above-described points, the semiconductor element 1 of this embodiment covers the back surface 2b, the side surface 2c, and the surface 2a of the semiconductor substrate 2 where the insulating protective film 12 is not disposed (outer peripheral region 6). It has the insulating adhesive layer 13 formed in this way. The insulating adhesive layer 13 may be formed so as to cover at least the back surface 2b of the semiconductor substrate 2 to the corner between the side surface 2c and the front surface 2a. The insulating adhesive layer 13 disposed on the back surface 2b of the semiconductor substrate 2 is disposed between the circuit substrate and the semiconductor element 1 when the semiconductor element 1 is stacked and mounted on the circuit substrate as will be described later. It is used as an adhesive or an adhesive between the semiconductor elements 1.

絶縁性接着剤層１３は５μｍ以上の厚さを有することが好ましい。絶縁性接着剤層１３の厚さが５μｍ未満であると、回路基材と半導体素子１との間の接着性や半導体素子１間の接着性が低下するおそれがある。絶縁性接着剤層１３を単に接着剤として使用する場合、その厚さが厚すぎると複数の半導体素子１の積層厚を厚くするだけであるため、絶縁性接着剤層１３の厚さは３０μｍ以下とすることが好ましい。典型的な絶縁性接着剤層１３の厚さは、例えば１０μｍである。絶縁性接着剤層１３にスペーサ層としての機能を持たせる場合には、その厚さは６０μｍ以下とすることが好ましい。この場合、絶縁性接着剤層１３の厚さは２０μｍ以上とすることが好ましい。絶縁性接着剤層１３の厚さは一様である必要はなく、例えば半導体基板２の裏面２ｂを覆う部分のみを厚くしてもよい。   The insulating adhesive layer 13 preferably has a thickness of 5 μm or more. If the thickness of the insulating adhesive layer 13 is less than 5 μm, the adhesion between the circuit substrate and the semiconductor element 1 and the adhesion between the semiconductor elements 1 may be reduced. When the insulating adhesive layer 13 is simply used as an adhesive, the thickness of the insulating adhesive layer 13 is 30 μm or less because if the thickness is too thick, the stacked thickness of the plurality of semiconductor elements 1 is only increased. It is preferable that A typical insulating adhesive layer 13 has a thickness of 10 μm, for example. When the insulating adhesive layer 13 has a function as a spacer layer, the thickness is preferably 60 μm or less. In this case, the thickness of the insulating adhesive layer 13 is preferably 20 μm or more. The thickness of the insulating adhesive layer 13 does not need to be uniform. For example, only the portion covering the back surface 2b of the semiconductor substrate 2 may be thickened.

この実施形態の半導体素子１においては、回路基材との接着剤や半導体素子１間の接着剤として用いられる絶縁性接着剤層１３を、半導体基板２の裏面のみならず、半導体基板２の側面２ｃや表面２ａの外周領域６（少なくとも側面２ｃと表面２ａとの間の角部）にまで形成している。従って、半導体素子１の表面は絶縁保護膜１２や絶縁性接着剤層１３で覆われており、さらに角部は絶縁性接着剤層１３で覆われている。絶縁性接着剤層１３は後に詳述するように、例えば接着性を有する熱硬化性絶縁樹脂で構成される。   In the semiconductor element 1 of this embodiment, the insulating adhesive layer 13 used as an adhesive with a circuit base material or an adhesive between the semiconductor elements 1 is applied not only to the back surface of the semiconductor substrate 2 but also to the side surfaces of the semiconductor substrate 2. 2c and the outer peripheral region 6 of the surface 2a (at least the corner between the side surface 2c and the surface 2a). Therefore, the surface of the semiconductor element 1 is covered with the insulating protective film 12 and the insulating adhesive layer 13, and the corners are covered with the insulating adhesive layer 13. As described later in detail, the insulating adhesive layer 13 is made of, for example, a thermosetting insulating resin having adhesiveness.

半導体素子１の角部を絶縁性接着剤層１３で覆うことによって、電極パッド３と回路基材の接続部との間を電気的に接続する接続部材としてのボンディングワイヤ（金属ワイヤ）のループ高さを、半導体素子１の角部と接触しないように維持する必要がなくなる。金属ワイヤは積極的に半導体素子１の表面や角部と接触させることもできる。従って、電極パッド３に接続される金属ワイヤ（接続部材）のループ高さを抑え、低ルーピングでの配線が可能となる。具体的には、金属ワイヤを半導体素子１の表面に這わせることで、ループ高さは電極パッド３との接続部分の高さで規定される最小高さとすることができ、さらに接続高さを低くできればワイヤ径と同等とすることも可能である。   By covering the corners of the semiconductor element 1 with the insulating adhesive layer 13, the loop height of the bonding wire (metal wire) as a connection member for electrically connecting the electrode pad 3 and the connection part of the circuit base material. Therefore, it is not necessary to maintain the height so as not to contact the corner portion of the semiconductor element 1. The metal wire can be positively brought into contact with the surface and corners of the semiconductor element 1. Therefore, the loop height of the metal wire (connecting member) connected to the electrode pad 3 is suppressed, and wiring with low looping becomes possible. Specifically, the loop height can be set to the minimum height defined by the height of the connection portion with the electrode pad 3 by placing the metal wire over the surface of the semiconductor element 1, and the connection height can be further reduced. If it can be lowered, it can be made equal to the wire diameter.

さらに、半導体素子１の表面を絶縁保護膜１２や絶縁性接着剤層１３で覆うと共に、側面も絶縁性接着剤層１３で覆うことで、電極パッド３との接続にワイヤボンディングに代えて、導電性樹脂の塗布層等を適用することも可能となる。すなわち、半導体素子１の表面や側面に導電性樹脂を直接塗布することができるため、導電性樹脂層で半導体素子１の電極パッド３と回路基材との間、また積層した半導体素子１の電極パッド３間を接続することが可能となる。電極パッド３との接続部材として金属ワイヤに代えて導電性樹脂層を適用することで、接続部材の高さをさらに低くすることができる。   Further, the surface of the semiconductor element 1 is covered with the insulating protective film 12 and the insulating adhesive layer 13, and the side surfaces are also covered with the insulating adhesive layer 13. It is also possible to apply a coating layer of a functional resin. That is, since the conductive resin can be directly applied to the surface or side surface of the semiconductor element 1, the electrode of the semiconductor element 1 laminated between the electrode pad 3 of the semiconductor element 1 and the circuit substrate with the conductive resin layer. The pads 3 can be connected. By applying a conductive resin layer as a connection member to the electrode pad 3 instead of the metal wire, the height of the connection member can be further reduced.

上述したように、接続部材としての金属ワイヤのループ高さを低く抑えたり、また接続部材として導電性樹脂層を適用することによって、後述するように複数の半導体素子１を積層してパッケージングする場合の封止材料の厚さ、ひいては半導体パッケージの厚さを薄くすることができる。さらに、接続部材として金属ワイヤを用いる場合に、その少なくとも一部を半導体素子の表面に接触させることで、樹脂封止時のワイヤ流れを抑制することができる。これらによって、複数の半導体素子を積層して搭載した半導体パッケージの小型・薄型化、さらに高歩留化や高信頼性化等を実現することが可能となる。   As described above, a plurality of semiconductor elements 1 are stacked and packaged as described later by reducing the loop height of the metal wire as the connection member or by applying a conductive resin layer as the connection member. In this case, the thickness of the sealing material, and thus the thickness of the semiconductor package can be reduced. Furthermore, when a metal wire is used as the connecting member, at least a part of the metal wire is brought into contact with the surface of the semiconductor element, whereby the wire flow during resin sealing can be suppressed. As a result, it becomes possible to realize a reduction in size and thickness of a semiconductor package in which a plurality of semiconductor elements are stacked and mounted, and to achieve a high yield and high reliability.

次に、上述した半導体素子１の製造工程について説明する。まず、絶縁性接着剤層１３を除いて、通常の半導体素子の製造工程にしたがって半導体ウェーハを作製する。半導体ウェーハは、複数の素子領域と、これら素子領域を区画するように格子状に設けられたダイシング領域とを有している。各素子領域内にはトランジスタを含む集積回路や配線等が形成されている。半導体ウェーハの表面には積層膜７や絶縁保護膜１２が形成されている。絶縁保護膜１２は前述したように素子領域内に形成されている。   Next, the manufacturing process of the semiconductor element 1 described above will be described. First, except for the insulating adhesive layer 13, a semiconductor wafer is manufactured according to a normal semiconductor element manufacturing process. The semiconductor wafer has a plurality of element regions and dicing regions provided in a lattice shape so as to partition these element regions. In each element region, an integrated circuit including a transistor, wiring, and the like are formed. A laminated film 7 and an insulating protective film 12 are formed on the surface of the semiconductor wafer. The insulating protective film 12 is formed in the element region as described above.

図３Ａに示すように、ダイシングブレード２１を用いて半導体ウェーハ２２をダイシング領域に沿ってハーフダイシングする。ハーフダイシングは半導体ウェーハ２２の表面（素子形成面）２２ａ側からダイシングブレード２１で溝２３を形成し、この溝２３の深さが半導体ウェーハ２２の厚さの範囲内となるように実施される。次いで、図３Ｂに示すように、溝２３を形成した半導体ウェーハ２２の表面２２ａに保護テープ２４を貼りつける。この後、図３Ｃに示すように、半導体ウェーハ２２の裏面２２ｂを砥石２５で研削する。裏面研削は半導体ウェーハ２２の表面２２ａ側から形成した溝２３に達するまで行われる。半導体ウェーハ２２の裏面２２ｂは必要に応じてバフ等で研磨される。   As shown in FIG. 3A, the semiconductor wafer 22 is half-diced along the dicing region using a dicing blade 21. Half dicing is performed such that a groove 23 is formed by a dicing blade 21 from the surface (element forming surface) 22 a side of the semiconductor wafer 22, and the depth of the groove 23 is within the thickness range of the semiconductor wafer 22. Next, as shown in FIG. 3B, a protective tape 24 is attached to the surface 22a of the semiconductor wafer 22 in which the grooves 23 are formed. Thereafter, as shown in FIG. 3C, the back surface 22 b of the semiconductor wafer 22 is ground with a grindstone 25. The back surface grinding is performed until the groove 23 formed from the front surface 22a side of the semiconductor wafer 22 is reached. The back surface 22b of the semiconductor wafer 22 is polished with a buff or the like as necessary.

表面２２ａ側から溝２３を形成した半導体ウェーハ２２の裏面２２ｂを、溝２３に達するまで研削（裏面研削）することによって、複数の素子領域がそれぞれ半導体素子１として個片化される。この段階では複数の半導体素子１はそれぞれ保護テープ２４に保持されているため、全体としてはウェーハ形状を保っている。この状態を図４に示す。保護テープ２４は複数の半導体素子１の表面側をそれぞれ保持している。隣接する半導体素子１の間には、ハーフダイシングで形成した溝２３の幅に相当する空間２６が存在している。さらに、半導体素子１の表面と保護テープ２４との間にも、絶縁保護膜１２が存在していない部分に対応して空間２７が存在している。   By grinding the back surface 22b of the semiconductor wafer 22 in which the groove 23 is formed from the front surface 22a side until the groove 23 is reached (back surface grinding), each of the plurality of element regions is singulated as the semiconductor element 1. At this stage, since the plurality of semiconductor elements 1 are respectively held on the protective tape 24, the wafer shape as a whole is maintained. This state is shown in FIG. The protective tape 24 holds the surface side of the plurality of semiconductor elements 1. A space 26 corresponding to the width of the groove 23 formed by half dicing exists between adjacent semiconductor elements 1. Further, a space 27 exists between the surface of the semiconductor element 1 and the protective tape 24 corresponding to a portion where the insulating protective film 12 does not exist.

次に、図５Ａに示すように、保護テープ２４に保持されてウェーハ形状を保っている複数の半導体素子１を、絶縁性接着剤層１３を成形するための金型２８内に配置する。絶縁性接着剤層１３の成形には、例えばコンプレッション成形のようなモールド成形が適用される。ウェーハ形状が保持された複数の半導体素子１は、その表面（集積回路や電極の形成面）が上方を向くように金型２８内に配置される。なお、絶縁性接着剤層１３の形成にはモールド成形に代えて、液状の絶縁性接着剤の塗布等を適用することも可能である。   Next, as shown in FIG. 5A, a plurality of semiconductor elements 1 held by the protective tape 24 and maintaining the wafer shape are arranged in a mold 28 for molding the insulating adhesive layer 13. For forming the insulating adhesive layer 13, for example, molding such as compression molding is applied. The plurality of semiconductor elements 1 in which the wafer shape is held are arranged in the mold 28 such that the surfaces (formation surfaces of integrated circuits and electrodes) face upward. The insulating adhesive layer 13 can be formed by applying a liquid insulating adhesive instead of molding.

複数の半導体素子１を配置した金型２８内に、絶縁性接着剤層１３の形成材料となる絶縁樹脂材料２９を投入した後、図５Ｂに示すように金型２８を閉じて、絶縁樹脂材料２９に応じた圧力と温度を加えて成型する。絶縁性接着剤層１３の形成材料となる絶縁樹脂材料２９としては、例えばエポキシ樹脂のような接着性を有する熱硬化性絶縁樹脂が用いられる。なお、成形性や接着性を満足していれば、絶縁樹脂材料２９としてアクリル樹脂のような熱可塑性絶縁樹脂や紫外線硬化型の絶縁樹脂等を使用してもよい。   After an insulating resin material 29 as a material for forming the insulating adhesive layer 13 is put into a mold 28 in which a plurality of semiconductor elements 1 are arranged, the mold 28 is closed as shown in FIG. The molding is performed by applying a pressure and temperature corresponding to 29. As the insulating resin material 29 used as the material for forming the insulating adhesive layer 13, for example, a thermosetting insulating resin having adhesiveness such as an epoxy resin is used. If the moldability and adhesiveness are satisfied, the insulating resin material 29 may be a thermoplastic insulating resin such as an acrylic resin, an ultraviolet curable insulating resin, or the like.

圧力と温度が加えられた絶縁樹脂材料２９は、図６に示すように、半導体素子１の裏面を覆うように層状に成形されると同時に、隣接する半導体素子１間の空間２６や半導体素子１の表面と保護テープ２４との間の空間２７に充填される。このようにして、ウェーハ形状が保持された複数の半導体素子１の所定面を絶縁樹脂材料２９で被覆（封止）することによって、半導体素子１の裏面、側面、および表面のうちの絶縁保護膜１２が形成されていない部分を覆う絶縁性接着剤層１３が形成される。   As shown in FIG. 6, the insulating resin material 29 to which pressure and temperature are applied is formed into a layer so as to cover the back surface of the semiconductor element 1, and at the same time, the space 26 between the adjacent semiconductor elements 1 and the semiconductor element 1. The space 27 between the surface and the protective tape 24 is filled. In this way, by covering (sealing) a predetermined surface of the plurality of semiconductor elements 1 in which the wafer shape is held with the insulating resin material 29, an insulating protective film among the back surface, side surface, and surface of the semiconductor element 1 An insulating adhesive layer 13 is formed to cover the portion where 12 is not formed.

絶縁樹脂材料２９として熱硬化性絶縁樹脂を用いる場合には、絶縁性接着剤層１３が回路基材への実装工程で接着剤として機能するように、半硬化状態（Ｂステージ）の熱硬化性絶縁樹脂層を形成する。このように、半導体素子１の段階における絶縁性接着剤層１３は、半硬化状態の熱硬化性絶縁樹脂層を備えている。絶縁樹脂材料２９として熱可塑性絶縁樹脂を使用する場合には、半導体素子１の絶縁性接着剤層１３は熱可塑性絶縁樹脂層を備えており、絶縁樹脂材料２９として紫外線硬化型絶縁樹脂を使用する場合には、半導体素子１の絶縁性接着剤１３は硬化前の紫外線硬化型絶縁樹脂層を備えている。   When a thermosetting insulating resin is used as the insulating resin material 29, the thermosetting property in a semi-cured state (B stage) so that the insulating adhesive layer 13 functions as an adhesive in the mounting process on the circuit substrate. An insulating resin layer is formed. Thus, the insulating adhesive layer 13 at the stage of the semiconductor element 1 includes a semi-cured thermosetting insulating resin layer. When a thermoplastic insulating resin is used as the insulating resin material 29, the insulating adhesive layer 13 of the semiconductor element 1 includes a thermoplastic insulating resin layer, and an ultraviolet curable insulating resin is used as the insulating resin material 29. In some cases, the insulating adhesive 13 of the semiconductor element 1 includes an ultraviolet curable insulating resin layer before curing.

次に、保護テープ２４に保持されて、かつ絶縁性接着剤層１３（絶縁樹脂材料２９）で覆われた複数の半導体素子１を、金型２８から取り出した後、図７Ａに示すようにダイシングテープ３０に貼り付ける。ダイシングテープ３０は複数の半導体素子１の絶縁性接着剤層１３で覆われた裏面側に貼り付けられる。複数の半導体素子１をダイシングテープ３０に貼り付けた後に、表面側の保護テープ２４を剥離する。この後、図７Ｂに示すように、隣接する半導体素子１間に存在する絶縁性接着剤層１３をブレード３１で切断することによって、複数の半導体素子１をそれぞれ個片化する。図７Ｂにおいて、符号３２はブレード３１による切断溝を示している。   Next, after the plurality of semiconductor elements 1 held by the protective tape 24 and covered with the insulating adhesive layer 13 (insulating resin material 29) are taken out from the mold 28, dicing is performed as shown in FIG. 7A. Affix to tape 30. The dicing tape 30 is attached to the back surface side covered with the insulating adhesive layer 13 of the plurality of semiconductor elements 1. After the plurality of semiconductor elements 1 are attached to the dicing tape 30, the protective tape 24 on the surface side is peeled off. Thereafter, as shown in FIG. 7B, the insulating adhesive layer 13 existing between adjacent semiconductor elements 1 is cut with a blade 31 to divide the plurality of semiconductor elements 1 into individual pieces. In FIG. 7B, reference numeral 32 indicates a cutting groove formed by the blade 31.

このようにして、表面の大部分（素子領域）が絶縁保護膜１２で被覆され、かつ絶縁保護膜１２で被覆されていない部分（外周領域）、裏面および側面を絶縁性接着剤層１３で覆った半導体素子１が作製される。この状態を図８に示す。絶縁性接着剤層１３を切断するブレード３１には、ダイシングブレード２１より刃厚が薄いものを使用する。これによって、半導体素子１の側面も絶縁性接着剤層１３で覆われた状態を維持することができる。絶縁性接着剤層１３の切断には、レーザ加工等を適用することも可能である。   In this way, most of the surface (element region) is covered with the insulating protective film 12, and the portion not covered with the insulating protective film 12 (outer peripheral region), the back surface and the side surfaces are covered with the insulating adhesive layer 13. The semiconductor device 1 is manufactured. This state is shown in FIG. As the blade 31 for cutting the insulating adhesive layer 13, a blade having a blade thickness smaller than that of the dicing blade 21 is used. As a result, the state in which the side surface of the semiconductor element 1 is also covered with the insulating adhesive layer 13 can be maintained. Laser cutting or the like can be applied to the cutting of the insulating adhesive layer 13.

次に、本発明の実施形態による半導体パッケージについて、図９ないし図１１を参照して説明する。図９は第１の実施形態によるスタック型マルチチップ構造の半導体パッケージの構成を示す断面図である。同図に示す半導体パッケージ４１は、素子搭載用の回路基材として回路基板４２を有している。回路基板４２は半導体素子を搭載することが可能で、かつ表面や内部に設けられた配線網を有するものであればよい。回路基材はリードフレームのような素子搭載部と回路部とを一体化したものであってもよい。   Next, a semiconductor package according to an embodiment of the present invention will be described with reference to FIGS. FIG. 9 is a cross-sectional view showing the configuration of the stacked multichip semiconductor package according to the first embodiment. A semiconductor package 41 shown in the figure has a circuit board 42 as a circuit substrate for mounting elements. The circuit board 42 only needs to be capable of mounting semiconductor elements and having a wiring network provided on the surface or inside. The circuit substrate may be one in which an element mounting part such as a lead frame and a circuit part are integrated.

回路基板４２を構成する基板には、樹脂基板、セラミックス基板、ガラス基板等の絶縁基板、あるいは半導体基板を適用することができる。回路基板４２の具体例としては、ガラス−エポキシ樹脂やＢＴ樹脂（ビスマレイミド・トリアジン樹脂）等を使用したプリント配線基板が挙げられる。回路基板４２の下面側には外部接続端子４３が設けられている。ここではＢＧＡパッケージを示しているため、回路基板４２の下面に外部接続端子４３として半田バンプが設けられている。半導体パッケージ４１はＬＧＡパッケージ等にも適用可能であり、この場合には外部接続端子４３として金属ランドが適用される。   An insulating substrate such as a resin substrate, a ceramic substrate, a glass substrate, or a semiconductor substrate can be applied to the substrate constituting the circuit substrate 42. Specific examples of the circuit board 42 include a printed wiring board using glass-epoxy resin, BT resin (bismaleimide / triazine resin), or the like. External connection terminals 43 are provided on the lower surface side of the circuit board 42. Since a BGA package is shown here, solder bumps are provided as external connection terminals 43 on the lower surface of the circuit board 42. The semiconductor package 41 can also be applied to an LGA package or the like. In this case, a metal land is applied as the external connection terminal 43.

回路基板４２の上面には素子搭載部が設けられており、その周囲には外部接続端子４３と配線網を介して電気的に接続された接続パッド４４が設けられている。接続パッド４４はワイヤボンディング時の接続部、導電性樹脂層との接続部等となる。回路基板４２の素子搭載部には複数の半導体素子１が積層されて搭載されており、半導体素子群４５を構成している。図９は４個の半導体素子１Ａ〜１Ｄを階段状に積層した状態を示している。   An element mounting portion is provided on the upper surface of the circuit board 42, and a connection pad 44 electrically connected to the external connection terminal 43 via a wiring network is provided around the element mounting portion. The connection pad 44 becomes a connection part at the time of wire bonding, a connection part with a conductive resin layer, or the like. A plurality of semiconductor elements 1 are stacked and mounted on the element mounting portion of the circuit board 42 to constitute a semiconductor element group 45. FIG. 9 shows a state in which four semiconductor elements 1A to 1D are stacked stepwise.

第１ないし第４の半導体素子１Ａ〜１Ｄには前述した実施形態の半導体素子１が適用されており、その裏面、側面、および表面のうちの絶縁保護膜１２が形成されていない部分（外周領域）には絶縁性接着剤層１３が形成されている。第１の半導体素子１Ａはその裏面側に存在する絶縁性接着剤層１３を介して回路基板４２の素子搭載部と接着されている。第２の半導体素子１Ｂはその裏面側に存在する絶縁性接着剤層１３を介して第１の半導体素子１Ａと接着されている。第３および第４の半導体素子１Ｃ、１Ｄも同様であり、絶縁性接着剤層１３を介して下層側の半導体素子１Ｂ、１Ｃと接着されている。   The semiconductor element 1 of the above-described embodiment is applied to the first to fourth semiconductor elements 1A to 1D, and the back surface, side surface, and part of the surface where the insulating protective film 12 is not formed (outer peripheral region) ) Is formed with an insulating adhesive layer 13. The first semiconductor element 1A is bonded to the element mounting portion of the circuit board 42 via the insulating adhesive layer 13 present on the back surface side. The second semiconductor element 1B is bonded to the first semiconductor element 1A via an insulating adhesive layer 13 existing on the back side thereof. The same applies to the third and fourth semiconductor elements 1C and 1D, which are bonded to the lower-layer side semiconductor elements 1B and 1C via the insulating adhesive layer 13.

第１ないし第４の半導体素子１Ａ〜１Ｄの具体例としては、例えばＮＡＮＤ型フラッシュメモリのような半導体メモリ素子が挙げられる。これら多段に積層された半導体素子上、具体的には最上層の半導体素子１Ｄ上には、必要に応じてコントローラ素子等を積層してもよい。半導体素子群４５を構成する半導体素子１の数は複数個（少なくとも２個）であればよく、４個に限られるものではない。半導体素子群４５は２個または３個、あるいは５個以上の半導体素子１で構成してもよい。   Specific examples of the first to fourth semiconductor elements 1A to 1D include semiconductor memory elements such as NAND flash memories. On these semiconductor elements stacked in multiple stages, specifically, on the uppermost semiconductor element 1D, a controller element or the like may be stacked as necessary. The number of the semiconductor elements 1 constituting the semiconductor element group 45 may be plural (at least two), and is not limited to four. The semiconductor element group 45 may be composed of two, three, or five or more semiconductor elements 1.

第１ないし第４の半導体素子１Ａ〜１Ｄに設けられた電極パッド３Ａ〜３Ｄは、それぞれ半導体素子１の外形の一辺（例えば一方の長辺）に沿って配列されている。すなわち、第１ないし第４の半導体素子１Ａ〜１Ｄはそれぞれ片側パッド構造を有している。片側パッド構造を有する第１ないし第４の半導体素子１Ａ〜１Ｄは、各電極パッド３Ａ〜３Ｄが露出するように階段状に積層されている。例えば、半導体素子１が長辺片側パッド構造を有する場合、第１ないし第４の半導体素子１Ａ〜１Ｄの短辺を揃え、かつ電極パッド３Ａ〜３Ｄが露出するように長辺をずらして積層される。   The electrode pads 3A to 3D provided on the first to fourth semiconductor elements 1A to 1D are arranged along one side (for example, one long side) of the outer shape of the semiconductor element 1, respectively. That is, each of the first to fourth semiconductor elements 1A to 1D has a one-side pad structure. The first to fourth semiconductor elements 1A to 1D having the one-side pad structure are stacked in a stepped manner so that the electrode pads 3A to 3D are exposed. For example, when the semiconductor element 1 has a long side one side pad structure, the short sides of the first to fourth semiconductor elements 1A to 1D are aligned and the long sides are shifted so that the electrode pads 3A to 3D are exposed. The

第１ないし第４の半導体素子１Ａ〜１Ｄの電極パッド３Ａ〜３Ｄは、配線基板４２の接続パッド４４と金属ワイヤ４６を介して電気的に接続されている。各電極パッド３Ａ〜３Ｄの電気特性や信号特性等が等しい場合には、積層された半導体素子１Ａ〜１Ｄの電極パッド３Ａ〜３Ｄを金属ワイヤ４６で順に接続することができる。この場合の金属ワイヤ４６は個々にボンディンク工程を実施して接続してもよいし、１本の金属ワイヤ４６で電極パッド３Ａ〜３Ｄを順に接続してもよい。   The electrode pads 3A to 3D of the first to fourth semiconductor elements 1A to 1D are electrically connected to the connection pads 44 of the wiring board 42 via the metal wires 46. When the electrical characteristics and signal characteristics of the electrode pads 3 </ b> A to 3 </ b> D are the same, the electrode pads 3 </ b> A to 3 </ b> D of the stacked semiconductor elements 1 </ b> A to 1 </ b> D can be sequentially connected by the metal wires 46. In this case, the metal wires 46 may be connected by performing a bonding process individually, or the electrode pads 3 </ b> A to 3 </ b> D may be connected in order by one metal wire 46.

金属ワイヤ４６は例えばリバースボンディングを適用して接続されている。すなわち、電極パッド３上には図示を省略した金属バンプが予め形成されている。金属ワイヤ４６の一端は回路基板４２の接続パッド４４にボール接続されており、他端は電極パッド３上に形成された金属バンプに接続されている。そして、回路基板４２上に積層された複数の半導体素子１Ａ〜１Ｄを、金属ワイヤ４６と共に樹脂封止部４７で封止することよって、積層構造を有する半導体パッケージ４１が構成される。樹脂封止部４７には一般的なエポキシ樹脂等が用いられ、その形成にはトランスファー成形等が適用される。   The metal wire 46 is connected by applying reverse bonding, for example. That is, metal bumps (not shown) are formed on the electrode pad 3 in advance. One end of the metal wire 46 is ball-connected to the connection pad 44 of the circuit board 42, and the other end is connected to a metal bump formed on the electrode pad 3. A plurality of semiconductor elements 1 </ b> A to 1 </ b> D stacked on the circuit board 42 are sealed together with the metal wires 46 by the resin sealing portion 47, thereby forming the semiconductor package 41 having a stacked structure. A general epoxy resin or the like is used for the resin sealing portion 47, and transfer molding or the like is applied for the formation thereof.

図１０は４個の半導体素子１Ａ〜１Ｄを階段状に積層し、さらにその上にスペーサ４８を介して４個の半導体素子１Ｅ〜１Ｈを反対方向に階段状に積層した状態を示している。図１０に示す半導体パッケージ４１において、第１ないし第４の半導体素子１Ａ〜１Ｄは各電極パッド３Ａ〜３Ｄが露出するように階段状に積層されており、第５ないし第８の半導体素子１Ｅ〜１Ｈは各電極パッド３Ｅ〜３Ｈが露出するように、第１ないし第４の半導体素子１Ａ〜１Ｄとは反対方向に階段状に積層されている。   FIG. 10 shows a state in which four semiconductor elements 1A to 1D are stacked stepwise, and further four semiconductor elements 1E to 1H are stacked stepwise in the opposite direction via spacers 48 thereon. In the semiconductor package 41 shown in FIG. 10, the first to fourth semiconductor elements 1A to 1D are stacked stepwise so that the electrode pads 3A to 3D are exposed, and the fifth to eighth semiconductor elements 1E to 1E. 1H is stacked stepwise in the opposite direction to the first to fourth semiconductor elements 1A to 1D so that the electrode pads 3E to 3H are exposed.

この場合にも図９と同様に、第１の半導体素子１Ａはその裏面側に存在する絶縁性接着剤層１３を介して回路基板４２の素子搭載部に接着される。第２ないし第４の半導体素子１Ｂ〜１Ｄはその裏面側に存在する絶縁性接着剤層１３を介して下層側の半導体素子と接着される。第４の半導体素子１Ｅはその裏面側に存在する絶縁性接着剤層１３を介してスペーサ４８に接着され、第５ないし第８の半導体素子１Ｅ〜１Ｈはその裏面側に存在する絶縁性接着剤層１３を介して下層側の半導体素子と接着される。   Also in this case, as in FIG. 9, the first semiconductor element 1A is bonded to the element mounting portion of the circuit board 42 via the insulating adhesive layer 13 present on the back surface side. 2nd thru | or 4th semiconductor element 1B-1D are adhere | attached with the semiconductor element of a lower layer side via the insulating adhesive bond layer 13 which exists in the back surface side. The fourth semiconductor element 1E is bonded to the spacer 48 via the insulating adhesive layer 13 existing on the back side thereof, and the fifth to eighth semiconductor elements 1E to 1H are insulating adhesives existing on the back side thereof. It is bonded to the lower semiconductor element through the layer 13.

第１ないし第４の半導体素子１Ａ〜１Ｄの電極パッド３Ａ〜３Ｄは第１の金属ワイヤ４６Ａを介して第１の接続パッド４４Ａと接続され、第５ないし第８の半導体素子１Ｅ〜１Ｈの電極パッド３Ｅ〜３Ｈは第２の金属ワイヤ４６Ｂを介して第２の接続パッド４４Ｂと接続されている。第１ないし第４の半導体素子１Ａ〜１Ｄの電極パッド３Ａ〜３Ｄのうち、電気特性や信号特性が等しい電極パッド３Ａ〜３Ｄは第１の金属ワイヤ４６Ａで順に接続されている。第５ないし第８の半導体素子１Ｅ〜１Ｈも同様であり、電気特性や信号特性が等しい電極パッド３Ｅ〜３Ｈは第２の金属ワイヤ４６Ｂで順に接続されている。   The electrode pads 3A to 3D of the first to fourth semiconductor elements 1A to 1D are connected to the first connection pad 44A via the first metal wire 46A, and the electrodes of the fifth to eighth semiconductor elements 1E to 1H. The pads 3E to 3H are connected to the second connection pad 44B through the second metal wire 46B. Of the electrode pads 3A to 3D of the first to fourth semiconductor elements 1A to 1D, the electrode pads 3A to 3D having the same electrical characteristics and signal characteristics are sequentially connected by a first metal wire 46A. The same applies to the fifth to eighth semiconductor elements 1E to 1H, and the electrode pads 3E to 3H having the same electrical characteristics and signal characteristics are sequentially connected by the second metal wire 46B.

上述した半導体パッケージ４１においては、半導体素子１の裏面のみならず、側面や表面の外周領域も絶縁性接着剤層１３で覆われているため、金属ワイヤ４７のループ高さを半導体素子１の角部と接触しないように維持する必要がない。従って、金属ワイヤ４６のループ高さを極力低くすることができる。特に、最上段に位置する半導体素子１に接続された金属ワイヤ４６のループ高さは樹脂封止部４７の厚さ、ひいては半導体パッケージ４１の厚さに影響を及ぼすが、これを低くすることで半導体パッケージ４１の厚さ自体を薄くすることが可能となる。すなわち、複数の半導体素子１を積層して搭載した半導体パッケージ４１の小型・薄型化、さらに高歩留化や高信頼性化等を実現することができる。   In the semiconductor package 41 described above, not only the back surface of the semiconductor element 1 but also the side surface and the outer peripheral region of the front surface are covered with the insulating adhesive layer 13, so that the loop height of the metal wire 47 is set to the corner of the semiconductor element 1. There is no need to keep it out of contact. Therefore, the loop height of the metal wire 46 can be made as low as possible. In particular, the height of the loop of the metal wire 46 connected to the semiconductor element 1 located at the uppermost stage affects the thickness of the resin sealing portion 47 and consequently the thickness of the semiconductor package 41. By reducing this, It is possible to reduce the thickness of the semiconductor package 41 itself. That is, it is possible to realize a reduction in size and thickness of the semiconductor package 41 in which a plurality of semiconductor elements 1 are stacked and mounted, and a higher yield and higher reliability.

さらに、金属ワイヤ４７は半導体素子１の表面に存在する絶縁保護膜１２や絶縁性接着剤層１３に接触させることができるため、トランスファー成形等を適用して樹脂封止部４７を形成する際の樹脂流によるワイヤ流れを防止することができる。これは金属ワイヤ４６を絶縁保護膜１２や絶縁性接着剤層１３に接触させることで、樹脂流に対する抵抗力が向上することに加えて、金属ワイヤ４６のワイヤ立ち上り部が転倒しにくくなることによる。そして、金属ワイヤ４６のワイヤ流れを防ぐことによって、異電位ワイヤ間の接触によるショート不良の発生等を抑制することができる。従って、積層構造を有する半導体パッケージ４１の製造歩留りや信頼性をさらに高めることが可能となる。   Furthermore, since the metal wire 47 can be brought into contact with the insulating protective film 12 and the insulating adhesive layer 13 existing on the surface of the semiconductor element 1, when the resin sealing portion 47 is formed by applying transfer molding or the like. Wire flow due to resin flow can be prevented. This is because the metal wire 46 is brought into contact with the insulating protective film 12 and the insulating adhesive layer 13 so that the resistance to the resin flow is improved, and the wire rising portion of the metal wire 46 is not easily toppled. . Further, by preventing the wire flow of the metal wire 46, it is possible to suppress the occurrence of a short circuit failure due to contact between different potential wires. Accordingly, it is possible to further increase the manufacturing yield and reliability of the semiconductor package 41 having a stacked structure.

図９や図１０では電極パッド３と接続パッド４４との間を電気的に接続する接続部材として金属ワイヤ４６を用いているが、接続部材はこれに限られるものではない。前述したように、半導体素子１の表面は絶縁保護膜１２や絶縁性接着剤層１３で覆われていると共に、側面も絶縁性接着剤層１３で覆われているため、電極パッド３と接続パッド４４との間に導電性樹脂の塗布層を形成することができる。このように、接続部材には導電性樹脂の塗布層等を適用することも可能であり、この場合には接続部材の高さをさらに低くすることができる。従って、複数の半導体素子１を積層して搭載した半導体パッケージ４１の小型・薄型化、さらに高歩留化や高信頼性化等を実現することが可能となる。   9 and 10, the metal wire 46 is used as a connection member for electrically connecting the electrode pad 3 and the connection pad 44, but the connection member is not limited to this. As described above, the surface of the semiconductor element 1 is covered with the insulating protective film 12 and the insulating adhesive layer 13, and the side surface is also covered with the insulating adhesive layer 13. A conductive resin coating layer can be formed between the first and second electrodes 44. Thus, a conductive resin coating layer or the like can be applied to the connection member, and in this case, the height of the connection member can be further reduced. Accordingly, it is possible to realize a reduction in size and thickness of the semiconductor package 41 on which a plurality of semiconductor elements 1 are stacked and mounted, and a higher yield and higher reliability.

上述した実施形態の半導体パッケージ４１は、例えば以下のようにして作製される。まず、図１１Ａに示すように、回路基板４２上に第１の半導体素子１Ａを配置し、さらにその上に第２の半導体素子１Ｂを階段状に配置する。同様に、第２の半導体素子１Ｂ上に第３および第４の半導体素子１Ｃ、１Ｄを順に配置する。次いで、図１１Ｂに示すように、回路基板４２上に第１ないし第４の半導体素子１Ａ〜１Ｄを積層した積層物を熱処理して、回路基板４２と第１の半導体素子１Ａとの間、および各半導体素子１間を接着する。   The semiconductor package 41 of the above-described embodiment is manufactured as follows, for example. First, as shown in FIG. 11A, the first semiconductor element 1A is arranged on the circuit board 42, and the second semiconductor element 1B is arranged thereon in a step shape. Similarly, the third and fourth semiconductor elements 1C and 1D are sequentially arranged on the second semiconductor element 1B. Next, as shown in FIG. 11B, the laminate in which the first to fourth semiconductor elements 1A to 1D are stacked on the circuit board 42 is heat-treated, and between the circuit board 42 and the first semiconductor element 1A, and The semiconductor elements 1 are bonded together.

回路基板４２と第１の半導体素子１Ａとの間、および各半導体素子１間の接着は、半導体素子１の裏面に設けられた絶縁性接着剤層１３により実施される。絶縁性接着剤層１３に半硬化状態の熱硬化性絶縁樹脂を適用した場合、接着後の絶縁性接着剤層１３は硬化状態（Ｃステージ）の絶縁樹脂となる。このように、半導体パッケージ４１を作製した段階においては、半導体素子１は硬化状態（Ｃステージ）の絶縁樹脂層（絶縁性接着剤層）１３を介して回路基板４２もしくは隣接する半導体素子１と接着されている。   Adhesion between the circuit board 42 and the first semiconductor element 1 </ b> A and between the semiconductor elements 1 is performed by the insulating adhesive layer 13 provided on the back surface of the semiconductor element 1. In the case where a semi-cured thermosetting insulating resin is applied to the insulating adhesive layer 13, the insulating adhesive layer 13 after bonding becomes a cured (C stage) insulating resin. Thus, at the stage where the semiconductor package 41 is manufactured, the semiconductor element 1 is bonded to the circuit board 42 or the adjacent semiconductor element 1 via the insulating resin layer (insulating adhesive layer) 13 in a cured state (C stage). Has been.

次いで、図１１Ｃに示すように、回路基板４２の接続パッド４４と各半導体素子１Ａ〜１Ｄの電極パッド３Ａ〜３Ｄとを金属ワイヤ４６で電気的に接続する。接続部材として導電性樹脂を用いる場合には、回路基板４２の接続パッド４４と各半導体素子１Ａ〜１Ｄの電極パッド３Ａ〜３Ｄとを電気的に接続するように、半導体素子１の表面（絶縁保護膜１２および絶縁性接着剤層１３で覆われた表面）および側面（絶縁性接着剤層１３で覆われた側面）、さらに回路基板４２の表面に導電性樹脂を塗布する。導電性樹脂の塗布にはディスペンサ等が用いられる。この後、樹脂封止工程や外部接続端子の形成工程を経ることによって、半導体パッケージ４１が作製される。   Next, as illustrated in FIG. 11C, the connection pads 44 of the circuit board 42 and the electrode pads 3 </ b> A to 3 </ b> D of the semiconductor elements 1 </ b> A to 1 </ b> D are electrically connected by metal wires 46. When a conductive resin is used as the connection member, the surface (insulation protection) of the semiconductor element 1 is electrically connected to the connection pads 44 of the circuit board 42 and the electrode pads 3A to 3D of the semiconductor elements 1A to 1D. A conductive resin is applied to the surface and the side surface (side surface covered with the insulating adhesive layer 13) and the surface of the circuit board 42 covered with the film 12 and the insulating adhesive layer 13. A dispenser or the like is used for applying the conductive resin. Thereafter, the semiconductor package 41 is manufactured through a resin sealing process and an external connection terminal forming process.

次に、本発明の第２の実施形態による半導体パッケージについて、図１２および図１３を参照して説明する。図１２は第２の実施形態による半導体パッケージの構成を示す断面図である。図１２に示す半導体パッケージ５１は、第１の実施形態と同様に回路基材として配線基板５２を有している。配線基板５２の構成は第１の実施形態と同様である。配線基板５２の下面側には外部接続端子５３として半田バンプ等が設けられている。   Next, the semiconductor package by the 2nd Embodiment of this invention is demonstrated with reference to FIG. 12 and FIG. FIG. 12 is a cross-sectional view showing the configuration of the semiconductor package according to the second embodiment. The semiconductor package 51 shown in FIG. 12 has a wiring board 52 as a circuit base material as in the first embodiment. The configuration of the wiring board 52 is the same as that of the first embodiment. Solder bumps and the like are provided as external connection terminals 53 on the lower surface side of the wiring board 52.

回路基板５２の上面には素子搭載部が設けられており、その周囲には外部接続端子５３と配線網を介して電気的に接続された接続パッド５４が設けられている。回路基板５２の素子搭載部には複数の半導体素子１が積層されて搭載されており、半導体素子群５５を構成している。図１２は４個の半導体素子１Ａ〜１Ｄを積層した状態を示しているが、半導体素子１の積層数はこれに限らず、複数個（２個以上）であればよい。第１ないし第４の半導体素子１Ａ〜１Ｄは矩形状でかつ同一の形状を有し、それぞれ長辺および短辺を揃えて積層されている。回路基板５２に対する素子占有面積が最小となるように、第１ないし第４の半導体素子１Ａ〜１Ｄはそれぞれ各辺を揃えて積層されている。   An element mounting portion is provided on the upper surface of the circuit board 52, and a connection pad 54 electrically connected to the external connection terminal 53 via a wiring network is provided around the element mounting portion. A plurality of semiconductor elements 1 are stacked and mounted on the element mounting portion of the circuit board 52 to constitute a semiconductor element group 55. Although FIG. 12 shows a state in which four semiconductor elements 1A to 1D are stacked, the number of stacked semiconductor elements 1 is not limited to this, and a plurality (two or more) may be used. The first to fourth semiconductor elements 1A to 1D are rectangular and have the same shape, and are laminated with their long sides and short sides aligned. The first to fourth semiconductor elements 1 </ b> A to 1 </ b> D are stacked with their sides aligned so that the element occupation area with respect to the circuit board 52 is minimized.

第１ないし第４の半導体素子１Ａ〜１Ｄの電極パッド３Ａ〜３Ｄは、回路基板５２の接続パッド５４と第１ないし第４の金属ワイヤ５６Ａ〜５６Ｄを介して電気的に接続されている。金属ワイヤ５６には一般的なＡｕワイヤやＣｕワイヤ等の金属細線が用いられる。金属ワイヤ５６はループ高さを低減することが可能な逆ボンディングを適用してワイヤボンディングすることが好ましい。すなわち、電極パッド３上に予め金属バンプを形成しておき、金属ワイヤ５６の一端を接続パッド５４にボール接続し、他端を電極パッド３上に形成された金属バンプに接続することが好ましい。   The electrode pads 3A to 3D of the first to fourth semiconductor elements 1A to 1D are electrically connected to the connection pads 54 of the circuit board 52 via the first to fourth metal wires 56A to 56D. For the metal wire 56, a general fine metal wire such as an Au wire or a Cu wire is used. The metal wire 56 is preferably wire bonded by applying reverse bonding capable of reducing the loop height. That is, it is preferable to form a metal bump on the electrode pad 3 in advance, connect one end of the metal wire 56 to the connection pad 54 with a ball, and connect the other end to the metal bump formed on the electrode pad 3.

第１ないし第４の半導体素子１Ａ〜１Ｄは各辺を揃えて積層されているため、第１ないし第３の半導体素子１Ａ、１Ｂ、１Ｃに接続された第１ないし第３の金属ワイヤ５６Ａ、５６Ｂ、５６Ｃにはそれぞれ上段側の半導体素子１が干渉する。そこで、第１の金属ワイヤ５６Ａの電極パッド３Ａとの接続側端部（素子側端部）は、上段に位置する第２の半導体素子１Ｂの絶縁性接着剤層１３内に埋め込まれている。同様に、第２および第３の金属ワイヤ５６Ｂ、５６Ｃの素子側端部は、それぞれ上段に位置する第３および第４の半導体素子１Ｃ、１Ｄの絶縁性接着剤層１３内に埋め込まれている。   Since the first to fourth semiconductor elements 1A to 1D are stacked with their sides aligned, the first to third metal wires 56A connected to the first to third semiconductor elements 1A, 1B, and 1C, The upper semiconductor element 1 interferes with 56B and 56C, respectively. Therefore, the connection side end (element side end) of the first metal wire 56A with the electrode pad 3A is embedded in the insulating adhesive layer 13 of the second semiconductor element 1B located in the upper stage. Similarly, the element side ends of the second and third metal wires 56B and 56C are embedded in the insulating adhesive layer 13 of the third and fourth semiconductor elements 1C and 1D, respectively, located in the upper stage. .

第１ないし第３の金属ワイヤ５６Ａ、５６Ｂ、５６Ｃの素子側端部が埋め込まれる第２ないし第４の半導体素子１Ｂ、１Ｃ、１Ｄの絶縁性接着剤層１３は、スペーサ層としての機能を併せ持つものである。前述した実施形態と同様に、金属ワイヤ５６は半導体素子１の表面（絶縁保護膜１２および絶縁性接着剤層１３で覆われた表面）を這わせることができるため、その高さを極力低くすることができる。このことは、第１ないし第３の半導体素子１Ａ、１Ｂ、１Ｃに接続された金属ワイヤ５６Ａ、５６Ｂ、５６Ｃについては埋め込みに必要な厚さを薄くできることを意味し、最上段の第４の半導体素子１Ｄに接続された金属ワイヤ５６Ｄについては樹脂封止厚を薄くできることを意味する。   The insulating adhesive layers 13 of the second to fourth semiconductor elements 1B, 1C, and 1D in which the element side ends of the first to third metal wires 56A, 56B, and 56C are embedded also have a function as a spacer layer. Is. Similar to the above-described embodiment, the metal wire 56 can have the surface of the semiconductor element 1 (the surface covered with the insulating protective film 12 and the insulating adhesive layer 13), so that its height is made as low as possible. be able to. This means that the metal wires 56A, 56B, and 56C connected to the first to third semiconductor elements 1A, 1B, and 1C can be reduced in thickness necessary for embedding, and the fourth semiconductor in the uppermost stage. This means that the resin sealing thickness of the metal wire 56D connected to the element 1D can be reduced.

スペーサ層として機能させる絶縁性接着剤層１３の厚さは、ループ高さを維持する必要があった従来装置の金属ワイヤを埋め込む場合に比べて薄くすることができる。具体的には、スペーサ層として機能する絶縁性接着剤層１３の厚さは６０μｍ以下とすることができる。ただし、あまり薄くしすぎるとスペーサ層としての機能が低下するため、絶縁性接着剤層１３の厚さは３０μｍ以上とすることが好ましい。さらに、第１ないし第４の半導体素子１Ａ〜１Ｄを金属ワイヤ５６Ａ〜５６Ｄと共に封止する樹脂封止部５７の厚さを薄くすることができる。従って、複数の半導体素子１を積層して搭載した半導体パッケージ５１の小型・薄型化、さらに高歩留化や高信頼性化等を実現することが可能となる。   The thickness of the insulating adhesive layer 13 that functions as the spacer layer can be made thinner than the case of embedding the metal wire of the conventional device that needs to maintain the loop height. Specifically, the thickness of the insulating adhesive layer 13 that functions as a spacer layer can be 60 μm or less. However, if the thickness is too thin, the function as the spacer layer is lowered. Therefore, the thickness of the insulating adhesive layer 13 is preferably 30 μm or more. Furthermore, the thickness of the resin sealing portion 57 that seals the first to fourth semiconductor elements 1A to 1D together with the metal wires 56A to 56D can be reduced. Therefore, it is possible to realize a reduction in size and thickness of the semiconductor package 51 on which a plurality of semiconductor elements 1 are stacked and mounted, and a higher yield and higher reliability.

この実施形態の半導体パッケージ５１は、例えば以下のようにして作製される。まず、図１３Ａに示すように、回路基板５２上に第１の半導体素子１Ａを接着する。第１の半導体素子１Ａはその裏面に設けられた絶縁性接着剤層１３を介して回路基板５２と接着される。続いて、回路基板５２の接続パッド５４と第１の半導体素子１Ａの電極パッド３Ａとを第１の金属ワイヤ５６Ａで電気的に接続する。次いで、図１３Ｂに示すように、第１の半導体素子１Ａ上に第２の半導体素子１Ｂを接着する。第２の半導体素子１Ｂはその裏面に設けられた絶縁性接着剤層１３を介して第１の半導体素子１Ａと接着される。   The semiconductor package 51 of this embodiment is manufactured as follows, for example. First, as shown in FIG. 13A, the first semiconductor element 1 </ b> A is bonded onto the circuit board 52. The first semiconductor element 1A is bonded to the circuit board 52 via the insulating adhesive layer 13 provided on the back surface thereof. Subsequently, the connection pads 54 of the circuit board 52 and the electrode pads 3A of the first semiconductor element 1A are electrically connected by the first metal wires 56A. Next, as shown in FIG. 13B, the second semiconductor element 1B is bonded onto the first semiconductor element 1A. The second semiconductor element 1B is bonded to the first semiconductor element 1A via an insulating adhesive layer 13 provided on the back surface thereof.

この際、第１の半導体素子１Ａに接続された第１の金属ワイヤ５６Ａの素子側端部は、接着工程時に軟化もしくは溶融した第２の半導体素子１Ｂの絶縁性接着剤層１３内に埋め込まれる。第１の金属ワイヤ５６Ａは第２の半導体素子１Ｂを接着する際の圧力で、第１の半導体素子１Ａの表面と接触しつつ、第２の半導体素子１Ｂの絶縁性接着剤層１３内に埋め込まれる。同様にして、第２の金属ワイヤ５６Ｂの接続、第３および第４の半導体素子１Ｃ、１Ｄの接着、および第３および第４の金属ワイヤ５６Ｃ、５６Ｄの接続を実施する。この後、樹脂封止工程や外部接続端子の形成工程を経ることによって、小型・薄型で信頼性に優れた半導体パッケージ５１が作製される。   At this time, the element side end portion of the first metal wire 56A connected to the first semiconductor element 1A is embedded in the insulating adhesive layer 13 of the second semiconductor element 1B softened or melted during the bonding process. . The first metal wire 56A is embedded in the insulating adhesive layer 13 of the second semiconductor element 1B while being in contact with the surface of the first semiconductor element 1A at the pressure when bonding the second semiconductor element 1B. It is. Similarly, connection of the second metal wire 56B, adhesion of the third and fourth semiconductor elements 1C and 1D, and connection of the third and fourth metal wires 56C and 56D are performed. Thereafter, through a resin sealing process and an external connection terminal forming process, a small and thin semiconductor package 51 with excellent reliability is manufactured.

なお、本発明は上記した各実施形態に限定されるものではなく、積層して回路基材上に搭載される各種構造の半導体素子、さらに回路基材上に複数の半導体素子を積層して搭載した各種構造の半導体パッケージに適用することができる。そのような半導体素子や半導体パッケージについても、本発明に含まれるものである。本発明の実施形態は本発明の技術的思想の範囲内で拡張もしくは変更することができ、この拡張、変更した実施形態も本発明の技術的範囲に含まれるものである。   The present invention is not limited to the above-described embodiments, and semiconductor elements having various structures that are stacked and mounted on a circuit substrate, and further, a plurality of semiconductor elements are stacked and mounted on the circuit substrate. The present invention can be applied to semiconductor packages having various structures. Such semiconductor elements and semiconductor packages are also included in the present invention. Embodiments of the present invention can be expanded or modified within the scope of the technical idea of the present invention, and these expanded and modified embodiments are also included in the technical scope of the present invention.

本発明の実施形態による半導体素子を示す断面図である。It is sectional drawing which shows the semiconductor element by embodiment of this invention. 図１に示す半導体素子の一部を拡大して示す断面図である。FIG. 2 is an enlarged sectional view showing a part of the semiconductor element shown in FIG. 1. 図１に示す半導体素子の製造工程における半導体ウェーハのダイシング状態を示す断面図である。It is sectional drawing which shows the dicing state of the semiconductor wafer in the manufacturing process of the semiconductor element shown in FIG. 図１に示す半導体素子の製造工程における半導体ウェーハへの保護テープの貼り付け状態を示す断面図である。It is sectional drawing which shows the affixing state of the protective tape to the semiconductor wafer in the manufacturing process of the semiconductor element shown in FIG. 図１に示す半導体素子の製造工程における半導体ウェーハの裏面研削状態を示す断面図である。It is sectional drawing which shows the back surface grinding state of the semiconductor wafer in the manufacturing process of the semiconductor element shown in FIG. 半導体ウェーハの裏面研削後の状態を示す断面図である。It is sectional drawing which shows the state after the back surface grinding of a semiconductor wafer. 図１に示す半導体素子の製造工程における絶縁性接着剤層の形成工程を示す断面図である。It is sectional drawing which shows the formation process of the insulating adhesive bond layer in the manufacturing process of the semiconductor element shown in FIG. 図１に示す半導体素子の製造工程における絶縁性接着剤層の形成状態を示す断面図である。It is sectional drawing which shows the formation state of the insulating adhesive bond layer in the manufacturing process of the semiconductor element shown in FIG. 絶縁性接着剤層を形成した後の半導体ウェーハの状態を示す断面図である。It is sectional drawing which shows the state of the semiconductor wafer after forming an insulating adhesive bond layer. 図１に示す半導体素子の製造工程における絶縁性接着剤層を切断するためのダイシングテープの貼り付け状態を示す断面図である。It is sectional drawing which shows the affixed state of the dicing tape for cut | disconnecting the insulating adhesive bond layer in the manufacturing process of the semiconductor element shown in FIG. 図１に示す半導体素子の製造工程における絶縁性接着剤層の切断状態を示す断面図である。It is sectional drawing which shows the cutting state of the insulating adhesive bond layer in the manufacturing process of the semiconductor element shown in FIG. 絶縁性接着剤層を切断した後の半導体ウェーハの状態を示す断面図である。It is sectional drawing which shows the state of the semiconductor wafer after cut | disconnecting an insulating adhesive bond layer. 本発明の第１の実施形態による半導体パッケージを示す断面図である。It is sectional drawing which shows the semiconductor package by the 1st Embodiment of this invention. 図９に示す半導体パッケージの変形例を断面図である。FIG. 10 is a cross-sectional view of a modified example of the semiconductor package shown in FIG. 9. 図９に示す半導体パッケージの製造工程における回路基板上に第１の半導体素子を配置した状態を示す図である。It is a figure which shows the state which has arrange | positioned the 1st semiconductor element on the circuit board in the manufacturing process of the semiconductor package shown in FIG. 図９に示す半導体パッケージの製造工程における回路基板上に複数の半導体素子を接着した状態を示す図である。It is a figure which shows the state which adhere | attached the several semiconductor element on the circuit board in the manufacturing process of the semiconductor package shown in FIG. 図９に示す半導体パッケージの製造工程における複数の半導体素子へのワイヤボンディング工程を示す断面図である。It is sectional drawing which shows the wire bonding process to the several semiconductor element in the manufacturing process of the semiconductor package shown in FIG. 本発明の第２の実施形態による半導体パッケージを示す断面図である。It is sectional drawing which shows the semiconductor package by the 2nd Embodiment of this invention. 図１２に示す半導体パッケージの製造工程における回路基板上に接着された第１の半導体素子にワイヤボンディングを実施した状態を示す断面図である。FIG. 13 is a cross-sectional view showing a state in which wire bonding is performed on the first semiconductor element bonded on the circuit board in the manufacturing process of the semiconductor package shown in FIG. 12. 図１２に示す半導体パッケージの製造工程における第１の半導体素子上に第２の半導体素子を接着した状態を示す図である。It is a figure which shows the state which adhere | attached the 2nd semiconductor element on the 1st semiconductor element in the manufacturing process of the semiconductor package shown in FIG.

符号の説明Explanation of symbols

１…半導体素子、２…半導体基板、２ａ…表面、２ｂ…裏面、２ｃ…側面、３…電極パッド、５…素子領域、６…外周領域（ダイシング領域）、７…積層膜、１２…絶縁保護膜、１３…絶縁性接着剤層、４１，５１…半導体パッケージ、４２，５２…回路基板、４４，５４…接続パッド、４５，５５…半導体素子群、４６，５６…金属ワイヤ、４７，５７…樹脂封止部。   DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Semiconductor substrate, 2a ... Front surface, 2b ... Back surface, 2c ... Side surface, 3 ... Electrode pad, 5 ... Element area | region, 6 ... Outer periphery area | region (dicing area | region), 7 ... Laminated film, 12 ... Insulation protection Film, 13 ... Insulating adhesive layer, 41, 51 ... Semiconductor package, 42, 52 ... Circuit board, 44, 54 ... Connection pad, 45, 55 ... Semiconductor element group, 46, 56 ... Metal wire, 47, 57 ... Resin sealing part.

Claims (5)

半導体素子本体と、
前記半導体素子本体の表面に配置された電極パッドと、
前記電極パッドを露出させつつ、前記表面をその外周領域を除いて覆う絶縁保護膜と、
前記半導体素子本体の裏面、側面および前記表面と前記側面との間の角部を少なくとも覆うように形成された絶縁性接着剤層と
を具備することを特徴とする半導体素子。 A semiconductor element body;
An electrode pad disposed on a surface of the semiconductor element body;
An insulating protective film that covers the surface excluding the outer peripheral region while exposing the electrode pad;
A semiconductor element comprising: a back surface, a side surface, and an insulating adhesive layer formed to cover at least a corner portion between the front surface and the side surface of the semiconductor element body. 請求項１記載の半導体素子において、
前記絶縁性接着剤層は前記絶縁保護膜で覆われていない前記表面の外周領域まで覆うように形成されていることを特徴とする半導体素子。 The semiconductor device according to claim 1,
The semiconductor element, wherein the insulating adhesive layer is formed so as to cover an outer peripheral region of the surface that is not covered with the insulating protective film. 請求項１または請求項２記載の半導体素子において、
前記絶縁性接着剤層は半硬化状態の熱硬化性絶縁樹脂層を備えることを特徴とする半導体素子。 The semiconductor device according to claim 1 or 2,
The insulating adhesive layer includes a semi-cured thermosetting insulating resin layer. 素子搭載部と接続部とを有する回路基材と、
前記回路基材の前記素子搭載部上に積層されて搭載された、請求項１ないし請求項３のいずれか１項記載の半導体素子を複数備える半導体素子群であって、前記複数の半導体素子は前記絶縁性接着剤層を介して接着されている半導体素子群と、
前記回路基材の前記接続部と前記複数の半導体素子の前記電極パッドとを電気的に接続する接続部材と、
前記複数の半導体素子を前記接続部材と共に封止する封止部と
を具備することを特徴とする半導体パッケージ。 A circuit substrate having an element mounting portion and a connection portion;
4. A semiconductor element group comprising a plurality of semiconductor elements according to claim 1, wherein the plurality of semiconductor elements are stacked and mounted on the element mounting portion of the circuit substrate. A group of semiconductor elements bonded via the insulating adhesive layer;
A connection member for electrically connecting the connection portion of the circuit substrate and the electrode pads of the plurality of semiconductor elements;
A semiconductor package comprising: a sealing portion that seals the plurality of semiconductor elements together with the connection member. 請求項４記載の半導体パッケージにおいて、
前記複数の半導体素子は前記電極パッドを露出させるように階段状に積層されていることを特徴とする半導体パッケージ。 The semiconductor package according to claim 4, wherein
The semiconductor package, wherein the plurality of semiconductor elements are stacked stepwise so as to expose the electrode pads.
JP2007212712A 2007-08-17 2007-08-17 Semiconductor device and semiconductor package using the same Expired - Fee Related JP4496241B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007212712A JP4496241B2 (en) 2007-08-17 2007-08-17 Semiconductor device and semiconductor package using the same
US12/191,574 US7911045B2 (en) 2007-08-17 2008-08-14 Semiconductor element and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007212712A JP4496241B2 (en) 2007-08-17 2007-08-17 Semiconductor device and semiconductor package using the same

Publications (2)

Publication Number Publication Date
JP2009049118A true JP2009049118A (en) 2009-03-05
JP4496241B2 JP4496241B2 (en) 2010-07-07

Family

ID=40501086

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007212712A Expired - Fee Related JP4496241B2 (en) 2007-08-17 2007-08-17 Semiconductor device and semiconductor package using the same

Country Status (1)

Country Link
JP (1) JP4496241B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009099922A (en) * 2007-10-16 2009-05-07 Hynix Semiconductor Inc Laminated semiconductor package, and manufacturing method thereof
WO2011162488A2 (en) * 2010-06-22 2011-12-29 하나마이크론㈜ Layered semiconductor package
JP2012186295A (en) * 2011-03-04 2012-09-27 Toshiba Corp Layered semiconductor device manufacturing method
KR20130091624A (en) 2012-02-08 2013-08-19 가부시키가이샤 제이디바이스 Semiconductor device and manufacturing method thereof
US8749031B2 (en) 2010-09-01 2014-06-10 Kabushiki Kaisha Toshiba Semiconductor device, method for manufacturing same, and semiconductor apparatus
CN112997308A (en) * 2018-11-12 2021-06-18 三菱电机株式会社 Semiconductor device and method for manufacturing semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04302164A (en) * 1991-03-29 1992-10-26 Fujitsu Ltd Semiconductor device
JPH11219962A (en) * 1998-01-30 1999-08-10 Hitachi Chem Co Ltd Manufacture of semiconductor device
JP2001168132A (en) * 1999-12-08 2001-06-22 Rohm Co Ltd Semiconductor electronic part
JP2004253422A (en) * 2003-02-18 2004-09-09 Renesas Technology Corp Semiconductor device
JP2007194491A (en) * 2006-01-20 2007-08-02 Renesas Technology Corp Semiconductor device, manufacturing method thereof, and interposer chip

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04302164A (en) * 1991-03-29 1992-10-26 Fujitsu Ltd Semiconductor device
JPH11219962A (en) * 1998-01-30 1999-08-10 Hitachi Chem Co Ltd Manufacture of semiconductor device
JP2001168132A (en) * 1999-12-08 2001-06-22 Rohm Co Ltd Semiconductor electronic part
JP2004253422A (en) * 2003-02-18 2004-09-09 Renesas Technology Corp Semiconductor device
JP2007194491A (en) * 2006-01-20 2007-08-02 Renesas Technology Corp Semiconductor device, manufacturing method thereof, and interposer chip

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009099922A (en) * 2007-10-16 2009-05-07 Hynix Semiconductor Inc Laminated semiconductor package, and manufacturing method thereof
WO2011162488A2 (en) * 2010-06-22 2011-12-29 하나마이크론㈜ Layered semiconductor package
WO2011162488A3 (en) * 2010-06-22 2012-04-12 하나마이크론㈜ Layered semiconductor package
US8749031B2 (en) 2010-09-01 2014-06-10 Kabushiki Kaisha Toshiba Semiconductor device, method for manufacturing same, and semiconductor apparatus
JP2012186295A (en) * 2011-03-04 2012-09-27 Toshiba Corp Layered semiconductor device manufacturing method
KR20130091624A (en) 2012-02-08 2013-08-19 가부시키가이샤 제이디바이스 Semiconductor device and manufacturing method thereof
EP2634796A2 (en) 2012-02-08 2013-09-04 J-Devices Corporation Semiconductor device and manufacturing method thereof
US8872350B2 (en) 2012-02-08 2014-10-28 J-Devices Corporation Semiconductor device and manufacturing method thereof
CN112997308A (en) * 2018-11-12 2021-06-18 三菱电机株式会社 Semiconductor device and method for manufacturing semiconductor device
CN112997308B (en) * 2018-11-12 2023-10-31 三菱电机株式会社 Semiconductor device and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JP4496241B2 (en) 2010-07-07

Similar Documents

Publication Publication Date Title
US7911045B2 (en) Semiconductor element and semiconductor device
US8941246B2 (en) Semiconductor device and manufacturing method thereof
TWI567897B (en) Thin fan-out stacked chip package and its manufacturing method
JP4998268B2 (en) Semiconductor device and manufacturing method thereof
KR100401020B1 (en) Stacking structure of semiconductor chip and semiconductor package using it
JP5280014B2 (en) Semiconductor device and manufacturing method thereof
TWI724744B (en) Semiconductor device and manufacturing method of semiconductor device
JP2015176906A (en) Semiconductor device and method of manufacturing the same
TWI240399B (en) Chip package structure and process for fabricating the same
JP2005183923A (en) Semiconductor device and its manufacturing method
KR20050119414A (en) Stacked package comprising two edge pad-type semiconductor chips and method of manufacturing the same
JP2004312008A (en) Semiconductor multi-chip package and manufacturing method therefor
JP2009044110A (en) Semiconductor device and its manufacturing method
KR20200024499A (en) Stack package include bridge die
JP2015177061A (en) Semiconductor device manufacturing method and semiconductor device
JP2016062995A (en) Semiconductor device and method of manufacturing semiconductor device
JP2011003715A (en) Semiconductor device
JP4496241B2 (en) Semiconductor device and semiconductor package using the same
JP2007242684A (en) Laminated semiconductor device and laminating method of device
JP4435187B2 (en) Multilayer semiconductor device
JP2012009713A (en) Semiconductor package and method of manufacturing the same
JP4602223B2 (en) Semiconductor device and semiconductor package using the same
JP2007214238A (en) Semiconductor device and its manufacturing method
US7968993B2 (en) Stacked semiconductor device and semiconductor memory device
JP2005167286A (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090806

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20091218

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20091222

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100222

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20100222

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100316

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100412

R151 Written notification of patent or utility model registration

Ref document number: 4496241

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130416

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140416

Year of fee payment: 4

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees