JP2000340741A - Manufacturing method and device of multi-chip module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and a device for manufacturing a multi-chip module, which is capable of carrying out a processing operation at a high speed and where inter-chip wirings are made micronized, and the circuit patterns of built-in semiconductor chips are aligned and arranged with high accuracy. SOLUTION: In a method of manufacturing a multi-chip module, composed of semiconductor chips which are electrically connected together and mounted on a support board 4, a process where the heights of the semiconductor chips are measured in advance, and pads 1a are formed on the support board 4 corresponding to the measured heights and another process, where the surface circuit patterns of the semiconductor chips are recognized by their images, and the semiconductor chips are aligned at prescribed positions and mounted on the pads 1a on the support board, on the basis of the data for the surface circuit patterns recognized by the images.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method and an apparatus for manufacturing a multichip module. More specifically, the present invention relates to a method and an apparatus for manufacturing a multi-chip module which is miniaturized by miniaturization of wiring.

[0002]

2. Description of the Related Art In order to meet the demands for electrical products and electronic devices such as small size, light weight and low power consumption, mounting technology for assembling these semiconductor devices at high density has been developed together with technology for manufacturing highly integrated semiconductor devices. I have.

In order to realize higher-density mounting, a multi-chip module (hereinafter referred to as MCM) has been developed in which a plurality of semiconductor elements are pre-assembled and mounted as one electronic component in addition to a multilayer wiring board or bare chip mounting.
This MCM includes a plurality of individually manufactured semiconductor elements,
They are electrically connected on a supporting substrate to achieve a desired function, and are made into one electronic component. Such an MCM is expected to operate at a high speed by shortening the distance between elements in addition to reducing the mounting area.

As one of the methods for manufacturing such an MCM, there is a method in which an LSI chip is mounted face-down on a multilayer wiring board formed in advance. In this method, a method of using a Si (silicon) wafer as a supporting substrate and utilizing a wafer process to facilitate formation of fine wiring has been put to practical use.

On the other hand, as a method of shortening the wiring distance between elements by using an MCM in which an LSI chip is mounted face-up, after mounting the elements on a supporting substrate, a plurality of polyimide films are coated to form a flattened insulating layer. A technique has been proposed in which the wiring is formed and a wiring connecting the elements is formed thereon (Japanese Patent Application Laid-Open No. 5-47856). In addition, an MCM using an inner via hole has been developed in order to multi-layer the inter-element wiring.

Japanese Patent Application Laid-Open Nos. 7-202115 and 9-260581 disclose a method of mounting a chip on a jig plate and then transferring irregularities on a resin film to cancel a variation in chip thickness. Has been proposed.

[0007]

However, in the above-described method of mounting the LSI chip face down, there is a problem in the alignment accuracy for aligning the chip circuit position with the wiring of the support substrate, and it is difficult to improve the mounting density.

In the case of a method in which multilayer wiring is formed on a chip mounted face-up, a step due to a variation in the thickness of the element becomes a major obstacle. In other words, there is a possibility that patterning mask formation failure or disconnection may occur due to a step.

The above-mentioned publication describes a method of shaving a chip mount portion of a support substrate and embedding a chip in the support substrate. However, a chip thickness of several tens μm due to a variation in a BGR process on a chip surface or a back surface of the substrate. However, there is a problem that variation in the size remains.

The method for canceling the variation in the chip thickness according to the above publications is excellent in that the height can be adjusted according to the mounted chip. However, since the chip is temporarily mounted face down on the jig plate, The accuracy of the circuit pattern interval (position) of the chip is deteriorated. This hinders lithographic patterning of the interchip interconnect.

In the above-mentioned publication, a method is proposed in which a connection hole is largely opened to absorb a chip displacement, but this method hinders miniaturization of wiring.

Further, the above publication proposes a method of mounting a chip on a jig plate, forming a concave portion corresponding to the thickness of the resin film, and mounting the chip in the concave portion in a face-up state. I have. In this method, the height is adjusted according to the mounted chip, and after checking the circuit pattern of each chip, mounting is performed to improve the positional accuracy.
However, since the chip is mounted in the concave portion corresponding to the position temporarily mounted on the jig plate face down, there is a problem that the actual positional accuracy is not improved.

On the other hand, the present inventors have already proposed to connect the chips without passing through the input / output interface circuit to reduce the size and the performance of the MCM.
Since this requires thousands of wires, a technology for forming fine wires is naturally required. However, in the above-described conventional technology, the relative positional deviation between the chip circuits is large, and the number of laminations needs to be increased several times.
High-speed operability obtained only by reducing the wiring length is reduced.

In view of this point, the present inventors have already proposed a method of controlling the position and height of a circuit pattern for each chip and fixing the circuit pattern with a photocurable resin. However, this method has a problem that although high mounting accuracy is obtained, the processing speed is slow.

The present invention has been made in consideration of the above-mentioned prior art, and has a structure in which the wiring between chips is miniaturized (for example, wiring of 2 μm or less), and the circuit pattern position of a semiconductor chip to be incorporated is adjusted with high accuracy and arranged. Another object of the present invention is to provide a method and an apparatus for manufacturing an MCM having a high processing speed.

[0016]

According to the present invention, there is provided a method of manufacturing a multi-chip module having a plurality of semiconductor chips electrically connected to a support substrate, the method comprising: Measuring the height of the semiconductor chip, forming a pedestal corresponding to the height on the support substrate, and image-recognizing the surface circuit pattern of the semiconductor chip, based on the data of the image-recognized surface circuit pattern. A method of manufacturing a multi-chip module, comprising: positioning each semiconductor chip at a predetermined position on the support substrate and mounting the semiconductor chip on the pedestal.

According to this configuration, by adjusting the position and height of the wiring pattern for each chip (semiconductor chip), the uppermost wiring surface of each chip can be aligned on the same plane, and the same MCM can be used. The relative positional accuracy between the chips to be incorporated is improved. Furthermore, since the chip mounting base can be mass-produced based on data measured in advance, productivity is improved. According to the method of the present invention, it is possible to mass-produce an MCM having a fine wiring structure in which the wiring between chips is reduced to 2 μm or less. In addition, the number of wirings that can be formed is dramatically increased due to miniaturization, and it becomes possible to manufacture an MCM that connects wirings between chips without passing through input / output circuits.

In the present invention, the formation of the height-adjusted pedestal and the position control of the circuit pattern of the chip are preferably performed according to the following flow.

(1) An LSI chip is placed on a surface plate, and an accurate thickness of each chip is measured by optical measurement.

(2) The arrangement of each chip in the MCM and the arrangement of the MCM formation region on the support substrate are determined, and a mount position map of each chip in the support substrate is created from the arrangement data.

(3) A target mark serving as a mount reference is imprinted on the support substrate, and a photocurable resin is coated.

(4) The resin in the mounting area of each chip is exposed and cured with an exposure amount corresponding to the chip thickness.

(5) After the exposure of the mount areas of all the chips is completed, a developing process is performed using a developing solution whose dissolution rate changes depending on the curing level, and a convex pattern (pedestal) having a height corresponding to the exposure amount is formed.

(6) The resin pedestal is completely cured by overall exposure or heating.

(7) A thin film having high thermal conductivity (low resistance) is deposited on the support substrate after the pedestal is formed, and is used as a part of a heat dissipation plate of the chip or a part of a potential fixing electrode of the chip substrate.

(8) A highly heat-conductive (conductive) adhesive is applied to the supporting substrate.

(9) The representative image of the circuit pattern of each chip is registered, the circuit pattern of the chip to be mounted is optically recognized, and this is compared with the registered image to accurately determine the position of the chip circuit as a reference point. To fit.

(10) The target mark reference point of the support substrate is moved to a preset relative position with respect to the circuit pattern reference point, and the chip is bonded to the pedestal by raising the support substrate stage to a certain height.

According to the above flow, the chip can be mounted on the support substrate in a state where the position and the height of the circuit pattern of the LSI chip are accurately aligned. Also, since a pedestal for correcting the chip height can be manufactured in advance,
The productivity is improved as compared with the method of fixing each chip.

Further, by utilizing the present invention, the relative positional accuracy of each circuit is improved, and the heights are aligned on the same plane.
Wiring between chips can be formed by a method similar to the process of manufacturing an SI chip. For example, if an i-line exposure apparatus is used to form the wiring between chips, 0.5 μm line / 0.5 μm S
A wiring of space can also be formed.

In a preferred configuration example, the support substrate is coated with a photocurable resin, and a pedestal pattern is printed on the photocurable resin with an exposure amount corresponding to the height data of the semiconductor chip. Are formed to cancel out variations in chip height.

According to this configuration, since the height is adjusted for each chip, the variation in the height of the chips is corrected, and the circuit forming surface is aligned on the same surface.

In a further preferred embodiment, the pedestal is
It is characterized in that each chip has a plurality of support points.

According to this structure, even if the edge is rounded in the process of forming the pedestal, the chip is supported horizontally without being inclined by dividing the pedestal into a plurality of support points.

In a further preferred configuration example, after forming the pedestal on the support substrate, a thin film having at least one of high thermal conductivity and high electrical conductivity is deposited, and the semiconductor chip is mounted thereon. Features.

According to this structure, it has a high thermal conductivity such that heat generated by the chip can be effectively conducted and emitted to the outside,
By coating a thin film such as copper (Cu) or silver (Ag) having conductivity enough to become a potential fixing electrode of the chip, when the support substrate is made of a dielectric material having low thermal conductivity, The heat generation of the chip is effectively escaped to improve the reliability of the function of the chip, and it is not necessary to provide a potential fixing electrode on the upper surface of the chip, so that an electrode space can be saved.

According to the present invention, there is further provided an apparatus for manufacturing a multi-chip module in which a plurality of semiconductor chips electrically connected to each other are mounted on a support substrate, wherein each semiconductor chip is mounted on the support substrate at a position where the semiconductor chips are mounted. A pedestal forming apparatus for forming a pedestal according to the height of the semiconductor chip, and image-recognizing the surface circuit pattern of the semiconductor chip. A multi-chip module manufacturing apparatus, comprising: a chip mounting device that is mounted on the pedestal while being positioned at a predetermined position.

According to this configuration, the above-described method of the present invention can be properly performed. In this case, the pedestal forming device and the chip mount device may be provided integrally, or may be used in combination with those separately provided.

In a preferred configuration example, the pedestal forming apparatus includes a coater section for coating a photocurable resin, and an exposure section for exposing a semiconductor chip mounting area of the support substrate with an exposure amount corresponding to the height of each semiconductor chip. A chip image capturing optical system for imaging a surface circuit pattern of a semiconductor chip, a mark position detecting optical system for detecting an alignment mark of the semiconductor chip, and the support substrate. XY direction and Z
A stage capable of adjusting the position in the direction, a support substrate transfer system for transferring the support substrate to the stage, and a chip transfer system for transferring the semiconductor chip onto the support substrate on the stage.

According to this configuration, the support substrate is coated with the photocurable resin in the coater section of the pedestal forming apparatus, and this is exposed in the exposure section to form a pedestal pattern by photolithography. The support substrate on which the pedestal pattern is formed is transferred to a chip mount device, and transferred to a stage by a support substrate transfer system. Each MCM formation region of the support substrate on the stage is detected from the image data of the alignment mark, aligned to a predetermined position, and the chip is mounted.

[0041]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 1A and 1B are a plan view of a supporting substrate and a configuration diagram of each MCM, respectively, showing an arrangement pattern of MCMs according to a first embodiment of the present invention.
This embodiment is an MCM in which a memory and a signal processing logic LSI are combined.

A 32-Mbit DRAM chip 1, a signal processing LSI chip 2, and an optical disk reading LSI chip 3 manufactured by a known technique are separated by chip type and BGR.
Group by processing lot.

Ten chips are taken out of each group, and the thickness of the BGR-finished chips is measured on the surface plate with an optical step meter. The average thickness of the ten chips is registered as the chip thickness of the group.

The DRAM chip 1, the signal processing LS
I chip 2 and optical disk reading LSI chip 3
How to arrange as CM and individual unit MCM
Is input to the pedestal forming apparatus, and the mounting position and array pattern are determined for each chip. Thereby, FIG. 1 (A)
As shown in FIG. 3, data of a pattern in which a plurality of MCMs 5 are arranged on a support substrate 4 made of, for example, a 200 mm quartz wafer, and position data of a DRAM chip 1, a signal processing LSI chip 2 and an optical disk reading LSI chip 3 in each MCM 5 The position data of the target mark 6 is input.

From these data, a mount map of the position, arrangement and dimensions is prepared for each chip type, and is input to the pedestal forming apparatus together with the thickness data of the chip group to be mounted.

FIGS. 2A to 2C are cross-sectional views of the substrate showing the procedure for preparing the chip mount on the support substrate in order. Step a (FIG. 2 (a) photoresist patterning): First, as shown in FIG. 2 (a), a MC is formed on a support substrate (quartz wafer) 4 by photolithography.
A resist pattern mask 7 having a pattern opening 7a for a target mark 6 (FIG. 1) serving as a reference for the M formation region is formed.

Step b (FIG. 2 (b) dry etching): Next, as shown in FIG. 2 (b), the target mark 6 is engraved on the support substrate 4 by fluorine-based dry etching using a resist as a mask to form a stamp. .

Step c (FIG. 2C, photocurable resin coating): Next, the resist is removed, and
As shown in (c), the UV (ultraviolet) curable resin film 8 (for example, a mixture of diallyl phthalate, polyfunctional acrylate, and photopolymerization initiator) is coated with a coating material of 350 μm.
m and a preliminary drying. After the coating is completed, the support substrate (quartz wafer) 4 is carried into the pedestal forming apparatus, and the pedestal is formed according to the following flow.

FIGS. 3A to 3D are cross-sectional views of the substrate showing the flow of the pedestal forming process in order. Step a (FIG. 3 (a) support substrate alignment): First, as shown in FIG. 3 (a), the target mark 6 on the support substrate 4 is read by the laser beam 10 of the position detecting device.
The position of the support substrate 4 is adjusted to the reference point. Furthermore, DRAM
In accordance with the chip mount map, a stage (not shown) on which the support substrate 4 is mounted is moved so that one of the DRAM chip formation regions is located at a predetermined position under the exposure optical system.

Step b (FIG. 3 (b) chip pedestal area resin curing): Next, the target mark 6 is read again,
From the relative position data with the target mark 6, the DRA
The M pedestal region 1a is determined, and U
UV light 11 is radiated by the V exposure optical system 9 and the DRA
Exposure is performed only on the M pedestal region 1a (FIG. 3B). At this time, the exposure amount is an exposure amount according to the thickness of the DRAM chip group to be mounted this time.

Step c (FIG. 3 (c) curing of all types of chip pedestal areas): Further, according to the mount map, the following D
The stage is moved so that the RAM pedestal area is aligned with a predetermined position of the exposure optical system 9, and the support substrate 4 is aligned.
Similarly, UV exposure is performed to expose all the DRAM pedestal regions 1a.

Subsequently, the signal processing LSI pedestal area 2a and the optical disc reading LSI pedestal area (not shown) are exposed in the same manner (FIG. 3C). Step d (FIG. 3D: pedestal pattern formation by development processing): When all the exposures are completed, the support substrate 4 is moved to a developing device, and the UV-cured resin film 8 in the unexposed areas is removed with a developing solution. At this time, since each pedestal portion has a different dissolution rate with respect to the developing solution according to the exposure amount, the pedestal pattern 12 for the DRAM, the pedestal pattern 13 for the signal processing LSI, and the pedestal pattern for the LSI for reading the optical disk have a height corresponding to the exposure amount. (Not shown) remain (FIG. 3D).

Thereafter, the support substrate 4 is transferred to a full-surface exposure apparatus, and is exposed to a mercury lamp at 400 W for 2 minutes.
The resin of the pedestal pattern is completely cured. FIG. 4 is a top view illustrating a configuration of a pedestal forming apparatus that performs the above-described series of pedestal forming operations. This apparatus has the same configuration as that of a coater developer / stepper connected in-line and used in semiconductor manufacturing, and includes a coater unit 14 and an exposure unit 15.

The support substrate (quartz wafer) conveyed from the cassette is subjected to a photo-curing resin coating process and a preliminary drying process in a coater unit 14, and is subjected to a position correction and exposure process (a pedestal resin curing for each chip) in an exposure unit 15. Processing) is performed. Thereafter, the support substrate is again transported to the coater unit 14, where the support substrate is subjected to a development process, and the resin remaining on the overall exposure stage 16 is further cured, and then returned to the cassette.

The coater unit 14 includes four cassettes 1
The cassette 7 can be accommodated in a cassette loader 18, and a support substrate in the cassette is carried to an arm robot 20 via an interface buffer 19. This arm robot 2
0 moves in the center of the coater section 14, and a resin coating cup 21 and a developing cup 22 are arranged on one side of the moving area, and a bake stage 23 for preliminary drying and A stage 16 is provided. Between the coater section 14 and the exposure section 15,
An interface buffer 24 is provided so that a support substrate can be transferred between the coater unit 14 and the exposure unit 15.

FIG. 5 is a side view showing the structure of the exposure unit 15. The exposure unit 15 includes a mercury lamp 25, and includes a support substrate transport system 26, a high-precision support substrate stage 27, a substrate stage drive system 28, and a UV exposure optical system 29 (the UV exposure optical system 29 in FIG. 3).
An exposure optical system 9) and a mark position detecting laser optical system 30 for detecting a target mark on the support substrate. The UV exposure optical system 29 includes a blind shutter 31 for limiting the exposure area, and limits the exposure area to a chip size or less based on the outer diameter data of the chip to be mounted. With the pedestal forming apparatus including the exposure unit 15 and the coater unit 14 described above, a series of steps from coating of the photocurable resin on the support substrate to position correction and exposure (curing of the chip pedestal region resin), development, and final resin curing. Pedestal forming process can be performed continuously.

On the surface of the support substrate on which the pedestal has been formed, a Cu film is deposited to a thickness of 1 μm by sputtering, and a conductive adhesive is coated thereon. A support substrate that has been subjected to this processing and an LSI chip (DRAM chip,
Signal processing LSI chip and LSI for reading optical disk
Chip) is set on a mounting device, and each chip is mounted and fixed according to the following flow.

FIGS. 6 (a) to 6 (c) and FIG. 7 (d)
(E) is an explanatory view sequentially showing a flow of a chip mounting process. Step a (FIG. 6 (a) chip circuit image capture): First, as shown in FIG. 6 (a), a DRAM chip 32 roughly aligned from the outer shape is supported on a support substrate (quartz wafer).
The chip is conveyed to the vicinity of the mount reference point 33 set on the stage No. 4, and the circuit pattern image of the chip 32 is taken in by the image recognition optical system of the mount device. On the support substrate 4, the above-described DRAM pedestal 1a is formed, and the Cu film 35 is formed.
Is coated. The DRAM 32 has a chip reference point 36.

Step b (FIG. 6 (b) Chip height adjustment by focus correction): Next, as shown in FIG. 6 (b), the captured image is focused on the chip height, and the chip height is set as a reference. Align with the plane of point 36. In this state, the reference point is determined by comparing with the registered image. Step c (horizontal position correction of chip reference point in FIG. 6C): Next, as shown in FIG. 6C, the horizontal position of the chip is corrected so that the mount reference point 33 and the chip reference point 36 coincide. I do.

Subsequently, the stage of the support substrate is moved, and the support substrate is moved so that the target mark 6 comes near the mount reference point 33.

Step d (FIG. 7 (d) Support substrate position correction): Here, as shown in FIG. 7 (d), the position of the target mark 6 is detected by the laser beam 37, and the set mount reference point 33 is set. The position of the support substrate is corrected such that the target mark 6 comes to a relative position with respect to.

Step e (FIG. 7 (e) Bonding of Chip by Raising Supporting Substrate): In this state, as shown in FIG.
2 is adhered to the pedestal 1a at the planned mounting position.

By repeating the above steps (a) to (e), all the DRAM chips, the signal processing LSI chips and the optical disk reading LSI chips are joined and fixed on the support substrate.

FIG. 8 is an explanatory diagram comparing a conventional height correction method using concave embedding (FIG. A) and a height correction method using a pedestal (FIG. B). As described above, by mounting the chip by the method using the pedestal of the present invention, only the lower surface of the chip is in contact with the pedestal, so that the chip can be positioned horizontally like a concave height correction film formed by a conventionally known chip. Is not limited to the concave shape, and the circuit position can be corrected at the time of mounting.

That is, as shown in FIG.
The concave pattern 38 for height correction for embedding the chip 39 on which the circuit pattern 41 is formed is embedded in the buried film 40 on the support substrate side.
Therefore, the horizontal movement for correcting the positional deviation B of the circuit pattern 41 could not be performed. In contrast,
In the present invention, as shown in FIG.
Before fixing the chip 39 on the pedestal 2,
The position can be corrected by moving horizontally relative to 2.

FIG. 9 is a configuration diagram of a chip mount device for performing the above-described series of pedestal forming operations. The chip mount device 43 transfers the support substrates one by one onto a substrate support stage 45 in a mount section 53 by a support substrate transport system 44 from a support substrate cassette 52 installed on a cassette stage 51. The chip to be mounted on the support substrate is housed in a chip storage 54, transported into a mount section 53 by a chip transport system 47, and mounted on a support substrate on a stage 45 by a chip mount arm 49. The stage 45 is driven and positioned by the substrate stage drive system 50. Above the stage, a laser optical system 46 for detecting the mark position of the support substrate and a chip image capturing optical system 48 for recognizing an image of a chip circuit pattern are provided.

The support substrate (quartz wafer) conveyed from the cassette 52 is returned to the original cassette 52 after performing position correction and chip bonding by the mount section 53.

After the chip mounting is completed, wiring is formed between the chips according to the following flow in order to function as the MCM. FIGS. 10A to 10D are main-portion cross-sectional views of the support substrate, showing the flow of the inter-chip wiring process.

Step a (FIG. 10A): FIG.
As shown in (a), in order to fill the step between chips, a resin film 55 is coated with a thickness of 500 μm, and flattened and polished by a CMP (chemical mechanical polishing) method until a chip circuit formation surface is exposed. The polishing agent used at this time contains a developer that can have a selectivity with respect to the chip outermost layer film (P-SiN).

After the planarization, a P-TEOS film 56 is deposited to a thickness of 1 μm, a photoresist 58 is coated thereon, and the connection pads of each chip are aligned with a wiring pattern by a photolithography apparatus for a semiconductor pre-process. A hole pattern 57 for connection of 5 μm square is formed on (not shown). In this case, the alignment focus adjustment may be performed for each chip group serving as the MCM or for each chip.

Step b (FIG. 10B): Next, FIG.
As shown in FIG. 0 (b), a connection hole 59 is opened by a drain etching apparatus for processing an insulating film for a semiconductor pre-process, and after removing a mask material (photoresist 58), a photoresist 60 is removed.
And a negative pattern of a 2 μm-wide inter-chip wiring pattern is formed by the same photolithography apparatus, and a wiring pattern groove 61 having a depth of 2 μm is formed by the same dry etching apparatus.

Step c (FIG. 10C): After removing the mask material (photoresist 60), a Cu film is deposited as a growth layer to a thickness of 50 μm by sputtering, and a Cu film is grown to a thickness of 5 μm by electroless plating. Subsequently, the Cu other than the groove is polished and removed by the Cu CMP apparatus to form the first-layer Cu wiring 62 (FIG. 10C).

When the second layer wiring is required, the above (a) to
By repeating the step (c), the second layer is formed on the first layer wiring 62.
A layer wiring is formed. Step d (FIG. 10D): After coating the circuit protection film 64, the protection film is removed only on the pad 65, and the bump 63 is formed on the pad 65 by a known method (FIG. 10D).

By implementing the present invention as described above, the circuit formation surface of each chip can be aligned on the same plane, and the relative positional accuracy between the chips can be improved, whereby the wiring width can be reduced to 2 μm or less. It is possible to form a highly reliable inter-chip wiring. Such a method of the present invention has a point that a pedestal can be manufactured at the time when chip thickness data is obtained in spite of performing height correction according to a mounted chip, and a chip group to be mounted. The production efficiency is excellent in that the pedestal can be manufactured in advance according to the number of chips included.

(Second Embodiment) In this embodiment, a memory and a signal processing theory LS
In the MCM combining I, a pedestal supporting at a plurality of points is used.

A 32-MBit DRAM chip, a signal processing LSI chip, and an optical disk read control LSI chip manufactured by a known technique are grouped for each chip type and for each BGR processing lot. As in the first embodiment, ten chips are taken out of each group, and the BGR-finished chip thickness is measured on the surface plate with an optical step meter. The average thickness of the ten chips is registered as the chip thickness of the group.

Data on how to arrange the chips as MCMs and how to arrange the individual unit MCMs on the support substrate are input to the pedestal forming apparatus, and the mounting position and arrangement for each chip Is determined. From this data, a mount map (position, arrangement, dimensions) is created for each chip type, and input to the pedestal forming apparatus together with the thickness data of the group to be mounted.

A resist pattern mask for a target mark serving as a reference for an MCM formation region is formed on a 200 μm quartz wafer serving as a support substrate by photolithography, and the mark is engraved on the substrate by fluorine-based dry etching. After removing the resist, a UV curable resin film (for example, diallyl phthalate, polyfunctional acrylate,
The photopolymerization initiator mixture) was added to the coating apparatus for 35 times.
Coating with a thickness of 0 μm and predrying. After the coating is completed, the quartz wafer is carried into a pedestal forming apparatus, and a pedestal is formed according to the following flow.

FIGS. 11 (a) to 11 (d) are cross-sectional views of a substrate showing the flow of the process of forming a pedestal for a plurality of dots in order. Step a (FIG. 11 (a) support substrate alignment): First, as shown in FIG. 11 (a), the target mark 6 of the support substrate 4 on which the light (UV) curable resin film 8 is formed is scanned by the laser of the position detecting device. Reading is performed with the light 10 and the position of the support substrate 4 is adjusted to the reference point. Further, the stage (not shown) on which the support substrate 4 is mounted is moved according to the mount map of the DRAM chip so that one of the DRAM chip formation regions is located at a predetermined position under the exposure optical system.

Step b (FIG. 11B: hardening the resin in the chip pedestal area): Next, the target mark 6 is read again, and D is obtained from the relative position data with respect to the target mark 6.
The RAM pedestal area 1a is determined, and UV light 11 is irradiated from the back side of the support substrate 4 by the UV exposure optical system 9 via the reticle mask 66 with a plurality of dots to expose the pedestal area at a plurality of points (FIG. 11). (B)). At this time, the exposure amount is
The exposure amount is set according to the thickness of the DRAM chip group to be mounted this time.

Step c (FIG. 11C: hardening of all types of pedestal areas): The next DRA is further performed according to the mount map.
The stage is moved so that the M pedestal region is aligned with a predetermined position of the exposure optical system 9, the support substrate 4 is aligned, and UV exposure is similarly performed to expose all the DRAM pedestal regions 1a. Subsequently, the signal processing LSI pedestal area 2a and the optical disc reading LSI pedestal area (not shown) are exposed in the same manner (FIG. 11C).

Step d (FIG. 11D: pedestal pattern formation by development processing): When all the exposures are completed, the support substrate 4 is transferred to the developing device, and the UV-cured resin film 8 in the unexposed area is
Is removed with a developer. At this time, since each pedestal has a different dissolving speed with respect to the developing solution according to the exposure amount, the pedestal pattern 67 for DRAM, the pedestal pattern 68 for signal processing LSI, and the optical disk reading pattern, which are composed of a plurality of dots of height corresponding to the exposure amount LSI pedestal pattern (not shown)
Remain (FIG. 11D).

Thereafter, the support substrate 4 is transferred to a full-surface exposure apparatus, and is exposed for 2 minutes at 400 W using a mercury lamp.
The resin of the pedestal pattern is completely cured.

FIG. 12 is an explanatory diagram comparing a single pedestal with a multi-dot pedestal. When the pedestal 69 has a large single pattern as in (A), when the pattern end is rounded and the circuit position correction is large (when the pedestal 69 and the chip 70 are largely displaced), the horizontality of the chip may be deteriorated. is there.
On the other hand, as shown in FIG.
In the case of 1, even if the end of each dot pattern 71a is rounded, the chip 70 is held horizontally to support at multiple points.

FIG. 13 is a structural view of an exposure section of a pedestal forming apparatus for forming a pedestal of a plurality of dots. This exposure unit has a configuration in which the dot opening reticle mask 72 is incorporated in the exposure unit 15 of the first embodiment shown in FIG. The change of the exposure area according to the chip size is performed by the blind shutter 31, as in the first embodiment.

On the surface of the support substrate on which the pedestal has been formed, a Cu film is deposited to a thickness of 1 μm by sputtering, and a conductive adhesive is coated thereon. After that, the support substrate subjected to this processing and the LSI chip (DRAM
Chip, a signal processing LSI chip and an optical disk reading LSI chip) are set in a mounting device, and the first
Each chip is mounted and fixed on a support substrate according to the same flow as in the embodiment. After the chip mounting is completed, in order to function as an MCM, as in the first embodiment,
Form wiring between chips.

(Third Embodiment) In a third embodiment of the present invention, as in the above-described second embodiment, an M is a combination of a memory using a pedestal supported at a plurality of points and a signal processing logic LSI.
In the CM, the height of the support pattern in the chip is corrected to maintain the horizontality of the chip circuit surface with high accuracy.

A 32-bit D manufactured by a known technique
The RAM chip, the signal processing LSI chip and the optical disk reading LSI chip are arranged in the mounting order, and the thickness of four points (at least three points) for each chip is measured on the surface plate. The thickness data of these four points is registered for each chip.

Data on how to arrange each chip as an MCM and how to arrange each unit MCM on a support substrate are input to a pedestal forming apparatus, and the mounting position and arrangement for each chip Is determined. From this data, a mount map (position, arrangement, dimensions) is created for each chip type, and input to the pedestal forming apparatus together with the thickness data of the group to be mounted.

On a 200 μm quartz wafer serving as a support substrate, a resist pattern mask for a target mark serving as a reference for an MCM formation region is formed by photolithography, and the mark is engraved on the substrate by fluorine-based dry etching. After removing the resist, a UV curable resin film (for example, diallyl phthalate, polyfunctional acrylate,
The photopolymerization initiator mixture) was added to the coating apparatus for 35 times.
Coating with a thickness of 0 μm and predrying. After the coating is completed, the quartz wafer is carried into a pedestal forming apparatus, and a pedestal is formed according to the following flow.

FIGS. 14 (a) to (c) and FIG. 15 (d)
(E) is a substrate sectional view showing in order the flow of the pedestal forming process for correcting the in-chip height.

Step a (FIG. 14 (a) Supporting Substrate Alignment): First, as shown in FIG.
V) The target mark 6 of the support substrate 4 on which the cured resin film 8 is formed is read by the laser beam 10 of the position detecting device,
The position of the support substrate 4 is adjusted to the reference point. Furthermore, DRAM
In accordance with the chip mount map, a stage (not shown) on which the support substrate 4 is mounted is moved so that one of the DRAM chip formation regions is located at a predetermined position under the exposure optical system.

Step b (FIG. 14 (b) pedestal area resin curing): Next, the target mark 6 is read again, and the DRAM pedestal area 1a is determined from the relative position data with respect to the target mark 6, and the support substrate 4 UV light 11 is irradiated from the back side by the UV exposure optical system 9 via the single dot aperture reticle mask 73, and one of the regions corresponding to the chip thickness measurement point is exposed (FIG. 14B). At this time,
The exposure amount is an exposure amount corresponding to the thickness of the DRAM chip measurement point to be mounted this time.

Step c (FIG. 14C: curing of all types of pedestal areas): The support substrate stage is moved so that the remaining three measurement point areas of the same chip are sequentially positioned under the exposure optical system, and similarly. Perform exposure. In the drawing, only two pedestal exposure points are shown on one chip.

Next, according to the mount map, the support substrate stage is moved so that the next pedestal forming region is located at the position of the exposure optical system. Subsequently, the pedestal areas of the signal processing LSI chip and the LSI chip for reading an optical disk are exposed in the same manner to expose all the pedestal areas (FIG. 14).
(C)).

Step d (FIG. 15D) formation of a pedestal pattern by development processing): The support substrate on which all the exposure has been completed is transferred to a developing device, and the resin in the unexposed area is removed with a developing solution. At this time, since the dissolution rate of the pedestal portion in the developing solution varies depending on the exposure amount, a pedestal composed of a four-point dot pattern having a height corresponding to the exposure amount remains (FIG. 15D).
Subsequently, the supporting substrate is transferred to a full-surface exposure apparatus, and is exposed to a mercury lamp at 400 W for 2 minutes to completely cure the pedestal pattern resin.

Step e (FIG. 15 (e) chip mount): A Cu film is deposited to a thickness of 1 μm by sputtering on the surface of the support substrate on which the pedestal has been formed, and a conductive adhesive is coated thereon. The support substrate subjected to such processing and the LSI chip (DRAM chip 7
4. The signal processing LSI chip 75 and the optical disk reading LSI chip (not shown) are set in the mounting device, and the chip is mounted and fixed according to the same flow as in the first embodiment.

Thus, the DRAM chip 74, the signal processing LSI chip 75 and the optical disk reading LS
An I chip (not shown) is mounted on pedestals 67 and 68 of four dots (FIG. 15E). in this case,
In the BGR, a chip in which the circuit formation surface and the back surface are not parallel occurs, but according to the method of this embodiment, the thickness of a plurality of points is measured for each chip, and the pedestal is corrected according to the thickness. As a result, the horizontality of the chip circuit surface after mounting is improved. By improving the horizontality in this way, it is possible to improve the processing accuracy of the wiring between chips, and it is possible to arrange finer wirings at high density. The configuration of the device that performs a series of pedestal forming operations is the same as that of the device of the above-described second embodiment. After the mounting of the chip is completed, the wiring between the chips is formed to function as the MCM, as in the first embodiment.

The present invention is not limited to the above embodiments, and a Si substrate, a glass substrate, or another substrate can be used as a support substrate instead of a quartz wafer. However,
The pedestal is formed on the upper surface of the support substrate, and the height of the pedestal is adjusted by the exposure amount from the back surface side of the substrate, so that the substrate is preferably transparent. Further, the chip constituting the MCM is not limited to the above-described LSI and DRAM, and various semiconductor elements can be used.

[0100]

As described above, according to the present invention,
The following effects can be obtained. (1) The position accuracy in the in-plane direction (XY direction) and the height direction (Z direction) of the circuit surface of the LSI chip assembled as the MCM can be improved and prompt position correction processing can be performed. Can be mass-produced in advance,
It is possible to improve the productivity of a small MCM having fine wiring.

(2) Since the chip is mounted after the resin on the lower side of the chip is completely cured, the displacement due to the curing of the resin is less likely to occur, and miniaturization of wiring between chips, multi-line wiring, and miniaturization of the MCM are achieved. Will be possible.

(3) Variations in thickness within a chip can be corrected, thereby further miniaturizing wiring between chips, increasing the number of wires, and reducing the size of the MCM.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an example of an arrangement pattern of an MCM to which the present invention is applied on a supporting substrate.

FIG. 2 is a cross-sectional view of a substrate showing a preparation procedure of a chip mount in order.

FIGS. 3A and 3B are cross-sectional views of a substrate sequentially showing a pedestal forming flow according to the first embodiment.

FIG. 4 is a configuration diagram of a pedestal forming apparatus.

FIG. 5 is a configuration diagram of an exposure unit of the pedestal forming apparatus of FIG.

FIG. 6 is an explanatory diagram showing the flow of chip mounting in order.

FIG. 7 is an explanatory view showing the flow following FIG. 6 in order.

FIG. 8 is a comparative explanatory diagram of a chip position correction method.

FIG. 9 is a configuration diagram of a chip mount device.

FIG. 10 is an explanatory view sequentially showing a flow of forming an inter-chip wiring.

FIG. 11 is an explanatory view sequentially showing a pedestal forming flow of the second embodiment.

FIG. 12 is an explanatory diagram of a chip horizontality on a pedestal.

FIG. 13 is a configuration diagram of an exposure unit of the multi-dot pedestal forming apparatus.

FIG. 14 is an explanatory view sequentially showing a pedestal forming flow of the third embodiment.

FIG. 15 is an explanatory diagram showing the flow following FIG. 14 in order;

[Explanation of symbols]

1: DRAM chip, 2: signal processing LSI chip, 3:
Optical disk reading LSI chip, 4: support substrate, 5: M
CM, 6: target mark, 7: resist pattern mask, 8: UV curable resin film, 9: UV exposure optical system, 1
0: laser light, 11: UV light, 12: pedestal for DRAM, 13: pedestal for signal processing LSI, 14: coater part,
15: exposure unit, 16: overall exposure stage, 17: cassette, 18: cassette loader, 19, 24: interface buffer, 20: arm robot, 21: resin coating cup, 22: developing cup, 23: bake stage, 25: Mercury lamps, 67, 68, 69, 71:
Pedestal, 70, 74, 75: chip.

Claims (6)

[Claims] 1. A method of manufacturing a multi-chip module in which a plurality of semiconductor chips electrically connected to a support substrate are mounted, wherein a height of each of the semiconductor chips is measured in advance, and a pedestal corresponding to the height is measured. Forming on the support substrate, image-recognizing the surface circuit pattern of the semiconductor chip, and aligning each semiconductor chip at a predetermined position on the support substrate based on the data of the image-recognized surface circuit pattern. A method for manufacturing a multi-chip module, comprising a step of mounting on a pedestal. 2. The method according to claim 1, wherein the supporting substrate is coated with a photo-curable resin, a pedestal pattern is printed on the photo-curable resin with an exposure amount corresponding to height data of the semiconductor chip, and the pedestal is formed by a developing process. The method for manufacturing a multi-chip module according to claim 1, wherein a variation in chip height is canceled by using the method. 3. The method according to claim 1, wherein the pedestal has a plurality of support points for each chip. 4. After forming a pedestal on the supporting substrate, a thin film having at least one of high thermal conductivity and high electrical conductivity is deposited, and the semiconductor chip is mounted thereon. Item 2. The method for manufacturing a multichip module according to Item 1. 5. An apparatus for manufacturing a multi-chip module having a plurality of semiconductor chips electrically connected on a support substrate, wherein the height of each semiconductor chip is at a mounting position of the semiconductor chip on the support substrate. A pedestal forming apparatus for forming a pedestal according to the image recognition of the surface circuit pattern of the semiconductor chip, and placing each semiconductor chip at a predetermined position of the support substrate based on data of the image recognized surface circuit pattern. A multi-chip module manufacturing apparatus, comprising: a chip mounting device that is aligned and mounted on the pedestal. 6. The pedestal forming apparatus includes a coater for coating a photocurable resin, and an exposure unit for exposing a semiconductor chip mounting area of the support substrate with an exposure amount corresponding to a height of each semiconductor chip. The chip mounting device includes a chip image capturing optical system for imaging a surface circuit pattern of a semiconductor chip, a mark position detecting optical system for detecting an alignment mark of the semiconductor chip, and the support substrate. A stage capable of adjusting the position in the XY and Z directions, a support substrate transfer system for transferring the support substrate to the stage, and a chip transfer system for transferring the semiconductor chip onto the support substrate on the stage. The multi-chip module manufacturing apparatus according to claim 5, wherein: