JP2000021935A - Electronic component mounting body and manufacture thereof - Google Patents
Electronic component mounting body and manufacture thereofInfo
- Publication number
- JP2000021935A JP2000021935A JP10198126A JP19812698A JP2000021935A JP 2000021935 A JP2000021935 A JP 2000021935A JP 10198126 A JP10198126 A JP 10198126A JP 19812698 A JP19812698 A JP 19812698A JP 2000021935 A JP2000021935 A JP 2000021935A
- Authority
- JP
- Japan
- Prior art keywords
- sealing
- semiconductor chip
- electronic component
- film
- film substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、フィルム基板上
に電子部品を搭載してなる電子部品実装体及びその製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component package having electronic components mounted on a film substrate and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】ＬＳＩ等からなる半導体チップ（電子部
品）の実装技術には、ＣＯＦ(Chip OnFilm)と呼ばれる
技術がある。図２は従来のこのような実装技術によって
製造された半導体チップ実装体（電子部品実装体）の一
例の断面図を示したものである。この半導体チップ実装
体はフィルム基板１を備えている。フィルム基板１の上
面の所定の箇所には入力側の外部接続パッド２、半導体
チップ用接続パッド３及びその間の引き回し線４が設け
られ、他の所定の箇所には出力側の外部接続パッド５、
半導体チップ用接続パッド６及びその間の引き回し線７
が設けられている。フィルム基板１の上面において両外
部接続パッド２、５の部分及び両半導体チップ用接続パ
ッド３、６の部分（つまり半導体チップ搭載領域）を除
く部分には、引き回し線４、７を保護するための絶縁性
インクからなる保護膜８が設けられている。フィルム基
板１の上面の半導体チップ搭載領域にはＬＳＩ等からな
る半導体チップ９が、その下面に設けられたバンプ１
０、１１を半導体チップ用接続パッド３、６に接続され
た状態で、搭載されている。そして、半導体チップ９の
周囲に封止材１２の材料がディスペンサによって滴下さ
れることにより、半導体チップ９とフィルム基板１との
間及び半導体チップ９の近傍における保護膜８の上面に
は、半導体チップ９の下面を保護（封止）するための封
止材１２が設けられている。2. Description of the Related Art There is a technique called COF (Chip On Film) as a mounting technique of a semiconductor chip (electronic component) composed of an LSI or the like. FIG. 2 is a cross-sectional view of an example of a semiconductor chip package (electronic component package) manufactured by such a conventional mounting technique. This semiconductor chip mounting body includes a film substrate 1. The external connection pads 2 on the input side, the connection pads 3 for the semiconductor chip, and the lead wires 4 therebetween are provided at predetermined locations on the upper surface of the film substrate 1, and the external connection pads 5 on the output side are provided at other predetermined locations.
Connection pads 6 for semiconductor chips and lead wires 7 between them
Is provided. On the upper surface of the film substrate 1, portions other than the portions of the external connection pads 2 and 5 and the portions of the connection pads 3 and 6 for the semiconductor chips (that is, the semiconductor chip mounting area) are provided for protecting the lead lines 4 and 7. A protective film 8 made of insulating ink is provided. A semiconductor chip 9 made of an LSI or the like is provided on a semiconductor chip mounting area on the upper surface of the film substrate 1 with bumps 1 provided on the lower surface thereof.
0 and 11 are mounted in a state where they are connected to the connection pads 3 and 6 for the semiconductor chip. The material of the sealing material 12 is dropped around the semiconductor chip 9 by a dispenser, so that a semiconductor chip is provided between the semiconductor chip 9 and the film substrate 1 and on the upper surface of the protective film 8 in the vicinity of the semiconductor chip 9. A sealing material 12 for protecting (sealing) the lower surface of 9 is provided.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来の
このような半導体チップ実装体では、フィルム基板１が
半導体チップ９の近傍で折り曲げられた場合、封止材１
２と保護膜８との界面で剥離が生じ、封止材１２の機能
が損なわれてしまうことがあるという問題があった。ま
た、保護膜８と封止材１２とをそれぞれ別の工程で形成
することになるので、製造工程数が多くなるという問題
もあった。この発明の課題は、特に封止機能が損なわれ
ることがなく、また製造工程数を少なくすることであ
る。However, in such a conventional semiconductor chip mounting body, when the film substrate 1 is bent in the vicinity of the semiconductor chip 9, the sealing material 1 is bent.
At the interface between the protective film 2 and the protective film 8, there is a problem that the function of the sealing material 12 may be impaired. In addition, since the protective film 8 and the sealing material 12 are formed in different steps, there is a problem that the number of manufacturing steps is increased. An object of the present invention is to reduce the number of manufacturing steps without particularly impairing the sealing function.
【０００４】[0004]
【課題を解決するための手段】請求項１記載の発明に係
る電子部品実装体は、一の面に電子部品用接続パッド、
外部接続パッド及びその間の引き回し線が設けられたフ
ィルム基板と、前記フィルム基板の電子部品用接続パッ
ドの部分に該電子部品用接続パッドに接続されて搭載さ
れた電子部品と、前記電子部品と前記フィルム基板との
間に介在されているとともに前記フィルム基板の引き回
し線の部分を覆う封止兼保護膜とを具備したものであ
る。請求項３記載の発明に係る電子部品実装体の製造方
法は、一の面に電子部品用接続パッド、外部接続パッド
及びその間の引き回し線が設けられたフィルム基板の一
の面上であって前記外部接続パッドの部分を除く部分に
封止兼保護膜を形成し、前記フィルム基板の電子部品用
接続パッドの部分における前記封止兼保護膜上に電子部
品を前記電子部品用接続パッドに接続させて搭載するよ
うにしたものである。この発明によれば、封止兼保護膜
に封止機能と保護機能とを兼ね備えさせているので、従
来のような剥離現象が生じることがなく、したがって特
に封止機能が損なわれることがなく、また封止兼保護膜
のみを形成すればよいので、製造工程数を少なくするこ
とができる。According to a first aspect of the present invention, there is provided an electronic component mounted body including a connection pad for an electronic component,
A film substrate provided with external connection pads and lead-out lines therebetween, an electronic component connected to and mounted on the electronic component connection pad of the film substrate, A sealing / protective film interposed between the film substrate and the wiring line of the film substrate. The method for manufacturing an electronic component package according to the invention according to claim 3, wherein the electronic component connection pad, the external connection pad, and the lead-out line between them are provided on one surface of the film substrate. A sealing and protection film is formed in a portion except an external connection pad portion, and an electronic component is connected to the electronic component connection pad on the sealing and protection film in an electronic component connection pad portion of the film substrate. It is intended to be mounted. According to the present invention, since the sealing and protection film has both the sealing function and the protection function, the conventional peeling phenomenon does not occur, and thus the sealing function is not particularly impaired. Further, since only the sealing and protection film needs to be formed, the number of manufacturing steps can be reduced.
【０００５】[0005]
【発明の実施の形態】図１（Ａ）〜（Ｄ）はそれぞれこ
の発明の一実施形態における半導体チップ実装体の各製
造工程を示したものである。そこで、これらの図を順に
参照して、この実施形態における半導体チップ実装体の
構造及びその製造方法について説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1A to 1D show respective manufacturing steps of a semiconductor chip package according to an embodiment of the present invention. Therefore, the structure of the semiconductor chip mounted body in this embodiment and the method of manufacturing the same will be described with reference to these drawings in order.
【０００６】まず、図１（Ａ）に示すように、ポリイミ
ドやポリエチレンテレフタレート等からなるフィルム基
板２１の上面にラミネートされた銅箔やアルミニウム箔
等からなる導電膜をパターニングすることにより、フィ
ルム基板２１の上面の所定の箇所に入力側の外部接続パ
ッド２２、半導体チップ用接続パッド２３及びその間の
引き回し線２４を形成するとともに、他の所定の箇所に
出力側の外部接続パッド２５、半導体チップ用接続パッ
ド２６及びその間の引き回し線２７を形成する。次に、
外部接続パッド２２、２５、半導体チップ用接続パッド
２３、２６及び引き回し線２４、２７上に電解メッキあ
るいは無電解メッキにより金、錫、半田等のメッキ層
（図示せず）を形成する。First, as shown in FIG. 1A, a conductive film made of copper foil, aluminum foil, or the like laminated on the upper surface of a film substrate 21 made of polyimide, polyethylene terephthalate, or the like is patterned. The external connection pad 22 on the input side, the connection pad 23 for the semiconductor chip, and the routing line 24 therebetween are formed at a predetermined location on the upper surface of the device, and the external connection pad 25 on the output side and the connection for the semiconductor chip are formed at another predetermined location. The pads 26 and the routing lines 27 therebetween are formed. next,
A plating layer (not shown) of gold, tin, solder, or the like is formed on the external connection pads 22, 25, the connection pads 23, 26 for the semiconductor chip, and the lead wires 24, 27 by electrolytic plating or electroless plating.
【０００７】次に、図１（Ｂ）に示すように、フィルム
基板２１の上面において両外部接続パッド２２、２５の
部分を除く部分に、熱可塑性エポキシ樹脂やＢ−ステー
ジエポキシ樹脂等の透明または半透明な熱可塑性樹脂を
印刷法やディスペンサ法等により塗布したりシート状の
ものをラミネートしたりすることにより、所定の厚さの
封止兼保護膜２８を形成する。次に、樹脂温度１５０℃
程度で１時間程度の加熱を行い、封止兼保護膜２８をあ
る程度硬化させる。次に、図１（Ｃ）に示すように、下
面に金等からなるバンプ３０、３１を有するＬＳＩ等か
らなる半導体チップ２９を、図示しない吸着機構付きボ
ンディングヘッドを用いて、フィルム基板２１の上面の
半導体チップ搭載領域の上方に位置合わせして配置す
る。この場合の位置合わせは、封止兼保護膜２８が透明
または半透明であるので、この封止兼保護膜２８下の半
導体チップ用接続パッド２３、２６を図示しないカメラ
で画像確認すること等によって行われる。Next, as shown in FIG. 1 (B), a transparent or thermoplastic epoxy resin or a B-stage epoxy resin or the like is provided on the upper surface of the film substrate 21 except for the two external connection pads 22 and 25. The sealing and protection film 28 having a predetermined thickness is formed by applying a translucent thermoplastic resin by a printing method or a dispenser method, or by laminating a sheet-like material. Next, a resin temperature of 150 ° C.
Heating is performed for about one hour, and the sealing and protection film 28 is cured to some extent. Next, as shown in FIG. 1C, a semiconductor chip 29 made of LSI or the like having bumps 30 and 31 made of gold or the like on the lower surface is attached to the upper surface of the film substrate 21 using a bonding head with a suction mechanism not shown. Above the semiconductor chip mounting area. In this case, since the sealing and protection film 28 is transparent or translucent, the semiconductor chip connection pads 23 and 26 under the sealing and protection film 28 are image-checked by a camera (not shown) or the like. Done.
【０００８】次に、図１（Ｄ）に示すように、半導体チ
ップ２９をボンディングヘッドと共に下降させ、フェー
スダウンボンディングを行う。この場合のボンディング
条件は、一例として、樹脂温度が融点以上（２００〜２
５０℃程度）で１〜１０秒程度とする。すると、半導体
チップ２９のバンプ３０、３１が、融点以上に加熱され
て軟らかくなった封止兼保護膜２８中に減り込み、半導
体チップ用接続パッド２３、２６に接続される。また、
半導体チップ２９の周囲における封止兼保護膜２８がや
や盛り上がって、半導体チップ２９の下部外周面を覆う
状態となる。そして、封止兼保護膜２８が硬化すること
により、特に半導体チップ２９の下面はその下の封止兼
保護膜２８を介してフィルム基板２１上に接着される。
かくして、フィルム基板２１の上面の半導体チップ搭載
領域に半導体チップ２９が搭載される。Next, as shown in FIG. 1D, the semiconductor chip 29 is lowered together with the bonding head to perform face-down bonding. The bonding condition in this case is, for example, that the resin temperature is higher than the melting point (200 to 2).
(About 50 ° C.) for about 1 to 10 seconds. Then, the bumps 30 and 31 of the semiconductor chip 29 are reduced into the sealing and protective film 28 which has been heated to a melting point or more and softened, and are connected to the semiconductor chip connection pads 23 and 26. Also,
The sealing and protection film 28 around the semiconductor chip 29 rises slightly to cover the lower outer peripheral surface of the semiconductor chip 29. When the sealing and protection film 28 is cured, the lower surface of the semiconductor chip 29 is bonded to the film substrate 21 through the sealing and protection film 28 thereunder.
Thus, the semiconductor chip 29 is mounted on the semiconductor chip mounting area on the upper surface of the film substrate 21.
【０００９】このようにして得られた半導体チップ実装
体では、封止兼保護膜２８が半導体チップ２９の下面を
保護（封止）する機能と引き回し線２４、２７を保護す
る機能とを兼ね備えることになるので、フィルム基板２
１が半導体チップ２９の近傍で折り曲げられても、従来
のような剥離現象が生じることがなく、したがって特に
封止機能が損なわれることがなく、また封止兼保護膜２
８のみを形成すればよいので、製造工程数を少なくする
ことができる。In the semiconductor chip mounted body thus obtained, the sealing and protection film 28 has both the function of protecting (sealing) the lower surface of the semiconductor chip 29 and the function of protecting the lead wires 24 and 27. So the film substrate 2
1 is bent in the vicinity of the semiconductor chip 29, the conventional peeling phenomenon does not occur, so that the sealing function is not particularly impaired.
Since only eight pieces need to be formed, the number of manufacturing steps can be reduced.
【００１０】ここで、この半導体チップ実装体の寸法の
一例について説明する。外部接続パッド２２、２５等の
配線の厚さは８〜１８μｍ程度である。封止兼保護膜２
８のフィルム基板２１上における厚さは、半導体チップ
２９のバンプ３０、３１の高さの１．５〜２倍程度であ
る。封止兼保護膜２８の外部接続パッド２２、２５等の
配線上における厚さは、半導体チップ２９のバンプ３
０、３１の高さとほぼ同じである。したがって、バンプ
３０、３１の高さが１５μｍ程度であれば、封止兼保護
膜２８の外部接続パッド２２、２５等の配線上における
厚さも１５μｍ程度である。Here, an example of the dimensions of the semiconductor chip mounted body will be described. The thickness of the wiring such as the external connection pads 22 and 25 is about 8 to 18 μm. Sealing and protective film 2
8 on the film substrate 21 is about 1.5 to 2 times the height of the bumps 30 and 31 of the semiconductor chip 29. The thickness of the sealing and protection film 28 on the wiring such as the external connection pads 22 and 25 is the same as that of the bump 3 of the semiconductor chip 29.
It is almost the same as the height of 0 and 31. Therefore, if the height of the bumps 30 and 31 is about 15 μm, the thickness of the sealing and protection film 28 on the wiring such as the external connection pads 22 and 25 is also about 15 μm.
【００１１】なお、上記実施形態では、図１（Ｃ）に示
すように、封止兼保護膜２８の表面を平坦とした場合に
ついて説明したが、これに限定されるものではない。例
えば、半導体チップ２９の下面中央部に対応する部分に
おける封止兼保護膜２８の表面を適宜に盛り上げ、ボン
ディング時に半導体チップ２９の下面で当該盛り上が部
を押し付けて平坦化するとともに、半導体チップ２９の
下面と封止兼保護膜２８の表面との間に存在するエアー
を押し出すようにしてもよい。このようにした場合に
は、半導体チップ２９と封止兼保護膜２８との間の密着
力を上げることができる。In the above embodiment, the case where the surface of the sealing and protection film 28 is flat as shown in FIG. 1C has been described, but the present invention is not limited to this. For example, the surface of the sealing and protection film 28 at a portion corresponding to the central portion of the lower surface of the semiconductor chip 29 is appropriately raised, and the raised portion is pressed against the lower surface of the semiconductor chip 29 at the time of bonding to flatten the semiconductor chip 29. The air existing between the lower surface of the upper surface 29 and the surface of the sealing and protection film 28 may be pushed out. In this case, the adhesion between the semiconductor chip 29 and the sealing and protection film 28 can be increased.
【００１２】また、上記実施形態では、フィルム基板２
１の上面にラミネートされた銅箔等からなる導電膜をパ
ターニングする場合について説明したが、これに限ら
ず、例えばフィルム基板２１の上面に接着剤層を介して
ラミネートされた銅箔等からなる導電膜をパターニング
するようにしてもよい。さらに、上記実施形態では、半
導体チップ２９にバンプ３０、３１を設けた場合につい
て説明したが、これに限らず、フィルム基板２１の半導
体チップ用接続パッド２４、２７上にバンプを設けるよ
うにしてもよい。ただし、半導体チップ２９の接続パッ
ドがアルミニウムによって形成されている場合には、オ
ーミックコンタクトを良好とするために、半導体チップ
２９のアルミニウムからなる接続パッド上に金属層（例
えばＴｉＷ層とＡｕ層の２層構造あるいはＴｉ層とＡｕ
層の２層構造）を形成するようにする。In the above embodiment, the film substrate 2
Although the case where the conductive film made of a copper foil or the like laminated on the upper surface of the film substrate 1 is patterned has been described, the present invention is not limited to this. The film may be patterned. Further, in the above-described embodiment, the case where the bumps 30 and 31 are provided on the semiconductor chip 29 has been described. However, the present invention is not limited to this. Good. However, when the connection pads of the semiconductor chip 29 are formed of aluminum, a metal layer (for example, a TiW layer and an Au layer of two layers) is formed on the aluminum connection pads of the semiconductor chip 29 to improve the ohmic contact. Layer structure or Ti layer and Au
(A two-layer structure of layers).
【００１３】[0013]
【発明の効果】以上説明したように、この発明によれ
ば、封止兼保護膜に封止機能と保護機能とを兼ね備えさ
せているので、従来のような剥離現象が生じることがな
く、したがって特に封止機能が損なわれることがなく、
また封止兼保護膜のみを形成すればよいので、製造工程
数を少なくすることができる。As described above, according to the present invention, since the sealing and protection film has both the sealing function and the protection function, the conventional peeling phenomenon does not occur. In particular, without impairing the sealing function,
Further, since only the sealing and protection film needs to be formed, the number of manufacturing steps can be reduced.
【図１】（Ａ）〜（Ｄ）はそれぞれこの発明の一実施形
態における半導体チップ実装体の各製造工程の断面図。FIGS. 1A to 1D are cross-sectional views of respective manufacturing steps of a semiconductor chip package according to an embodiment of the present invention;
【図２】従来の半導体チップ実装体の一例の断面図。FIG. 2 is a cross-sectional view of an example of a conventional semiconductor chip package.
２１ フィルム基板 ２２、２５ 外部接続パッド ２３、２６ 半導体チップ用接続パッド ２４、２７ 引き回し線 ２８ 封止兼保護膜 ２９ 半導体チップ Reference Signs List 21 film substrate 22, 25 external connection pad 23, 26 connection pad for semiconductor chip 24, 27 wiring 28 sealing and protection film 29 semiconductor chip
Claims (4)
続パッド及びその間の引き回し線が設けられたフィルム
基板と、前記フィルム基板の電子部品用接続パッドの部
分に該電子部品用接続パッドに接続されて搭載された電
子部品と、前記電子部品と前記フィルム基板との間に介
在されているとともに前記フィルム基板の引き回し線の
部分を覆う封止兼保護膜とを具備することを特徴とする
電子部品実装体。1. A film substrate provided with an electronic component connection pad, an external connection pad, and a lead line between them on one surface, and an electronic component connection pad on the electronic component connection pad portion of the film substrate. An electronic component connected and mounted, and a sealing / protective film interposed between the electronic component and the film substrate and covering a portion of a lead line of the film substrate. Electronic component mount.
兼保護膜は熱可塑性樹脂からなっていることを特徴とす
る電子部品実装体。2. The electronic component package according to claim 1, wherein the sealing and protection film is made of a thermoplastic resin.
続パッド及びその間の引き回し線が設けられたフィルム
基板の一の面上であって前記外部接続パッドの部分を除
く部分に封止兼保護膜を形成し、前記フィルム基板の電
子部品用接続パッドの部分における前記封止兼保護膜上
に電子部品を前記電子部品用接続パッドに接続させて搭
載することを特徴とする電子部品実装体の製造方法。3. A portion of the film substrate on one surface on which a connection pad for an electronic component, an external connection pad, and a lead-out line therebetween are provided, and a portion other than the external connection pad is sealed and sealed. An electronic component package, comprising: forming a protective film, and mounting an electronic component on the sealing / protective film in a portion of the film substrate where the electronic component connection pad is connected to the electronic component connection pad. Manufacturing method.
兼保護膜は熱可塑性樹脂によって形成することを特徴と
する電子部品実装体の製造方法。4. The method according to claim 3, wherein the sealing and protection film is formed of a thermoplastic resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19812698A JP3951462B2 (en) | 1998-06-30 | 1998-06-30 | Electronic component mounting body and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19812698A JP3951462B2 (en) | 1998-06-30 | 1998-06-30 | Electronic component mounting body and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000021935A true JP2000021935A (en) | 2000-01-21 |
| JP3951462B2 JP3951462B2 (en) | 2007-08-01 |
Family
ID=16385893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19812698A Expired - Fee Related JP3951462B2 (en) | 1998-06-30 | 1998-06-30 | Electronic component mounting body and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3951462B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002313841A (en) * | 2000-04-14 | 2002-10-25 | Namics Corp | Flip-chip mounting method |
| US6972381B2 (en) | 1998-07-01 | 2005-12-06 | Seiko Epson Corporation | Semiconductor device and method of manufacture thereof, circuit board and electronic instrument |
| US7042644B2 (en) | 1998-12-10 | 2006-05-09 | Seiko Epson Corporation | Optical substrate and display device using the same |
| JP2006147983A (en) * | 2004-11-24 | 2006-06-08 | Oki Electric Ind Co Ltd | Film carrier for chip-on-film and semiconductor device using it |
| US7170145B2 (en) | 2003-04-28 | 2007-01-30 | Sharp Kabushiki Kaisha | Method of manufacturing semiconductor device, flexible substrate, and semiconductor device |
| CN100411163C (en) * | 2002-10-04 | 2008-08-13 | 夏普株式会社 | Cof semiconductor device and a manufacturing method for the same |
-
1998
- 1998-06-30 JP JP19812698A patent/JP3951462B2/en not_active Expired - Fee Related
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6972381B2 (en) | 1998-07-01 | 2005-12-06 | Seiko Epson Corporation | Semiconductor device and method of manufacture thereof, circuit board and electronic instrument |
| US6995476B2 (en) | 1998-07-01 | 2006-02-07 | Seiko Epson Corporation | Semiconductor device, circuit board and electronic instrument that include an adhesive with conductive particles therein |
| US7198984B2 (en) | 1998-07-01 | 2007-04-03 | Seiko Epson Corporation | Semiconductor device and method of manufacture thereof, circuit board and electronic instrument |
| US7332371B2 (en) | 1998-07-01 | 2008-02-19 | Seiko Epson Corporation | Semiconductor device and method of manufacture thereof, circuit board and electronic instrument |
| US7560819B2 (en) | 1998-07-01 | 2009-07-14 | Seiko Epson Corporation | Semiconductor device and method of manufacture thereof, circuit board and electronic instrument |
| US7868466B2 (en) | 1998-07-01 | 2011-01-11 | Seiko Epson Corporation | Semiconductor device and method of manufacture thereof, circuit board and electronic instrument |
| US7042644B2 (en) | 1998-12-10 | 2006-05-09 | Seiko Epson Corporation | Optical substrate and display device using the same |
| JP2002313841A (en) * | 2000-04-14 | 2002-10-25 | Namics Corp | Flip-chip mounting method |
| CN100411163C (en) * | 2002-10-04 | 2008-08-13 | 夏普株式会社 | Cof semiconductor device and a manufacturing method for the same |
| US7170145B2 (en) | 2003-04-28 | 2007-01-30 | Sharp Kabushiki Kaisha | Method of manufacturing semiconductor device, flexible substrate, and semiconductor device |
| JP2006147983A (en) * | 2004-11-24 | 2006-06-08 | Oki Electric Ind Co Ltd | Film carrier for chip-on-film and semiconductor device using it |
| JP4573103B2 (en) * | 2004-11-24 | 2010-11-04 | Ｏｋｉセミコンダクタ株式会社 | Film carrier for chip-on-film and semiconductor device using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3951462B2 (en) | 2007-08-01 |
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