JP2006147983A - Film carrier for chip-on-film and semiconductor device using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for quantitatively keeping a track of the bonding strength of each inner lead after bonding even if a film carrier for a chip-on-film is used. <P>SOLUTION: The film carrier for the chip-on-film is formed with base film, a wiring pattern formed on the base film and a resist for protecting the wiring pattern and inner leads of the wiring pattern are exposed in a semiconductor device mounting region which is formed of the opening of the resist. In this case, a cutoff line along an endless line following sides of the inner lead and its end is formed on the base film in the semiconductor device mounting region. For checking bonding strength, the base film is cut off by using the cutoff line and the bonding strength of the inner lead is measured. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a film carrier for chip-on-film used for manufacturing a semiconductor device having a COF (Chip On Film / chip-on-film) structure and a semiconductor device using the same.

  A conventional COF structure semiconductor device has a wiring pattern formed on a thin flexible base film that can be bent freely, and an inner lead and an input terminal for connecting a semiconductor element provided in the wiring pattern. And a film carrier for chip-on-film (hereinafter referred to as a film carrier) formed by covering portions other than the output terminals with a resist.

  When manufacturing a semiconductor device, the positions of the inner leads exposed in the region where the semiconductor element not covered with the resist is mounted (referred to as a semiconductor element mounting region) and the bump formed on the terminal of the semiconductor element are determined. In addition, the semiconductor elements are mounted on the film carrier by bonding them together, and the flow rate of the sealing resin injected into the gap between the semiconductor elements mounted on the four corners of the semiconductor element mounting area and the base film is reduced. Then, the semiconductor element is sealed in a state where the bubble generation rate is reduced to 50% or less, and then the sealed semiconductor element is separated from the film carrier including the input terminal and the output terminal (for example, Patent Document 1). reference.).

The bonding of the semiconductor element performed on the film carrier is performed by aligning the inner lead of the semiconductor element mounting region and the bump of the semiconductor element, and then melting the bump of the semiconductor element by thermocompression bonding. It is performed by joining to.
Confirmation of the bonding strength at this time is generally as shown in FIGS. 15A to 15E because the bonding portion between the inner lead and the bump is covered with the base film and it is difficult to directly measure the bonding strength. The film carrier 101 is peeled off from the semiconductor element 114, and the peeled state is observed, and all the inner leads 108 are not peeled off from the bumps 115 and the inner leads 108 are broken (shown in FIG. 15E). State), it is determined that the bonding strength is sufficient.

On the other hand, in the manufacture of a semiconductor device with a TCP (Tape Carrier Package) structure, which is a surface-mount type semiconductor device similar to a semiconductor device with a COF structure, a through hole for mounting a semiconductor element in advance on a flexible carrier tape The bumps of the semiconductor element are bonded to the cantilevered inner leads protruding from the window, and the hook from the tension gauge that directly hooks the bonding strength after bonding to the inner leads is pulled upward. Measured by a tensile test to quantitatively grasp the bonding strength for each inner lead (see, for example, Patent Document 2).
JP 2002-124526 A (5th page paragraph 0038-4th page paragraph 0043, FIG. 1, FIG. 2) JP-A-6-117993 (2nd page, paragraphs 0002-0003, FIGS. 3 and 6)

  However, in the conventional method for confirming the bonding strength between the film carrier and the semiconductor element used in the semiconductor device having the COF structure described above, it is possible to qualitatively determine whether the inner lead and the bump are bonded, but the inner lead Since it is not possible to directly measure the bonding strength for each, there is a problem that it is difficult to grasp variations in bonding strength, irregularities and inclinations of the bonding tool, abnormalities in the bonding state due to adhesion of foreign matters, and the like.

Further, since it is impossible to quantitatively grasp the bonding strength, there is a problem in that it is impossible to set a quantitative management standard in manufacturing process management, and it is impossible to find process abnormality in advance.
Furthermore, in the technique of Patent Document 1, the bubble generation rate in the injection of the sealing resin into the gap between the semiconductor element and the base film is reduced to 50% or less by the dummy patterns provided at the four corners of the semiconductor element mounting region of the film carrier. Even though it has been reduced, bubbles still exist inside the sealing resin after curing, and there is a problem that defects such as cracks and corrosion occur.

  Furthermore, in the technique of Patent Document 1, when positioning the semiconductor element and the inner lead, the surface pattern of the semiconductor element mounted on the base film must be confirmed through the base film. There is a problem that the positioning accuracy of the semiconductor element may be lowered due to an error due to a shadow of a material constituting the film and wrinkles or distortion of the base film.

The present invention has been made to solve the above problems, and provides a means for quantitatively grasping the bonding strength of each inner lead after bonding even when using a film carrier for chip-on-film. With the goal.
Another object of the present invention is to provide means for preventing entrainment of bubbles in the injection of the sealing resin into the gap between the semiconductor element and the base film.

  It is another object of the present invention to provide means for reliably confirming the surface pattern of a semiconductor element mounted on a base film when positioning the semiconductor element and the inner lead.

  In order to solve the above-mentioned problems, the present invention comprises a base film, a wiring pattern formed on the base film, and a resist that protects the wiring pattern, and the inner leads of the wiring pattern are opened in the resist. In the film carrier for chip-on-film exposed in the semiconductor element mounting region formed by the above, the base film in the semiconductor element mounting region is formed into a side surface of the inner lead and an endless line that traces the tip of the inner lead. It is characterized in that a cut line is formed along.

  The base film in the semiconductor element mounting area is formed with a cut line along at least one closed curve belonging to the semiconductor element mounting area.

As described above, the present invention provides a cut line on the base film in the semiconductor element mounting region of the film carrier along the side surface of the inner lead and the endless line that traces the tip of the inner lead. Thus, it is possible to easily measure the bonding strength between the inner lead and the bump of the semiconductor element using the space cut out by the above.
In addition, the base film at the center of the film carrier is cut off by a cut line provided along an endless line that traces the tip of the inner lead in the semiconductor element mounting region, thereby providing an opening. The sealing resin can be injected and the sealing resin can flow out to the outside of the semiconductor element, and the entrapment of bubbles in the injection of the sealing resin into the gap between the semiconductor element and the base film can be prevented. An effect is obtained.

  Furthermore, by providing a cut line along the closed curve belonging to the semiconductor element mounting area in the base film of the semiconductor element mounting area, when positioning the semiconductor element and the inner lead, the base film can be cut using the cutting line. The surface pattern of the semiconductor element to be mounted can be confirmed with certainty, and the positioning accuracy of the semiconductor element to be mounted can be improved.

  Examples of the film carrier according to the present invention will be described below with reference to the drawings.

  FIG. 1 is an enlarged view showing the tip of the inner lead of the film carrier of Example 1, FIG. 2 is a top view showing the film carrier of Example 1, and FIG. 3 shows the vicinity of the semiconductor element mounting region of the film carrier of Example 1. FIG. 4 is an AA cross-sectional view of FIG. 1, FIG. 5 is a partial enlarged view showing the vicinity of the inner lead of Example 1, and FIG. 6 is an enlarged view showing the end state of the bonding step of the semiconductor element of Example 1. It is sectional drawing. FIG. 1 is a bottom view seen from below in FIG.

2 and 3, reference numeral 1 denotes a film carrier.
Reference numeral 2 denotes a base film of the film carrier 1, which is a thin film of 100 μm or less that is made of a resin material such as polyimide having a relatively high heat resistance and is flexible, and has edge portions on both sides along the longitudinal direction thereof. Is formed with a plurality of sprocket holes 3 which are perforated at a predetermined pitch in order to move and position the film carrier 1 in the feed direction by fitting with sprocket teeth driven by a driving device (not shown). .

Reference numeral 4 denotes a wiring pattern, which is formed by selectively cutting a metal foil, such as a copper foil, formed on the base film 2 by plating or the like by photoetching or the like. 7 is electrically connected to the inner leads 8 formed on the inner surface 8.
A resist 9 covers a portion of the wiring pattern 4 other than the input terminal 5, the output terminal 6 and the inner lead 8 to protect the wiring at that portion.

The semiconductor element mounting area 7 is an opening provided in the resist 9 as an area for mounting a semiconductor element 14 to be described later on the film carrier 1, and inner leads 8 formed on the base film 2 are formed at the periphery of the opening. Exposed.
1, 4, and 5, reference numerals 11 and 12 denote cutoff lines. In this embodiment, as shown in FIGS. 1 and 4, a substantially square through-hole penetrating the base film 2 is intermittently formed. Perforated.

The cut line 11 is formed along both side surfaces of the inner lead 8, and the cut line 12 is formed at the tip of the inner lead 8, that is, the tip of the end on the center side of the semiconductor element installation region 7 as shown in FIGS. 2 and 4. It is formed along an endless line that follows.
In addition, the perforation shape used as the cut lines 11 and 12 is not limited to the above-described quadrilateral shape, and may be any shape such as a circle, an ellipse, or an ellipse. There may be. In short, it is sufficient if the cut portions penetrating the base film 2 are formed intermittently.

Further, it is desirable that the positions where the cut lines 11 and 12 are provided be as close as possible to the portion where the inner lead 8 and the base film 2 are in contact, and if possible, the portion where the inner lead 8 and the base film 2 are in contact is formed. Good.
In FIG. 6, reference numeral 14 denotes a semiconductor element such as an LSI, which is joined to the inner lead 8 exposed in the semiconductor element mounting region 7 by a bump 15 formed on the terminal thereof.

  The inner lead 8 and the bump 15 of the semiconductor element 14 are joined with the film carrier 1 shown in FIG. 3 turned upside down, and the semiconductor element 14 on which the bump 15 is formed is placed on the bonding stage 18 with the bump 15 facing up. The bonding stage 18 is moved and the bumps 15 and the inner leads 8 are aligned to raise the bonding stage 18 and the bonding tool 19 to lower the bumps 15 of the semiconductor element 14 on the bonding stage 18 and the inner leads 8. The lead 8 is pressed by the heated bonding tool 19 through the base film 2 to melt the bump 15 and thermocompression-bonded. Thereafter, the bonding stage 18 is lowered, the bonding tool 19 is raised, and the bonding stage 18 is moved to the semiconductor element. Away from 14 In a state shown in FIG. 4 Release the bonding tool 19 from the base film 2, and ends the bonding process of the semiconductor device 14.

In this embodiment, in order to prevent electrical failure due to contact between the corners of the semiconductor element 14 and the inner leads 8, the inner leads 8 are bent downward in FIG. 6 at the end of the joining process as shown in FIG. It is processed into the shape.
When the bonding strength between the bump 15 of the semiconductor element 14 bonded in this way and the inner lead 8 is confirmed, as shown in FIG. 7, the inner lead 8 for measuring the bonding strength and the inner leads 8 located on both sides thereof. The base film 2 is cut off by using the cut line 12 and the cut line 11, and the hook 20 is hooked on the inner lead 8 as shown in FIG. The hook 20 is lifted upward in FIG. 8 by a measuring device, and the load when the inner lead 8 and the bump 15 are broken is read to quantitatively check the bonding strength between the inner lead 8 and the bump 15.

When measuring the bonding strength between the plurality of inner leads 8 and the bumps 15, the above is repeated to measure the bonding strength.
Note that such measurement of the bonding strength is performed periodically (for example, one for each lot) or as necessary.
The semiconductor element 14 bonded as described above is then sealed, and the sealed semiconductor element 14 including the input terminal 5 and the output terminal 6 is separated from the film carrier 1 to manufacture a semiconductor device. .

  As described above, in this embodiment, the base film in the semiconductor element mounting region of the film carrier is formed with cut lines along the side surfaces of the inner leads and the endless lines that follow the tips of the inner leads. Can easily measure the bonding strength between the inner lead and the bump of the semiconductor element using the space cut by the cutting line, and quantitatively grasp the bonding strength of each inner lead and It can be used effectively for discovery and management of manufacturing processes, and process abnormalities can be prevented in advance.

Moreover, the base film can be easily cut by forming the cut lines with perforations penetrating the base film.
In the present embodiment, the cut line has been described as being formed by perforations penetrating the base film, but cut lines as shown below may be used.
9 is an enlarged view of the vicinity of the distal end portion of the inner lead showing another form of the cutoff line of Example 1, and FIG. 10 is a cross-sectional view taken along line BB of FIG. FIG. 9 is a bottom view seen from below in FIG.

The cut lines 11 and 12 of this embodiment are formed at the same positions as described above as shown in FIG. 9, and the shape thereof is perforated by a cut that does not penetrate the base film 2 that is stopped by a so-called single paper as shown in FIG. It is formed by processing.
If the cut line is formed by a cut that does not penetrate the base film in this way, it is possible to prevent the sealing resin injected between the semiconductor element and the base film from seeping out to the back surface of the base film after the semiconductor element bonding step. Can do.

  As described above, in this embodiment, the cut lines are formed by perforations or perforations, so that the rigidity of the film carrier can be maintained higher than when the base film is cut in advance. Thus, handling of the film carrier in the manufacturing process can be facilitated. This is particularly useful in a film carrier for chip-on-film that is rich in flexibility and used for manufacturing a semiconductor device having a COF structure.

  In addition, when forming a cutting line by the notch which does not penetrate a base film, you may make it form each as a continuous groove | channel other than forming in perforation shape as mentioned above.

FIG. 11 is a bottom view showing the vicinity of the semiconductor element mounting region of the second embodiment.
In addition, the same part as the said Example 1 attaches | subjects the same code | symbol, and abbreviate | omits the description.
FIG. 11 shows a state in which the semiconductor element 14 is exposed by cutting off the central portion of the inner lead 8 of the base film 2 using the cutting line 12 after the bonding step of the semiconductor element 14 described in the first embodiment. Show.

The resist 9 of this embodiment is formed up to a position relatively close to the semiconductor element 14 as shown in FIG. 12, and the length of the inner lead 8 is set to be shorter than that of the first embodiment.
Thus, the film carrier 1 provided with an opening on the central portion side of the inner lead 8 of the base film 2 using the cut line 12 is used as follows in the sealing step with the sealing resin 21 shown by shading in FIG. .

That is, as shown in FIG. 12, the sealing resin 21 is injected from the opening on the center portion side of the inner lead 8 using the nozzle 22 for injecting the sealing resin 21.
The injection of the sealing resin 21 at this time is performed while moving the nozzle 22 in the vicinity of the center of the opening, and the semiconductor element is injected so that the sealing resin 21 injected into the ventral side of the semiconductor element 14 is transmitted through the semiconductor element 14. 14 is extended to four sides to cover the joint portion between the inner lead 8 and the bump 15, and protrudes from the outside of the semiconductor element 14, and the sealing resin 21 reaches the resist 9 and covers the exposed portion of the inner lead 8. Stop infusion. Thereafter, the sealing resin 21 is cured by heating or the like, and the sealing process of the semiconductor element 14 is completed.

  As described above, in this embodiment, the base film in the central portion of the film carrier is cut off by the cut line provided along the endless line that traces the tip of the inner lead in the semiconductor element mounting region to provide the opening. As a result, the sealing resin can be injected from the cut-out opening so that the sealing resin can flow out toward the outside of the semiconductor element, and no air retention occurs, so that there is no gap between the semiconductor element and the base film. It is possible to prevent entrainment of air bubbles in the injection of the sealing resin into the sealing resin, thereby preventing cracks, corrosion, etc. occurring in the cured sealing resin.

  In addition, the sealing resin used for sealing a semiconductor device having a COF structure is usually expensive. However, if a sealing resin is injected from a cut opening, a relatively inexpensive TCP structure semiconductor device can be sealed. Since the sealing resin to be used can be used, the cost of the semiconductor device having a COF structure can be reduced.

FIG. 13 is a bottom view showing the vicinity of the semiconductor element mounting region of the third embodiment.
In addition, the same part as the said Example 1 attaches | subjects the same code | symbol, and abbreviate | omits the description.
In FIG. 13, reference numeral 25 denotes a cutoff line, which is formed on the base film 2 in the semiconductor element mounting region 7 along a closed curve belonging to the semiconductor element mounting region 7.
The cut lines 25 of the present embodiment are perforations formed along circular closed curves provided at the four corners on the central portion side of the inner lead 8 in the semiconductor element mounting region 7.

Such a cut line 25 is used for alignment of the bump 15 and the inner lead 8 in the bonding process of the semiconductor element 14.
That is, as shown in FIG. 14, before the alignment of the semiconductor element 14 described in the first embodiment, a closed curve formed by the cut line 25 is punched using a punch or the like, and this is used as a peephole to form a part of the semiconductor element 14. Is visible from the base film 2 side.

Then, when aligning the bump 15 and the inner lead 8, the surface pattern of the semiconductor element 14 is directly confirmed from the viewing hole, and then the alignment is performed. Thereafter, as in the first embodiment, the bump 15 and the inner lead 8 are aligned. 8 is joined.
In the present embodiment, it has been described that four cutting lines 25 are provided. However, it is sufficient that the surface pattern of the semiconductor element 14 can be directly confirmed, and it is sufficient that at least one cutting line 25 is provided.

  As described above, in this embodiment, the cut line is provided when positioning the semiconductor element and the inner lead by providing the cut line along the closed curve belonging to the semiconductor element mounting area in the base film of the semiconductor element mounting area. If the base film is cut out using, the surface pattern of the semiconductor element to be mounted can be reliably confirmed, and the positioning accuracy of the semiconductor element to be mounted can be improved.

The enlarged view which shows the inner lead front-end | tip part of the film carrier of Example 1 The top view which shows the film carrier of Example 1 The expanded sectional view which shows the semiconductor element mounting area vicinity of the film carrier of Example 1 AA sectional view of FIG. Partial enlarged view showing the vicinity of the inner lead of Example 1 Explanatory drawing which shows the completion | finish state of the joining process of the semiconductor element of Example 1. Explanatory drawing which shows the cutting state by the cutting line of the base film of Example 1 Explanatory drawing which shows the measurement state of the joint strength of the semiconductor element of Example 1. The enlarged view of the inner lead front-end | tip part vicinity which shows the other form of the cutoff line of Example 1. BB sectional view of FIG. The bottom view which shows the semiconductor element mounting area vicinity of Example 2. Explanatory drawing which shows the sealing process of the semiconductor element of Example 2. The bottom view which shows the semiconductor element mounting area vicinity of Example 3. The bottom view which shows the punching state of the peephole of Example 3 Explanatory drawing which shows the confirmation method of the joining strength of the conventional semiconductor element

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,101 Film carrier 2 Base film 3 Sprocket hole 4 Wiring pattern 5 Input terminal 6 Output terminal 7 Semiconductor element mounting area 8, 108 Inner lead 9 Resist 11, 12, 25 Cut line 14, 114 Semiconductor element 15, 115 Bump 18 Bonding stage 19 Bonding tool 20 Hook 21 Sealing resin 22 Nozzle

Claims (5)

A base film, a wiring pattern formed on the base film, and a resist that protects the wiring pattern, and an inner lead of the wiring pattern is exposed to a semiconductor element mounting region formed by the opening of the resist In film carrier for chip-on-film,
A film carrier for chip-on-film, wherein a cut line along a side surface of the inner lead and an endless line tracing the tip of the inner lead is formed on the base film in the semiconductor element mounting region. A base film, a wiring pattern formed on the base film, and a resist that protects the wiring pattern, and an inner lead of the wiring pattern is exposed to a semiconductor element mounting region formed by the opening of the resist In film carrier for chip-on-film,
A film carrier for chip-on-film, wherein a cut line along at least one closed curve belonging to the semiconductor element mounting region is formed on a base film of the semiconductor element mounting region. In claim 1 or claim 2,
The film carrier for chip-on-film, wherein the cut line is formed by a perforation penetrating the base film. In claim 1 or claim 2,
The film carrier for chip-on-film, wherein the tear line is formed by a perforated cut that does not penetrate the base film. A semiconductor device formed using the film carrier for chip-on-film according to claim 1.

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