JPH07147299A - Semiconductor integrated circuit device and mounting method thereof - Google Patents

Semiconductor integrated circuit device and mounting method thereof

Info

Publication number
JPH07147299A
JPH07147299A JP29584293A JP29584293A JPH07147299A JP H07147299 A JPH07147299 A JP H07147299A JP 29584293 A JP29584293 A JP 29584293A JP 29584293 A JP29584293 A JP 29584293A JP H07147299 A JPH07147299 A JP H07147299A
Authority
JP
Japan
Prior art keywords
lsi chip
integrated circuit
semiconductor integrated
circuit device
seal ring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP29584293A
Other languages
Japanese (ja)
Other versions
JP2669310B2 (en
Inventor
Kazufumi Takahashi
和史 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5295842A priority Critical patent/JP2669310B2/en
Publication of JPH07147299A publication Critical patent/JPH07147299A/en
Application granted granted Critical
Publication of JP2669310B2 publication Critical patent/JP2669310B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the heat increase of an LSI chip with simplified case by air-tightly sealing the element region of the LSI chip and a pad electrode with a seal ring to be connected to the LSI chip and a dielectric substarate. CONSTITUTION:An LSI chip 1 is connected to a pattern 10 on a ceramic substarate 4 via a sealing ring 2, an element region 7 provided on the LSI chip 1 and a pad electrode 3 are air-tightly sealed by the LSI chip and sealing ring. The LSI chip 1 is electrically connected to the ceramic substarate 4 via a bump electrode 5 formed on the pad electrode 3. Thus, it is possible to simplify the case and prevent the heat increase of the LSI chip 1.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体集積回路装置の
誘電体基板への実装方法に関し、特にシールリングによ
りＬＳＩチップを気密封止する半導体集積回路装置およ
びその実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor integrated circuit device on a dielectric substrate, and more particularly to a semiconductor integrated circuit device in which an LSI chip is hermetically sealed by a seal ring and a mounting method thereof.

【０００２】[0002]

【従来の技術】従来、この種の半導体集積回路装置の誘
電体基板への実装方法は、ＬＳＩチップの電極にワイヤ
を用いず、電気的に導通な球状の電極、すなわちバンプ
電極を用いてフリップチップ実装されている。2. Description of the Related Art Conventionally, a method of mounting a semiconductor integrated circuit device of this type on a dielectric substrate is flipped by using electrically conductive spherical electrodes, that is, bump electrodes, without using wires for electrodes of an LSI chip. Chip mounted.

【０００３】図３は従来の半導体集積回路装置を示す断
面図である。図３において、ＬＳＩチップ１は半田によ
り形成されたバンプ電極５を介して誘電体基板、すなわ
ちセラミック基板４と電気的に接続されている。また、
ＬＳＩチップ１の周囲はキャップ１１により覆われ、気
密封止されている。キャップ１１は導電性接着剤１２に
よりセラミック基板４に固定されている。FIG. 3 is a sectional view showing a conventional semiconductor integrated circuit device. In FIG. 3, the LSI chip 1 is electrically connected to a dielectric substrate, that is, a ceramic substrate 4 via bump electrodes 5 formed of solder. Also,
The periphery of the LSI chip 1 is covered with a cap 11 and hermetically sealed. The cap 11 is fixed to the ceramic substrate 4 with a conductive adhesive 12.

【０００４】図３に示す半導体集積回路装置は、バンプ
電極５だけが主要な放熱経路なため、ＬＳＩチップ１の
熱上昇が大きく、チップが破壊されるという問題があ
る。In the semiconductor integrated circuit device shown in FIG. 3, since only the bump electrode 5 is the main heat radiation path, there is a problem that the LSI chip 1 has a large heat rise and the chip is destroyed.

【０００５】上述した問題を解決するため、例えば、１
９９１年２月１４日公開の特開平３−３４４４５号公報
（文献１）に示されるように、ＬＳＩチップの裏面をキ
ャップに接着させ、キャップ側面に開講部を設ける構造
が知られている。To solve the above problem, for example, 1
As disclosed in Japanese Patent Application Laid-Open No. 3-34445 (reference 1) published on February 14, 991, a structure is known in which the back surface of an LSI chip is adhered to a cap and the opening portion is provided on the side surface of the cap.

【０００６】図４は文献１第２図記載の半導体集積回路
装置を示す断面図である。図４において、ＬＳＩチップ
１の裏面が導電性接着剤１２によりキャップ１１に直接
接着されており、またキャップ１１の側面には開口部１
３が形成されている。さらにＬＳＩチップ１の表面に造
り込まれた素子領域を気密封止するためにモジュ−ルケ
ース１４によりキャップ１１およびセラミック基板４が
覆われている。このような構造を採用することにより、
バンプ電極５、およびキャップ１による放熱経路が形成
され、ＬＳＩチップ１の熱上昇を防止することができ
る。FIG. 4 is a sectional view showing a semiconductor integrated circuit device described in FIG. In FIG. 4, the back surface of the LSI chip 1 is directly adhered to the cap 11 by the conductive adhesive 12, and the side surface of the cap 11 has the opening 1
3 is formed. Further, the module case 14 covers the cap 11 and the ceramic substrate 4 to hermetically seal the element region formed on the surface of the LSI chip 1. By adopting such a structure,
A heat dissipation path is formed by the bump electrode 5 and the cap 1, and the heat rise of the LSI chip 1 can be prevented.

【０００７】しかしながら、この文献１記載の半導体集
積回路装置はキャップ１１に開口部１３が形成されてい
るため、大型のモジュールケース１４による気密封止が
必要となり、装置の大型化、および高価格化という問題
がある。However, since the semiconductor integrated circuit device described in Document 1 has the opening 13 formed in the cap 11, it is necessary to hermetically seal the device with a large module case 14, resulting in an increase in size and cost of the device. There is a problem.

【０００８】さらに、上述した問題を解決するために、
例えば、１９９２年１２月９日公開の特開平４−３５５
９３７号公報（文献２）に示されるように、あらかじ
め、キャップにＬＳＩチップを接着後、キャップ封止と
ＬＳＩチップのバンプ電極接続を同時におこなうという
半導体集積回路装置が知られている。Further, in order to solve the above-mentioned problems,
For example, Japanese Patent Laid-Open No. 4-355, published on December 9, 1992.
As disclosed in Japanese Patent No. 937 (reference 2), a semiconductor integrated circuit device is known in which an LSI chip is bonded to a cap in advance, and then cap sealing and bump electrode connection of the LSI chip are simultaneously performed.

【０００９】図５は文献２記載の半導体集積回路装置を
示す断面図である。図５において、ＬＳＩチップ１は導
電性のバンプ電極５を介してセラミック基板４に接続さ
れ、キャップ１１がＬＳＩチップ１の裏面に直接導電性
接着剤１２により接着されている。また、キャップ１１
は導電性接着剤１２によりセラミック基板４に接続され
ている。FIG. 5 is a sectional view showing a semiconductor integrated circuit device described in Reference 2. In FIG. 5, the LSI chip 1 is connected to the ceramic substrate 4 via the conductive bump electrodes 5, and the cap 11 is directly bonded to the back surface of the LSI chip 1 with the conductive adhesive 12. Also, the cap 11
Are connected to the ceramic substrate 4 by a conductive adhesive 12.

【００１０】[0010]

【発明が解決しようとする課題】この従来の文献２記載
の半導体集積回路装置は、半導体集積回路装置の基板４
への実装とキャップ１１による気密封止を同時に行うこ
とができるため、キャップ封止行程が省略できる。しか
しながら、キャップ１１にＬＳＩチップ１を接着する行
程が新たに必要となるため、全体の行程は決して少なく
ならないという課題がある。また、上述した３つの従来
技術の半導体集積回路装置はキャップを必要とするた
め、組立後の重量がかさむという課題がある。The conventional semiconductor integrated circuit device described in Document 2 is a substrate 4 of the semiconductor integrated circuit device.
Since it can be mounted on the substrate and hermetically sealed by the cap 11, the cap sealing step can be omitted. However, there is a problem in that the process of adhering the LSI chip 1 to the cap 11 is newly required, so that the total process is never reduced. In addition, the above-mentioned three conventional semiconductor integrated circuit devices require a cap, and thus there is a problem that the weight after assembly is heavy.

【００１１】[0011]

【課題を解決するための手段】本発明の目的は、上述し
た欠点を除去し、ケースの簡略化およびＬＳＩチップの
熱上昇を防止する半導体集積回路装置およびその実装方
法を提供することにある。上記目的を達成するために本
発明の半導体集積回路装置およびその実装方法では、パ
ッド電極の周囲のシールリングと接着する領域と、セラ
ミック基板のパターンとをシールリングを介して接続さ
せることにより気密封止を行うとともに、バンプ電極を
介して電気的接続を得るという構造および実装方法を採
用することにより上記目的を達成している。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device which eliminates the above-mentioned drawbacks, simplifies the case, and prevents heat rise of an LSI chip, and a mounting method thereof. In order to achieve the above object, in a semiconductor integrated circuit device and a mounting method thereof according to the present invention, a region around a pad electrode, which is bonded to a seal ring, and a pattern of a ceramic substrate are connected via a seal ring to hermetically seal. The above object is achieved by adopting a structure and a mounting method in which the electrical connection is obtained through the bump electrode while performing the stop.

【００１２】[0012]

【実施例】次に本発明を図面を参照して詳細に説明す
る。The present invention will now be described in detail with reference to the drawings.

【００１３】図１は本発明の一実施例を示す半導体集積
回路装置の断面図である。図１ａ図において、ＬＳＩチ
ップ１はシールリング２を介してセラミック基板４のパ
ターン１０に接続され、ＬＳＩチップ１およびシールリ
ング２によりＬＳＩチップ１上に設けられた素子領域
７、およびパッド電極３を気密封止している。シールリ
ング２はコバールもしくは銅タングステンにより形成さ
れている。また、ＬＳＩチップ１はパッド電極３上に形
成されたバンプ電極５を介してセラミック基板４と電気
的に接続されている。FIG. 1 is a sectional view of a semiconductor integrated circuit device showing an embodiment of the present invention. In FIG. 1 a, the LSI chip 1 is connected to the pattern 10 of the ceramic substrate 4 via the seal ring 2, and the device region 7 and the pad electrode 3 provided on the LSI chip 1 are connected by the LSI chip 1 and the seal ring 2. It is hermetically sealed. The seal ring 2 is made of Kovar or copper tungsten. Further, the LSI chip 1 is electrically connected to the ceramic substrate 4 via bump electrodes 5 formed on the pad electrodes 3.

【００１４】図１ｂ図は、図１ａ図におけるＸ−Ｘ’面
における横断面から見たＬＳＩチップの上面図である。
ＬＳＩチップ１の周辺端部にシールリング２がパッド電
極３を取り囲むようにして接続されている。FIG. 1b is a top view of the LSI chip seen from the cross section taken along the line XX 'in FIG. 1a.
A seal ring 2 is connected to the peripheral edge of the LSI chip 1 so as to surround the pad electrode 3.

【００１５】ＬＳＩチップ１がシリコン組成の場合は線
膨張係数が３．６ｐｐｍ／℃であり、セラミック基板４
の線膨張係数が７．１ｐｐｍ／℃である。また、シール
リングの組成であるコバールあるいは銅タングステンの
線膨張係数は６ｐｐｍ／℃であるため、膨張係数が近
く、接着の際の熱による歪等が生じず、信頼性の高い接
合を得ることができる。また、ＬＳＩチップがＧａＡｓ
組成の場合は線膨張係数が７ｐｐｍ／℃であるため、さ
らに良好の接合を得ることができる。When the LSI chip 1 has a silicon composition, the linear expansion coefficient is 3.6 ppm / ° C., and the ceramic substrate 4
Has a linear expansion coefficient of 7.1 ppm / ° C. In addition, since the linear expansion coefficient of Kovar or copper-tungsten, which is the composition of the seal ring, is 6 ppm / ° C, the expansion coefficient is close, and distortion due to heat during bonding does not occur, so that highly reliable bonding can be obtained. it can. Also, the LSI chip is GaAs
In the case of the composition, the coefficient of linear expansion is 7 ppm / ° C., so that a better bond can be obtained.

【００１６】図２は図１に示した半導体集積回路装置の
実装方法を説明する断面図である。図２において、まず
行程（ａ）によりシールリング２をＬＳＩチップ１にＡ
ｕＳｉ８で接着した後、行程（ｂ）によりＬＳＩチップ
１のパッド電極３にバンブ電極５を半田により形成す
る。次に行程（ｃ）によりＬＳＩチップ１をセラミック
基板４に接着する際に、シールリング２とセラミック基
板４上のパターン１０との間に半田プリフォーム９を挿
入、加熱し、ＬＳＩチップ１上に形成されたバンブ電極
５と、接着されたシールリング２に対して、セラミック
基板４のそれぞれに対応するパターン１０とを接続す
る。上述の行程を経て、（ｄ）に示す本発明の一実施例
である半導体集積回路装置を得る。FIG. 2 is a sectional view for explaining a method of mounting the semiconductor integrated circuit device shown in FIG. In FIG. 2, first, the seal ring 2 is attached to the LSI chip 1 by the step (a).
After bonding with uSi8, bump electrodes 5 are formed on the pad electrodes 3 of the LSI chip 1 by soldering in the step (b). Next, when the LSI chip 1 is bonded to the ceramic substrate 4 in the step (c), the solder preform 9 is inserted between the seal ring 2 and the pattern 10 on the ceramic substrate 4 and heated, and the LSI chip 1 is heated on the LSI chip 1. The formed bump electrodes 5 and the bonded seal ring 2 are connected to the patterns 10 corresponding to the respective ceramic substrates 4. Through the steps described above, the semiconductor integrated circuit device according to the embodiment of the present invention shown in (d) is obtained.

【００１７】上述したこれらの組立行程例は本発明の実
現性を裏付けるために示したものであり、他の組立行程
例として、シールリング２を先にセラミック基板４に接
続する方法、およびＬＳＩチップ１、シールリング２お
よびセラミック基板４とを同時に接着する方法等が使用
でき、本発明を何等制限するものではない。The above-described examples of the assembling steps are shown to support the feasibility of the present invention. As another example of the assembling steps, a method of connecting the seal ring 2 to the ceramic substrate 4 first, and an LSI chip. 1, a method of simultaneously adhering the seal ring 2 and the ceramic substrate 4 can be used, and the present invention is not limited thereto.

【００１８】[0018]

【発明の効果】以上説明したように、本発明による半導
体集積回路装置の実装方法は、ＬＳＩチップとセラミッ
ク基板とをシールリングにより直接接続することで、気
密封止を可能としたため、キャップを用いた気密封止と
比較して組立後の重量が１〜２割程度軽減できるという
効果を有する。また、モジュールサイズの気密封止も不
要なため、ケースの簡略化ができ、さらに、フリップチ
ップ実装でのバンブ電極以外にシールリングでの放熱経
路が得られるため、ＬＳＩチップの熱上昇を防止するこ
とができるという効果を有する。As described above, in the method of mounting a semiconductor integrated circuit device according to the present invention, since the LSI chip and the ceramic substrate are directly connected to each other by the seal ring to enable hermetic sealing, the cap is used. It has an effect that the weight after assembly can be reduced by about 10 to 20% as compared with the hermetic sealing. Further, since the module size does not need to be hermetically sealed, the case can be simplified, and a heat dissipation path can be obtained by the seal ring in addition to the bump electrodes in flip chip mounting, so that the heat rise of the LSI chip is prevented. It has the effect of being able to.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例を示す半導体集積回路装置の
断面図。FIG. 1 is a sectional view of a semiconductor integrated circuit device showing an embodiment of the present invention.

【図２】図１に示した半導体集積回路装置の組立行程例
を示す断面図。FIG. 2 is a sectional view showing an example of an assembling process of the semiconductor integrated circuit device shown in FIG.

【図３】従来の半導体集積回路装置を示す断面図。FIG. 3 is a sectional view showing a conventional semiconductor integrated circuit device.

【図４】他の従来の半導体集積回路装置を示す断面図。FIG. 4 is a sectional view showing another conventional semiconductor integrated circuit device.

【図５】他の従来の半導体集積回路装置の実装方法を示
す断面図FIG. 5 is a cross-sectional view showing another conventional method for mounting a semiconductor integrated circuit device.

【符号の説明】[Explanation of symbols]

１ ＬＳＩチップ ２ シールリング ３ パッド電極 ４ セラミック基板 ５ バンプ電極 ７ 素子領域 ８ ＡｕＳｉ ９ 半田プリフォーム １０ セラミック基盤上のパターン １１ キャップ １２ 導電性接着剤 １３ 開口部 １４ モジュールケース 1 LSI Chip 2 Seal Ring 3 Pad Electrode 4 Ceramic Substrate 5 Bump Electrode 7 Element Area 8 AuSi 9 Solder Preform 10 Pattern on Ceramic Substrate 11 Cap 12 Conductive Adhesive 13 Opening 14 Module Case

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 ＬＳＩチップと誘電体基板とをバンプ電
極を用いてフリップチップ実装する半導体集積回路の実
装方法において、前記ＬＳＩチップと前記誘電体基板と
に接続されるシールリングを用いて前記ＬＳＩチップの
素子領域およびパッド電極を気密封止することを特徴と
する半導体集積回路装置の実装方法。1. A method for mounting a semiconductor integrated circuit, wherein an LSI chip and a dielectric substrate are flip-chip mounted using bump electrodes, wherein the LSI is formed by using a seal ring connected to the LSI chip and the dielectric substrate. A method for mounting a semiconductor integrated circuit device, characterized in that an element region of a chip and a pad electrode are hermetically sealed. 【請求項２】 バンプ電極が形成された誘電体基板と、
前記バンプ電極周辺のシールリングを介してフリップチ
ップ実装されたＬＳＩチップとから構成されたことを特
徴とする半導体集積回路装置。2. A dielectric substrate having bump electrodes formed thereon,
A semiconductor integrated circuit device comprising an LSI chip flip-chip mounted via a seal ring around the bump electrode. 【請求項３】 前記シールリングが、コバールあるいは
銅タングステンを組成とすることを特徴とする請求項２
記載の半導体集積装置回路。3. The seal ring is composed of Kovar or copper-tungsten.
The semiconductor integrated device circuit described. 【請求項４】 前記シールリングが、前記パッド電極の
周囲に設けられた前記シールリング接着用の領域と、前
記誘電体基板のパターンとに接続されることを特徴とす
る請求項３記載の半導体集積回路装置。4. The semiconductor according to claim 3, wherein the seal ring is connected to a region for bonding the seal ring provided around the pad electrode and a pattern of the dielectric substrate. Integrated circuit device. 【請求項５】 前記シールリングが、前記ＬＳＩチップ
の周辺端部に接続されていることを特徴とする請求項４
記載の半導体集積回路装置。5. The seal ring is connected to a peripheral end portion of the LSI chip.
The semiconductor integrated circuit device described. 【請求項６】 前記シールリングが、前記パッド電極を
取り囲むようにして前記ＬＳＩチップの素子領域および
前記パッド電極を気密封止することを特徴とする請求項
５記載の半導体集積回路装置。6. The semiconductor integrated circuit device according to claim 5, wherein the seal ring hermetically seals the element region of the LSI chip and the pad electrode so as to surround the pad electrode.
JP5295842A 1993-11-26 1993-11-26 Semiconductor integrated circuit device and mounting method thereof Expired - Fee Related JP2669310B2 (en)

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JP5295842A JP2669310B2 (en) 1993-11-26 1993-11-26 Semiconductor integrated circuit device and mounting method thereof

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Application Number Priority Date Filing Date Title
JP5295842A JP2669310B2 (en) 1993-11-26 1993-11-26 Semiconductor integrated circuit device and mounting method thereof

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JPH07147299A true JPH07147299A (en) 1995-06-06
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007299900A (en) * 2006-04-28 2007-11-15 Kawasaki Microelectronics Kk Semiconductor device and method of preventing dielectric breakdown of semiconductor device
US7301243B2 (en) 2004-08-30 2007-11-27 Sharp Kabushiki Kaisha High-reliable semiconductor device using hermetic sealing of electrodes

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62217619A (en) * 1986-03-19 1987-09-25 Hitachi Ltd Chip carrier with pin
JPH0281447A (en) * 1988-09-16 1990-03-22 Hitachi Ltd Flexible pin carrier and semiconductor device employing the same
JPH0430544A (en) * 1990-05-28 1992-02-03 Hitachi Ltd Integrated circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62217619A (en) * 1986-03-19 1987-09-25 Hitachi Ltd Chip carrier with pin
JPH0281447A (en) * 1988-09-16 1990-03-22 Hitachi Ltd Flexible pin carrier and semiconductor device employing the same
JPH0430544A (en) * 1990-05-28 1992-02-03 Hitachi Ltd Integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7301243B2 (en) 2004-08-30 2007-11-27 Sharp Kabushiki Kaisha High-reliable semiconductor device using hermetic sealing of electrodes
CN100401504C (en) * 2004-08-30 2008-07-09 夏普株式会社 High-reliable semiconductor device using hermetic sealing of electrodes
JP2007299900A (en) * 2006-04-28 2007-11-15 Kawasaki Microelectronics Kk Semiconductor device and method of preventing dielectric breakdown of semiconductor device

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