JPH01117049A - Integrated circuit element cooling device - Google Patents
Integrated circuit element cooling deviceInfo
- Publication number
- JPH01117049A JPH01117049A JP62273041A JP27304187A JPH01117049A JP H01117049 A JPH01117049 A JP H01117049A JP 62273041 A JP62273041 A JP 62273041A JP 27304187 A JP27304187 A JP 27304187A JP H01117049 A JPH01117049 A JP H01117049A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- sealing cap
- cap
- chip
- circuit element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001816 cooling Methods 0.000 title claims description 15
- 238000007789 sealing Methods 0.000 claims abstract description 40
- 229910000679 solder Inorganic materials 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 7
- 238000009429 electrical wiring Methods 0.000 claims 1
- 230000008646 thermal stress Effects 0.000 abstract description 10
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000005476 soldering Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29011—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29075—Plural core members
- H01L2224/29078—Plural core members being disposed next to each other, e.g. side-to-side arrangements
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はコンピュータなどに装備される集積回路素子の
冷却装置の改良に係り、特に集積回路素子の接続部にか
かる熱応力を緩和すると共に、集積回路素子封止用高熱
伝導性キャップと集積回路素子との接合を常に安定に保
つための手段を具備した集積回路素子用冷却装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a cooling device for an integrated circuit device installed in a computer or the like, and in particular, to alleviate thermal stress applied to the connection portion of an integrated circuit device, The present invention relates to a cooling device for an integrated circuit device that includes a means for always maintaining stable bonding between a highly thermally conductive cap for sealing an integrated circuit device and the integrated circuit device.
第６図は従来の集積回路素子用冷却装置の構成を示す要
部側断面図である。同図に示すように、集積回路素子（
以下チップと称する）１は、基板２に半田ボール３によ
って電気的接続と、機械的接続が行われ、封止キャップ
４をかぶせ気密封止が行われている。一般に、封止キャ
ップ４．基板２、チップ１は、各々熱膨張係数が異なる
ため、チップ１が発熱すると、各部に熱応力が発生する
。FIG. 6 is a sectional side view of a main part showing the configuration of a conventional cooling device for integrated circuit elements. As shown in the figure, integrated circuit elements (
1 (hereinafter referred to as a chip) is electrically and mechanically connected to a substrate 2 by solder balls 3, and is hermetically sealed by covering with a sealing cap 4. Generally, the sealing cap 4. Since the substrate 2 and the chip 1 have different coefficients of thermal expansion, when the chip 1 generates heat, thermal stress is generated in each part.
半田ボールの外径は、約１００μｍ程度と微細なので、
半田ボール３に歪ができるだけ加わらないようにするた
め、チップ１の背面と封止キャップ４内面との間に小さ
な隙間が設けられている。しかし、熱応力緩和の点で優
れているが、チップ１から発生する熱は、封止キャップ
に伝わりにくい構造になっている。従って、チップの発
熱量は、冷却性能上制限されてしまう。The outer diameter of the solder ball is minute, about 100 μm, so
In order to prevent distortion from being applied to the solder balls 3 as much as possible, a small gap is provided between the back surface of the chip 1 and the inner surface of the sealing cap 4. However, although it is excellent in terms of thermal stress relaxation, it has a structure that makes it difficult for the heat generated from the chip 1 to be transmitted to the sealing cap. Therefore, the amount of heat generated by the chip is limited in terms of cooling performance.
そこで、特開昭５７−２１８４５号公報に記載されてい
る集積回路素子の冷却構造が提案されている。Therefore, a cooling structure for integrated circuit elements has been proposed, which is described in Japanese Patent Application Laid-Open No. 57-21845.
この場合、第５図の構造に対して、チップ］−の背面と
封止キャップ４の内面が、高熱伝導性接着材あるいは半
田などによって互いに接合されている。In this case, with respect to the structure shown in FIG. 5, the back surface of the chip and the inner surface of the sealing cap 4 are bonded to each other with a highly thermally conductive adhesive, solder, or the like.
しかし、チップ１は封止キャップ４に固着されるので、
チップ接続用半田ボール３に熱応力が直接加わってしま
う。チップ１の熱は封止キャップ４に良好に伝わるが、
半田ボール３の接続寿命は著しく低下してしまう。また
、チップ背面のようにある程度の大きさの接合面積にな
ると、接合層内には、不確定な大きさの気泡が混入して
しまう。However, since the chip 1 is fixed to the sealing cap 4,
Thermal stress is directly applied to the solder balls 3 for chip connection. Although the heat of the chip 1 is transferred well to the sealing cap 4,
The connection life of the solder balls 3 will be significantly reduced. Further, when the bonding area is a certain size such as the back surface of a chip, air bubbles of uncertain size are mixed into the bonding layer.
必ずしも決った大きさの気泡が混入するわけでないため
、せっかく高熱伝導性の接着材や半田などによって、チ
ップとキャップを接合しても、接合層の熱抵抗はばらつ
いてしまう。近年、集積回路素子の集積度が著しく増大
しているため発熱量も数十Ｗにも達する。わずか０．１
℃／Ｗの熱抵抗が生じても、チップの温度は数度も変
動してしまう。Since air bubbles of a fixed size are not necessarily mixed in, even if the chip and cap are bonded using a highly thermally conductive adhesive or solder, the thermal resistance of the bonding layer will vary. In recent years, as the degree of integration of integrated circuit elements has increased significantly, the amount of heat generated has reached several tens of watts. Only 0.1
Even if a thermal resistance of °C/W occurs, the temperature of the chip will fluctuate by several degrees.
しかしながら、上記従来の集積回路素子用冷却装置の場
合は、半田ボールに加わる熱応力を緩和しながら、かつ
チップの熱を効果的に封止キャップに伝えることができ
ない。また、たとえ、熱を良く導くためにチップと封止
キャップとを互いに接合すると、接合層内に気密が残存
し、残留気泡の大きさは必ずしも決った大きさにならず
、接合層の熱抵抗は増大し、その増加量も安定しない問
題があった。However, in the case of the above-mentioned conventional integrated circuit device cooling device, it is not possible to effectively transfer the heat of the chip to the sealing cap while alleviating the thermal stress applied to the solder balls. In addition, even if the chip and the sealing cap are bonded to each other in order to conduct heat well, airtightness remains in the bonding layer, and the size of the residual bubbles is not necessarily a fixed size, and the thermal resistance of the bonding layer increases, and the amount of increase is also unstable.
本発明の目的は、熱応力緩和と冷却性能向上。The purpose of the present invention is to alleviate thermal stress and improve cooling performance.
及び冷却性能の安定を同時に達成する集積回路素子の冷
却装置を提供することにある。An object of the present invention is to provide a cooling device for an integrated circuit device that simultaneously achieves stable cooling performance.
かかる目的達成のため、本発明は、チップ背面と封止キ
ャップ内面にある決まった大きさで、細かく分割したメ
タライズ層を設け、両者メタライズ層を互いに向かい合
わせになるように配置し、かつチップと封止キャップを
ハンダ等の高熱伝導性接合材によって互いに接合するも
のである。To achieve this objective, the present invention provides finely divided metallized layers of a predetermined size on the back surface of the chip and the inner surface of the sealing cap, and arranges both metallized layers to face each other, and to The sealing caps are bonded together using a highly thermally conductive bonding material such as solder.
このように構成されたものは、チップと封止キャップ間
の隙間をハンダ等によって全面的に接合されているわけ
でないので、封止キャップや基板及びチップなどの材料
の熱膨張率の違いによって発生する熱応力は、すべて半
田ボールに加わらず、細かく分割した接合層によって緩
和される。In devices configured in this way, the gap between the chip and the sealing cap is not completely joined with solder, etc., so thermal expansion coefficients of materials such as the sealing cap, substrate, and chip may occur due to differences in thermal expansion coefficients. All of the thermal stress that occurs is not applied to the solder balls, but is alleviated by the finely divided bonding layer.
また、細かく分割したメタライズ層によって、接合層の
大きさは規定され、接合層は細かく分散されるので、接
合層に気泡が混入せず、接合層の熱抵抗の変動は無視で
きるほど小さく押えることができる。更に、チップから
接合層にあるいは接合層から封止キャップに、熱が伝わ
る際発生する熱伝導収縮熱抵抗や拡大熱抵抗も非常に小
さく押えることができる。In addition, the size of the bonding layer is regulated by the finely divided metallized layer, and the bonding layer is finely dispersed, so air bubbles are not mixed into the bonding layer, and fluctuations in the thermal resistance of the bonding layer can be suppressed to a negligible level. Can be done. Furthermore, the thermal conduction shrinkage thermal resistance and expansion thermal resistance that occur when heat is transferred from the chip to the bonding layer or from the bonding layer to the sealing cap can be kept very small.
以下、本発明の実施例を第１図〜第３図の図面に基づい
て詳細に説明する。Hereinafter, embodiments of the present invention will be described in detail based on the drawings of FIGS. 1 to 3.
第１図は本発明による集積回路素子用冷却装置の一実施
例を示す要部側断面図、第２図は第１図の封止キャップ
内面の正面図である。なお、第１図、第５図と同一部分
に同一符号を付して説明するものである。FIG. 1 is a sectional side view of a main part showing an embodiment of the cooling device for integrated circuit elements according to the present invention, and FIG. 2 is a front view of the inner surface of the sealing cap shown in FIG. 1. Note that the same parts as in FIGS. 1 and 5 will be described with the same reference numerals.
第１図と第２図、第３図に示すように、本発明の集積回
路素子用冷却装置は、チップ１の背面及び封止キャップ
４の内面の半田接合面上に、細かく分割した正方形ある
いは円形の格子状のメタライズ層５ａ、５ｂが互いに向
かい合う位置に設けられている。なお、チップ搭載用の
基板２及び封止キャップ４はセラミック製である。特に
、封止キャップ４は高熱伝導性と電気絶縁性を共に兼ね
備えて持つことが必要である。このため高熱伝導性窒化
アルミ（Ａ Ｑ Ｎ）あるいはＢｅ入力の高熱伝導性Ｓ
ｉＣが用いられる。封止キャップ４を基板２に半田によ
って気密封止する際、封止キャップ４とチップ１とは、
あらかじめ各分割メタライズ層６に迎え半田をした半田
層７を溶解することによって接合することができる。こ
のため、封止キャップ４の気密封止用半田８と、チップ
１と封止キャップ４との接合半田７とは同一のものを用
いる方が好ましい。As shown in FIGS. 1, 2, and 3, the integrated circuit device cooling device of the present invention has finely divided squares or Circular lattice-shaped metallized layers 5a and 5b are provided at positions facing each other. Note that the chip mounting substrate 2 and the sealing cap 4 are made of ceramic. In particular, the sealing cap 4 needs to have both high thermal conductivity and electrical insulation. For this reason, high thermal conductivity aluminum nitride (AQN) or high thermal conductivity S with Be input is used.
iC is used. When the sealing cap 4 is hermetically sealed to the substrate 2 by soldering, the sealing cap 4 and the chip 1 are
Bonding can be achieved by melting a solder layer 7 that has been soldered onto each divided metallized layer 6 in advance. For this reason, it is preferable to use the same solder 8 for hermetically sealing the sealing cap 4 and the bonding solder 7 between the chip 1 and the sealing cap 4.
又、第４図に示す他の実施例においては、第１図の実施
例に示すセラミック製封止キャップの代りにセラミック
の体膨張率の値に近い、Ｃｕ−Ｗ。In another embodiment shown in FIG. 4, the sealing cap made of ceramic shown in the embodiment of FIG. 1 is replaced by Cu-W, which has a coefficient of expansion close to that of ceramic.
Ｃｕ −Ｍ ｏ 、コバール、４２７０イ、インバータ
などの金属材料を封止キャップ材に選んだ場合を示すも
のである。金属製封止キャップの場合、半田付けを容易
にするため封止キャップ４の内面にＮｉ Ａｕなどの
メツキを行った後、第５図に示すように多角形、あるい
は円形状に半田付は部９をくり抜いた格子部１０にＰＩ
Ｑなどの半田付は防止用のレジスト膜を設けている。This figure shows a case where a metal material such as Cu-Mo, Kovar, 4270I, or inverter is selected as the sealing cap material. In the case of a metal sealing cap, the inner surface of the sealing cap 4 is plated with Ni-Au to facilitate soldering, and then the soldering part is shaped into a polygonal or circular shape as shown in Figure 5. PI in the lattice part 10 which hollowed out 9.
A resist film is provided to prevent soldering such as Q.
上記のとおり、本発明によれば、集積回路素子は、封止
キャップにより外部環境から保護され、確実に封止され
ると共に、半田ボールに加わる熱応力を緩和させながら
、かつ集積回路素子の発熱量を封止キャップに効率良く
伝えることができる。As described above, according to the present invention, the integrated circuit element is protected from the external environment by the sealing cap, and is reliably sealed, while also relieving the thermal stress applied to the solder balls and reducing the heat generated by the integrated circuit element. The amount can be efficiently transmitted to the sealing cap.
また、集積回路素子と封止キャップとを細かく分割して
接合するので、接合層内に接合時に混入する気泡が残存
することがなくなり、接合層の熱抵抗を安定に保つこと
ができる。Furthermore, since the integrated circuit element and the sealing cap are finely divided and bonded, there are no air bubbles that are mixed into the bonding layer during bonding, and the thermal resistance of the bonding layer can be kept stable.
第１図は本発明の実施例を示す要部側断面図、第２図、
第３図は夫々封止キャップ内面のメタライズ層の形状を
示す正面図、第４図は本発明の他の実施例を示す要部側
断面図、第５図は封止キャップ内面のレジスト層の形状
を示す正面図、第６図は従来の集積回路素子冷却装置を
示す要部側断面図である。
１・・・集積回路素子、２・・・配線基板、３・・・半
田ボール、４・・・封止キャップ、５・・・メタライズ
層、７・・・＼ｊ ＋＋０１Ｓｌ へ
壌 ３ 医
第 ＝＋ 図
第 ５ 口
３−半田ホ゛ゝル ８ 気茹封止ｉ晶４・−封止キ
ャ・ツブ ｒＯ＃チ部FIG. 1 is a side sectional view of the main part showing an embodiment of the present invention, FIG.
3 is a front view showing the shape of the metallized layer on the inner surface of the sealing cap, FIG. 4 is a sectional side view of the main part showing another embodiment of the present invention, and FIG. 5 is a front view showing the shape of the metallized layer on the inner surface of the sealing cap. A front view showing the shape, and FIG. 6 is a side sectional view of the main part showing a conventional integrated circuit device cooling device. DESCRIPTION OF SYMBOLS 1... Integrated circuit element, 2... Wiring board, 3... Solder ball, 4... Sealing cap, 5... Metallized layer, 7... + Figure 5 Port 3 - Solder hole 8 Air-boiled sealing crystal 4 - Sealing cap rO # Chi part
Claims (1)
線基板上に半田ボールによって実装し、上記集積回路素
子チップを覆うように封止キャップによつて気密封止す
る集積回路素子冷却装置において、集積回路素子チップ
背面と封止キャップ内面とを互いに高熱伝導性接合材に
よつて、細かく分割して接合したことを特徴とする集積
回路素子冷却装置。1. An integrated circuit device cooling device in which at least one integrated circuit device chip is mounted on an electrical wiring board using solder balls, and hermetically sealed with a sealing cap covering the integrated circuit device chip. 1. An integrated circuit device cooling device characterized in that a back surface of a circuit device chip and an inner surface of a sealing cap are finely divided and bonded to each other using a highly thermally conductive bonding material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62273041A JPH01117049A (en) | 1987-10-30 | 1987-10-30 | Integrated circuit element cooling device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62273041A JPH01117049A (en) | 1987-10-30 | 1987-10-30 | Integrated circuit element cooling device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01117049A true JPH01117049A (en) | 1989-05-09 |
Family
ID=17522342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62273041A Pending JPH01117049A (en) | 1987-10-30 | 1987-10-30 | Integrated circuit element cooling device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01117049A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03182397A (en) * | 1989-12-12 | 1991-08-08 | Mitsubishi Electric Corp | Ic card |
| EP0812015A1 (en) * | 1996-06-04 | 1997-12-10 | MAGNETI MARELLI S.p.A. | A heat dissipator for integrated circuits |
| US6118177A (en) * | 1998-11-17 | 2000-09-12 | Lucent Technologies, Inc. | Heatspreader for a flip chip device, and method for connecting the heatspreader |
| US6362437B1 (en) | 1999-06-17 | 2002-03-26 | Nec Corporation | Mounting structure of integrated circuit device having high effect of buffering stress and high reliability of connection by solder, and method of mounting the same |
| US6429512B1 (en) * | 1999-03-16 | 2002-08-06 | Siliconware Precision Industries Co., Ltd. | Ball grid array integrated circuit package with palladium coated heat-dissipation device |
| EP1450402A1 (en) * | 2003-02-21 | 2004-08-25 | Fujitsu Limited | Semiconductor device with improved heat dissipation, and a method of making semiconductor device |
| JP2008053350A (en) * | 2006-08-23 | 2008-03-06 | Denso Corp | Sensor device, and its manufacturing method |
| WO2014034306A1 (en) * | 2012-08-29 | 2014-03-06 | 日立オートモティブシステムズ株式会社 | Electronic control device |
| JP2016178235A (en) * | 2015-03-20 | 2016-10-06 | 日本電気株式会社 | Thermal conductive member, cooling structure, and device |
| EP3478045A4 (en) * | 2016-06-28 | 2020-02-19 | Zeon Corporation | Heat dissipating device |
| EP3758058A1 (en) * | 2019-06-25 | 2020-12-30 | Intel Corporation | Microelectronic package with solder array thermal interface material (sa-tim) |
-
1987
- 1987-10-30 JP JP62273041A patent/JPH01117049A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03182397A (en) * | 1989-12-12 | 1991-08-08 | Mitsubishi Electric Corp | Ic card |
| EP0812015A1 (en) * | 1996-06-04 | 1997-12-10 | MAGNETI MARELLI S.p.A. | A heat dissipator for integrated circuits |
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