JPH09213847A - Semiconductor integrated circuit device, manufacture thereof, and electronic device equipped therewith - Google Patents

Semiconductor integrated circuit device, manufacture thereof, and electronic device equipped therewith

Info

Publication number
JPH09213847A
JPH09213847A JP1630296A JP1630296A JPH09213847A JP H09213847 A JPH09213847 A JP H09213847A JP 1630296 A JP1630296 A JP 1630296A JP 1630296 A JP1630296 A JP 1630296A JP H09213847 A JPH09213847 A JP H09213847A
Authority
JP
Japan
Prior art keywords
semiconductor chip
integrated circuit
heat radiator
circuit device
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1630296A
Other languages
Japanese (ja)
Inventor
Akihisa Uchida
明久 内田
Toshihiko Sato
俊彦 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1630296A priority Critical patent/JPH09213847A/en
Publication of JPH09213847A publication Critical patent/JPH09213847A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

PROBLEM TO BE SOLVED: To enable an air-cooled LSI (large scale semiconductor integrated circuit device) to be lessened in thermal resistance and improved in heat dissipation efficiency. SOLUTION: A first heat dissipating body 6 which is formed of aluminum nitride(AlN), copper tungsten(CuW) or the like and very approximate to Si in thermal expansion coefficient and thermal conductivity is provided with a recess 7 at its center, a semiconductor chip 1 of Si is positioned in the recess 7 so as make its rear side 1a and side face 1C come into close contact with the heat dissipating body 6 through the intermediary of an adhesive layer 8 of silicone resin or solder excellent in thermal conductivity. For instance, a second heat dissipating body 9 of Cu or Al high in thermal conductivity is mounted on the first heat dissipating body 6 through the intermediary of another adhesive layer 8 of silicone resin or solder high in thermal conductivity.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体集積回路装
置及びこの製造方法並びにそれを用いた電子装置に関
し、特に、大電力用に使用する場合に放熱効率の改善を
図る半導体集積回路装置に適用して有効な技術に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, a method of manufacturing the same, and an electronic device using the same, and particularly to a semiconductor integrated circuit device for improving heat dissipation efficiency when used for high power. And about effective technology.

【0002】[0002]

【従来の技術】マイクロプロセッサで代表される最近の
LSI(大規模半導体集積回路装置)は、多くの機能が
要求されるにつれて集積度はより高まっており、ますま
す多ピン化の傾向にある。これに伴い半導体チップで大
量の熱が発生するので、この放熱対策が重要になってき
ている。
2. Description of the Related Art Recent LSIs (large-scale semiconductor integrated circuit devices) represented by microprocessors have a higher degree of integration as more functions are required, and the number of pins is increasing. As a result, a large amount of heat is generated in the semiconductor chip, and this heat dissipation measure is becoming important.

【0003】マイクロプロセッサは、低電力で動作する
MOS型トランジスタからなるCMOS、あるいはこの
CMOSを主要部に用いたBiCMOSなどで構成され
るのが主流になってきているが、放熱効率を改善するた
めに、そのパッケージは半導体チップの裏面に放熱体を
取り付けたBGA(Ball Grid Array)
やPGA(Pin Grid Array)からなる冷
却構造が採用されている。
The microprocessor is mainly composed of a CMOS including a MOS transistor operating at low power, or a BiCMOS using the CMOS as a main part, but in order to improve the heat radiation efficiency. In addition, the package is a BGA (Ball Grid Array) in which a radiator is attached to the back surface of the semiconductor chip.
A cooling structure made of PGA (Pin Grid Array) is adopted.

【0004】このようなマイクロプロセッサは、パソコ
ン(PC)、ワークステーション(WS)、メインフレ
ーム(MF)などの各種コンピュータシステムを含む電
子装置に組み込まれており、動作中に大量の熱を発生す
る。高性能のマイクロプロセッサを実現するためには、
それらの放熱対策が必須となる。
Such a microprocessor is incorporated in an electronic device including various computer systems such as a personal computer (PC), a workstation (WS) and a mainframe (MF), and generates a large amount of heat during operation. . In order to realize a high-performance microprocessor,
Measures to dissipate those heat are essential.

【0005】この放熱対策としては、水冷方式が一般的
に考えられるが、最近のコンピュータシステムは、限ら
れたスペースに収納可能なようにより小型化されたもの
の要求が高まっており、水冷方式は冷却のための付帯設
備を含めた構造が比較的大きくなるので省力化の点で問
題がある。このため、構造が比較的に簡単な空冷方式が
有利である。
A water-cooling method is generally considered as a measure for this heat dissipation. However, recent computer systems are more miniaturized so that they can be stored in a limited space, and there is an increasing demand for the water-cooling method. There is a problem in labor saving because the structure including the auxiliary equipment for is relatively large. For this reason, the air-cooling method having a relatively simple structure is advantageous.

【0006】マイクロプロセッサに例をあげると、最近
では50〜60W程度の消費電力を満たす大電力用のも
のが要求されているが、この程度のマイクロプロセッサ
を高性能で動作させるように空冷方式で実現するために
は、熱抵抗TはT≦1℃/Wが必要になる。
Taking a microprocessor as an example, recently, a high-power one satisfying a power consumption of about 50 to 60 W is demanded, but an air-cooling system is used to operate the microprocessor of this level with high performance. In order to realize it, the thermal resistance T needs to be T ≦ 1 ° C./W.

【0007】このような観点から、空冷方式によるLS
Iとして、CCB(Controlled Colla
pse Bonding)技術を利用することにより、
表面に複数の半田バンプ電極を設けた半導体チップの表
面側を前記半田バンプ電極を介して例えばセラミックな
どから構成されたベース基板にフェースダウンボンディ
ングするとともに、その裏面側を接着用半田を介して例
えばAlN(アルミニウムナイトライド)などから構成
された封止用キャップの裏面に接着した構造のパッケー
ジを備えたものが知られている。
From this point of view, the LS by the air cooling system is used.
CCB (Controlled Colla)
By using the pse Bonding technology,
The surface side of a semiconductor chip having a plurality of solder bump electrodes on its surface is face-down bonded to a base substrate made of, for example, ceramics via the solder bump electrodes, and its back surface side is bonded via an adhesive solder, for example. It is known that a package having a structure in which a sealing cap made of AlN (aluminum nitride) or the like is adhered to the back surface is used.

【0008】例えば、日経BP社発行、1993年5月
31日発行、「VLSIパッケージング技術(下)」、
P178には、そのような構造のパッケージを備えたL
SIが示されている。
For example, published by Nikkei BP, published on May 31, 1993, "VLSI packaging technology (lower)",
P178 is an L that has a package of such a structure.
SI is shown.

【0009】このような構造のパッケージは、MCC
(Micro Carrier for LSI Ch
ip、あるいはMicro Chip Carrie
r)と称されており、半導体チップで発生した熱は、そ
の裏面から熱伝導性に優れた接着用半田を介して封止用
キャップに伝達されて、同様に熱伝導性に優れた封止用
キャップから外部に放熱されるようになっている。
A package having such a structure is an MCC.
(Micro Carrier for LSI Ch
ip or Micro Chip Carrier
The heat generated in the semiconductor chip is transferred from the back surface of the semiconductor chip to the sealing cap through the bonding solder having excellent thermal conductivity, and the sealing having excellent thermal conductivity is also performed. The cap is designed to radiate heat to the outside.

【0010】[0010]

【発明が解決しようとする課題】前記のようなMCC構
造からなる空冷方式によるLSIでは、前記文献の説明
からも明らかなように、前記したような熱抵抗Tの条件
を満足するのは不可能であり、せいぜいT≦1〜数℃/
Wが限界である。このため、放熱効率の改善を図るのは
不可能となる。
In the air-cooling type LSI having the MCC structure as described above, it is impossible to satisfy the condition of the thermal resistance T as described above, as is apparent from the description of the above document. And at most T ≦ 1 to several degrees C. /
W is the limit. Therefore, it is impossible to improve the heat dissipation efficiency.

【0011】仮に、消費電力が50WのLSIに例をあ
げると、T=1℃/Wの場合は、パッケージの温度上昇
は50℃以上になり、封止用キャップのような放熱体か
ら外気まで含めると100℃位の温度上昇となってしま
い、空冷方式による冷却は機能しないことになる。
As an example of an LSI having a power consumption of 50 W, if T = 1 ° C./W, the temperature rise of the package becomes 50 ° C. or more, and a heat sink such as a sealing cap to outside air. If it is included, the temperature rises by about 100 ° C., and the cooling by the air cooling system will not function.

【0012】本発明の目的は、空冷方式によるLSIに
おいても熱抵抗を低減して放熱効率の改善を図ることが
可能な技術を提供することにある。
An object of the present invention is to provide a technique capable of reducing the heat resistance and improving the heat radiation efficiency even in an air cooling type LSI.

【0013】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【0014】[0014]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記の通りである。
SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.

【0015】(1)本発明の半導体集積回路装置は、半
導体チップをボール状電極を介してベース基板にフェー
スダウンボンディングするとともに、その裏面に放熱体
を取り付け、前記ベース基板の底面に前記ボール状電極
と導通する実装用電極を配置した半導体集積回路装置で
あって、前記半導体チップの裏面及び側面を覆う第1の
放熱体と、この第1の放熱体に取り付けられた第2の放
熱体とを有している。
(1) In the semiconductor integrated circuit device of the present invention, a semiconductor chip is face-down bonded to a base substrate through a ball-shaped electrode, and a heat radiator is attached to the back surface of the semiconductor chip, and the ball-shaped solder is attached to the bottom surface of the base substrate. A semiconductor integrated circuit device in which a mounting electrode that is electrically connected to an electrode is arranged, the first heat radiator covering a back surface and a side surface of the semiconductor chip, and a second heat radiator attached to the first heat radiator. have.

【0016】(2)本発明の半導体集積回路装置の製造
方法は、表面にボール状電極を設けた半導体チップを、
底面に実装用電極を配置したベース基板の表面に前記ボ
ール状電極が前記実装用電極と導通するようにフェース
ダウンボンディングする工程と、凹部が設けられた第1
の放熱体の前記凹部に半導体チップを位置決めし、熱伝
導性に優れた接着層を介して前記半導体チップの裏面及
び側面を覆うように第1の放熱体を取り付ける工程と、
前記第1の放熱体に熱伝導性に優れた接着層を介して第
2の放熱体を取り付ける工程とを含んでいる。
(2) In the method of manufacturing a semiconductor integrated circuit device of the present invention, a semiconductor chip having a ball-shaped electrode on the surface is
A step of face-down bonding so that the ball-shaped electrode is electrically connected to the mounting electrode on the surface of a base substrate having a mounting electrode arranged on the bottom surface;
Positioning the semiconductor chip in the recess of the heat radiator, and attaching the first heat radiator so as to cover the back surface and the side surface of the semiconductor chip via an adhesive layer having excellent thermal conductivity,
And a step of attaching the second heat radiator to the first heat radiator via an adhesive layer having excellent thermal conductivity.

【0017】(3)本発明の電子装置は、半導体チップ
がボール状電極を介して底面に実装用電極が配置された
ベース基板にフェースダウンボンディングされ、前記半
導体チップの裏面及び側面を覆うように第1の放熱体が
取り付けられるとともに、この第1の放熱体に第2の放
熱体が取り付けられてなる半導体集積回路装置が前記実
装用電極を介して配線基板に実装され、この配線基板が
複数組み込まれている。
(3) In the electronic device of the present invention, the semiconductor chip is face-down bonded to the base substrate having the mounting electrode on the bottom surface through the ball-shaped electrode so as to cover the back surface and the side surface of the semiconductor chip. A semiconductor integrated circuit device, in which a first radiator is attached and a second radiator is attached to the first radiator, is mounted on a wiring board via the mounting electrodes, and a plurality of wiring boards are provided. It has been incorporated.

【0018】上述した(1)の手段によれば、本発明の
半導体集積回路装置は、ボール状電極を介してベース基
板にフェースダウンボンディングされる半導体チップの
裏面及び側面を覆う第1の放熱体と、この第1の放熱体
に取り付けられた第2の放熱体とを有しているので、空
冷方式によるLSIにおいても熱抵抗を低減して放熱効
率の改善を図ることが可能となる。
According to the above-mentioned means (1), the semiconductor integrated circuit device of the present invention is the first heat radiator for covering the back surface and the side surface of the semiconductor chip face-down bonded to the base substrate via the ball-shaped electrodes. And the second heat radiator attached to the first heat radiator, the heat resistance can be reduced and the heat radiation efficiency can be improved even in the air-cooled LSI.

【0019】上述した(2)の手段によれば、本発明の
半導体集積回路装置の製造方法は、まず、表面にボール
状電極を設けた半導体チップを、底面に実装用電極を配
置したベース基板の表面に前記ボール状電極が前記実装
用電極と導通するようにフェースダウンボンディングす
る。次に、凹部が設けられた第1の放熱体の前記凹部に
半導体チップを位置決めし、熱伝導性に優れた接着層を
介して前記半導体チップの裏面及び側面を覆うように第
1の放熱体を取り付ける。続いて、前記第1の放熱体に
熱伝導性に優れた接着層を介して第2の放熱体を取り付
ける。これによって、空冷方式によるLSIにおいても
熱抵抗を低減して放熱効率の改善を図ることが可能とな
る。
According to the above-mentioned means (2), in the method for manufacturing a semiconductor integrated circuit device of the present invention, first, a semiconductor chip having a ball-shaped electrode on the surface thereof and a base substrate having a mounting electrode on the bottom surface thereof are arranged. Face down bonding is performed on the surface of the so that the ball-shaped electrode is electrically connected to the mounting electrode. Next, the semiconductor chip is positioned in the recess of the first heat radiator provided with the recess, and the first heat radiator is covered so as to cover the back surface and the side surface of the semiconductor chip via the adhesive layer having excellent thermal conductivity. Attach. Subsequently, the second heat radiator is attached to the first heat radiator via an adhesive layer having excellent thermal conductivity. As a result, it is possible to reduce the thermal resistance and improve the heat dissipation efficiency even in an LSI using the air cooling method.

【0020】上述した(3)の手段によれば、本発明の
電子装置は、半導体チップがボール状電極を介して底面
に実装用電極が配置されたベース基板にフェースダウン
ボンディングされ、前記半導体チップの裏面及び側面を
覆うように第1の放熱体が取り付けられるとともに、こ
の第1の放熱体に第2の放熱体が取り付けられてなる半
導体集積回路装置が前記実装用電極を介して配線基板に
実装され、この配線基板が複数組み込まれているので、
空冷方式によるLSIにおいても熱抵抗を低減して放熱
効率の改善を図ることが可能となる。
According to the above-mentioned means (3), in the electronic device of the present invention, the semiconductor chip is face-down bonded to the base substrate having the mounting electrode on the bottom surface through the ball electrode, and the semiconductor chip is mounted. A semiconductor integrated circuit device in which a first heat radiator is attached so as to cover the back surface and side surface of the substrate and a second heat radiator is attached to the first heat radiator is provided on a wiring board via the mounting electrodes. Since it is mounted and multiple wiring boards are incorporated,
It is possible to reduce the heat resistance and improve the heat dissipation efficiency even in the LSI using the air cooling method.

【0021】以下、本発明について、図面を参照して実
施形態とともに詳細に説明する。
Hereinafter, the present invention will be described in detail along with embodiments with reference to the drawings.

【0022】なお、実施形態を説明するための全図にお
いて、同一機能を有するものは同一符号を付け、その繰
り返しの説明は省略する。
In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

【0023】[0023]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

(実施形態1)図1は本発明の実施形態1による半導体
集積回路装置を示す平面図で、図2は図1のA−A断面
図である。本実施形態1による半導体集積回路装置10
において、例えばSi単結晶からなる半導体チップ(L
SIチップ)1の表面1Aには例えば半田バンプからな
る複数のボール状電極2が設けられていて、この半導体
チップ1は例えばBT樹脂あるいはセラミック(Al2
3などを主成分とする)などからなるベース基板3の
表面の導電層4に、ボール状電極2が半田付けにより接
続されることでフェースダウンボンディングされてい
る。
(Embodiment 1) FIG. 1 is a plan view showing a semiconductor integrated circuit device according to Embodiment 1 of the present invention, and FIG. 2 is a sectional view taken along line AA of FIG. Semiconductor integrated circuit device 10 according to the first embodiment
, A semiconductor chip (L
A plurality of ball-shaped electrodes 2 made of, for example, solder bumps are provided on the surface 1A of the SI chip 1 and the semiconductor chip 1 is made of, for example, BT resin or ceramic (Al 2
Face-down bonding is performed by connecting the ball-shaped electrode 2 to the conductive layer 4 on the surface of the base substrate 3 made of, for example, O 3 or the like) by soldering.

【0024】半導体チップ1は、例えばCMOS、ある
いはこのCMOSを主要部に用いたBiCMOSなどで
構成された、マイクロプロセッサ用のチップが用いられ
ている。
As the semiconductor chip 1, a microprocessor chip composed of, for example, CMOS or BiCMOS using this CMOS as a main part is used.

【0025】ベース基板3の底面には例えば半田バンプ
からなる複数の実装用電極5が配置されていて、各実装
用電極5はスルーホール配線を通じて対応した導電層4
を介して各ボール状電極2と導通している。これにより
BGAが構成されて、高密度実装が可能になっている。
A plurality of mounting electrodes 5 made of, for example, solder bumps are arranged on the bottom surface of the base substrate 3, and each mounting electrode 5 is provided with a corresponding conductive layer 4 through through-hole wiring.
It is electrically connected to each ball-shaped electrode 2 via. As a result, the BGA is configured and high density mounting is possible.

【0026】例えばアルミニウムナイトライド(Al
N)、銅タングステン(CuW)などからなる、Siと
熱膨張率が近似しかつ熱伝導率が近似した第1の放熱体
6が用いられ、この第1の放熱体6のほぼ中央位置には
凹部7が設けられて、半導体チップ1は凹部7に位置決
めされることにより例えばシリコーン樹脂、半田などか
らなる熱伝導性に優れた接着層8を介してその裏面1B
及び側面1Cが第1の放熱体6によって覆われている。
この第1の放熱体6は、いわゆるヒートスプレッダーと
して働くようになっており、凹部7の深さ寸法はこれに
位置決めする半導体チップ1の厚さ寸法(約0.3〜
0.5mm)よりやや小さな値に設定されている。
For example, aluminum nitride (Al
N), copper tungsten (CuW) and the like, a first heat radiator 6 having a coefficient of thermal expansion similar to that of Si and a coefficient of thermal conductivity similar to that of Si is used. When the recess 7 is provided and the semiconductor chip 1 is positioned in the recess 7, the back surface 1B of the semiconductor chip 1 is bonded to the semiconductor chip 1 via an adhesive layer 8 made of, for example, silicone resin, solder or the like and having excellent thermal conductivity.
And the side surface 1C is covered with the first radiator 6.
The first radiator 6 functions as a so-called heat spreader, and the depth dimension of the recess 7 is the thickness dimension of the semiconductor chip 1 (about 0.3 to
It is set to a value slightly smaller than 0.5 mm).

【0027】例えばCu系あるいはAl系金属などから
なる熱伝導率の高い第2の放熱体9が用いられて、この
第2の放熱体9は例えばシリコーン樹脂、半田などから
なる熱伝導性に優れた接着層8を介して、第1の放熱体
6に取り付けられている。第2の放熱体9は効率的な放
熱が可能となるように、表面積の大きいフィン状になっ
ていることが望ましい。
A second radiator 9 having a high thermal conductivity made of, for example, a Cu-based or Al-based metal is used, and the second radiator 9 is made of, for example, a silicone resin or solder and has excellent thermal conductivity. It is attached to the first radiator 6 via the adhesive layer 8. It is desirable that the second radiator 9 has a fin shape with a large surface area so that heat can be efficiently dissipated.

【0028】なお、各ボール状電極2及び実装用電極5
の数は、説明を理解し易くするため限られた数で示して
いる。また、同様な趣旨で、半導体チップ1、ベース基
板3、第1の放熱体6及び第2の放熱体9などの相互間
における寸法の大小関係は、実情を反映していない。
In addition, each ball-shaped electrode 2 and mounting electrode 5
The number of is shown as a limited number to facilitate understanding of the description. For the same reason, the size relationship between the semiconductor chip 1, the base substrate 3, the first radiator 6, the second radiator 9, and the like does not reflect the actual situation.

【0029】このような構造のLSIによれば、半導体
チップ1の裏面1B及び側面1Cはともに、例えばシリ
コーン樹脂、半田などからなる熱伝導性に優れた接着層
8を介して第1の放熱体6によって覆われ、さらにこの
第1の放熱体6には例えばシリコーン樹脂、半田などか
らなる熱伝導性に優れた接着層8を介して第2の放熱体
9が取り付けられているので、半導体チップ1で発生し
た熱はこの裏面1Aだけでなくその側面1Cからも第1
の放熱体6に伝達されて周囲に広がり、さらにこの熱は
第2の放熱体9から外気に放熱されるので、効率的な放
熱が可能となる。
According to the LSI having such a structure, both the back surface 1B and the side surface 1C of the semiconductor chip 1 are provided with the first heat radiating body via the adhesive layer 8 made of, for example, silicone resin, solder or the like and having excellent thermal conductivity. The second heat radiator 9 is covered with the second heat radiator 6, and the second heat radiator 9 is attached to the first heat radiator 6 via the adhesive layer 8 made of, for example, silicone resin, solder or the like and having excellent thermal conductivity. The heat generated at 1 is generated not only from the back surface 1A but also from the side surface 1C thereof.
The heat is transmitted to the heat radiating body 6 and spread to the surroundings, and this heat is further radiated to the outside air from the second heat radiating body 9, so that efficient heat radiating is possible.

【0030】よって、熱抵抗Tを著しく低減することが
可能となり、約0.2〜0.7℃/Wの熱抵抗が実現可
能となる。これにより、放熱効率の改善を図ることが可
能となり、高性能のマイクロプロセッサを実現できるの
で、マイクロプロセッサを各種コンピュータシステムを
含む電子装置に組み込んだ場合でも、十分な放熱対策を
講じることができるようになる。
Therefore, the thermal resistance T can be remarkably reduced, and the thermal resistance of about 0.2 to 0.7 ° C./W can be realized. This makes it possible to improve heat dissipation efficiency and realize a high-performance microprocessor, so that even when the microprocessor is incorporated in an electronic device including various computer systems, sufficient heat dissipation measures can be taken. become.

【0031】次に、本実施形態1による半導体集積回路
装置10の製造方法を、図3乃至図6を参照して工程順
に説明する。
Next, the method of manufacturing the semiconductor integrated circuit device 10 according to the first embodiment will be described in the order of steps with reference to FIGS.

【0032】まず、図3に示すように、表面1Aに例え
ば半田バンプからなる複数のボール状電極2が設けられ
た例えばSi単結晶からなる半導体チップ(LSIチッ
プ)1を用意する。
First, as shown in FIG. 3, a semiconductor chip (LSI chip) 1 made of, for example, a Si single crystal having a plurality of ball-shaped electrodes 2 made of, for example, solder bumps provided on the surface 1A is prepared.

【0033】次に、図4に示すように、表面に導電層4
が設けられるとともに、底面に例えば半田バンプからな
る複数の実装用電極5が配置された例えば樹脂あるいは
セラミックなどからなるベース基板3を用意し、半導体
チップ1をその導電層4にボール状電極2を半田付けに
より接続して、フェースダウンボンディングする。この
ボンディング工程は、ベース基板3上に半導体チップ1
を位置決めした状態で、リフロー炉を通過させることに
より容易に行うことができる。
Next, as shown in FIG. 4, a conductive layer 4 is formed on the surface.
Is provided, and a base substrate 3 made of, for example, resin or ceramic, having a plurality of mounting electrodes 5 made of, for example, solder bumps arranged on the bottom surface is prepared, and the semiconductor chip 1 is provided with the ball-shaped electrodes 2 on its conductive layer 4. Connect by soldering and face down bonding. In this bonding process, the semiconductor chip 1 is mounted on the base substrate 3.
It can be easily carried out by passing the reflow furnace in the state of being positioned.

【0034】続いて、図5に示すように、例えばアルミ
ニウムナイトライド(AlN)、銅タングステン(Cu
W)などからなる、Siと熱膨張率が近似しかつ熱伝導
率が近似した中央位置に凹部7が設けられた第1の放熱
体6を用意して、半導体チップ1を凹部7に位置決めす
ることにより例えばシリコーン樹脂、半田などからなる
熱伝導性に優れた接着層8を介して、その裏面1B及び
側面1Cを第1の放熱体6によって覆う。
Then, as shown in FIG. 5, for example, aluminum nitride (AlN) and copper tungsten (Cu) are used.
A semiconductor chip 1 is positioned in the recess 7 by preparing a first heat radiator 6 made of W) or the like having a coefficient of thermal expansion similar to that of Si and having a coefficient of thermal conductivity similar to that of the first embodiment. As a result, the back surface 1B and the side surface 1C thereof are covered with the first heat radiator 6 via the adhesive layer 8 made of, for example, silicone resin, solder or the like and having excellent thermal conductivity.

【0035】次に、図6に示すように、例えばCu系あ
るいはAl系金属などからなる熱伝導率の高い第2の放
熱体9を用意して、この第2の放熱体9を例えばシリコ
ーン樹脂、半田などからなる熱伝導性に優れた接着層8
を介して、第1の放熱体6に取り付ける。
Next, as shown in FIG. 6, a second heat radiating body 9 made of, for example, a Cu-based or Al-based metal and having a high thermal conductivity is prepared, and the second heat radiating body 9 is made of, for example, a silicone resin. Adhesive layer 8 made of solder, solder, etc. with excellent thermal conductivity
It is attached to the first radiator 6 via.

【0036】以上によって、図1に示したような半導体
集積回路装置10が得られる。
As described above, the semiconductor integrated circuit device 10 as shown in FIG. 1 is obtained.

【0037】以上のような実施形態1によれば次のよう
な効果が得られる。
According to the first embodiment described above, the following effects can be obtained.

【0038】例えば半田バンプからなる複数のボール状
電極2を介してベース基板3にフェースダウンボンディ
ングされる半導体チップ1の裏面1B及び側面1Cを覆
う第1の放熱体6と、この第1の放熱体6に取り付けら
れた第2の放熱体9とを有しているので、空冷方式によ
るLSIにおいても熱抵抗を低減して放熱効率の改善を
図ることが可能となる。
A first radiator 6 for covering the back surface 1B and the side surface 1C of the semiconductor chip 1 which is face-down bonded to the base substrate 3 via a plurality of ball-shaped electrodes 2 formed of, for example, solder bumps, and this first heat radiation. Since the second heat radiator 9 attached to the body 6 is provided, the heat resistance can be reduced and the heat radiation efficiency can be improved even in the LSI by the air cooling method.

【0039】(実施形態2)図7は本発明の実施形態2
による半導体集積回路装置を示す断面図である。本実施
形態2による半導体集積回路装置10は、ベース基板3
の底面に設けた実装用電極5として短いピンを用いるよ
うにした、いわゆるButt−PGAに適用した例を示
すものである。このようなButt−PGA構造におい
ても、BGAと同様に高密度実装が可能になっている。
(Second Embodiment) FIG. 7 shows a second embodiment of the present invention.
3 is a cross-sectional view showing the semiconductor integrated circuit device according to FIG. The semiconductor integrated circuit device 10 according to the second embodiment includes the base substrate 3
This is an example applied to a so-called Butt-PGA in which a short pin is used as the mounting electrode 5 provided on the bottom surface of the. Even in such a Butt-PGA structure, high-density mounting is possible like BGA.

【0040】以上のような実施形態2によれば、実施形
態1に比較してパッケージ構造が異なるだけなので、実
施形態1と同様な効果を得ることができる。
According to the second embodiment described above, only the package structure is different from that of the first embodiment, and therefore the same effect as that of the first embodiment can be obtained.

【0041】(実施形態3)図8は本発明の実施形態2
による半導体集積回路装置を示す断面図である。本実施
形態3による半導体集積回路装置10は、実施形態1に
比較して、第1の放熱体6には凹部7を囲むように凸部
11が設けられていて、この凸部11は図9に示すよう
に全周囲にわたって設けられている。この凸部11の高
さ寸法は、ボール状電極2を含めた半導体チップ1の厚
さ寸法よりやや大きな値に設定される。
(Embodiment 3) FIG. 8 shows Embodiment 2 of the present invention.
3 is a cross-sectional view showing the semiconductor integrated circuit device according to FIG. In the semiconductor integrated circuit device 10 according to the third embodiment, as compared with the first embodiment, the first radiator 6 is provided with the convex portion 11 so as to surround the concave portion 7. As shown in FIG. The height dimension of the convex portion 11 is set to a value slightly larger than the thickness dimension of the semiconductor chip 1 including the ball-shaped electrode 2.

【0042】第1の放熱体6は、凸部11がベース基板
3の表面に樹脂などの絶縁性接着層12を介して支持さ
れるようにして、半導体チップ1の裏面1B及び側面1
Cを覆っている。
The first radiator 6 has a convex portion 11 supported on the surface of the base substrate 3 via an insulating adhesive layer 12 such as a resin so that the back surface 1B and the side surface 1 of the semiconductor chip 1 are covered.
It covers C.

【0043】以上のような実施形態3によれば、実施形
態1と同様な効果が得られる他に、半導体チップ1は第
1の放熱体6の凸部11によってベース基板3に外気か
ら密封された構造で取り付けられているので、外気から
の不純物、汚染物などの有害な物質の侵入を阻止するこ
とができるようになり、高信頼性のLSIを実現できる
という効果が得られる。また、第1の放熱体6は凸部1
1によって半導体チップ1に対して第1及び第2の放熱
体6、9の重みがかかるのを阻止しているので、半導体
チップ1の破損が防止されるという効果が得られる。
According to the third embodiment as described above, in addition to the same effect as that of the first embodiment, the semiconductor chip 1 is sealed from the outside air in the base substrate 3 by the convex portion 11 of the first heat radiator 6. Since it is mounted in such a structure, it is possible to prevent invasion of harmful substances such as impurities and contaminants from the outside air, and it is possible to obtain a highly reliable LSI. In addition, the first radiator 6 is the convex portion 1
Since 1 prevents the weight of the first and second heat radiators 6 and 9 from being applied to the semiconductor chip 1, the effect of preventing damage to the semiconductor chip 1 can be obtained.

【0044】(実施形態4)図10は本発明の実施形態
4による電子装置を示す断面図で、実施形態1により得
られた半導体集積回路装置10を複数用いて、共通の配
線基板13に実装してモジュール基板17を組み立てた
例を示すものである。
(Embodiment 4) FIG. 10 is a sectional view showing an electronic device according to Embodiment 4 of the present invention. A plurality of semiconductor integrated circuit devices 10 obtained in Embodiment 1 are used and mounted on a common wiring board 13. This shows an example in which the module board 17 is assembled.

【0045】各半導体集積回路装置10は予め表面に導
電層14が設けられた配線基板13上に位置決めされ
て、リフロー炉を通過させることにより、実装用電極5
が導電層14に半田付けされて実装される。
Each of the semiconductor integrated circuit devices 10 is positioned on the wiring substrate 13 having the conductive layer 14 provided on the surface thereof in advance, and is passed through the reflow furnace, whereby the mounting electrodes 5 are formed.
Are soldered and mounted on the conductive layer 14.

【0046】このように各半導体集積回路装置10を配
線基板13に実装する場合、ボール状電極2の半田バン
プの成分と実装用電極5の半田バンプの成分とを変えて
おくことにより、各々の融点が相違するので、後工程で
実装用電極5の半田付け処理時に前工程で半田付けした
ボール状電極2の溶融を避けることができる。なお、本
実施形態の構造の場合、第1及び第2の放熱体6、9の
重みによって半導体チップ1に加重がかかるのを防止す
るために、第1の放熱体6と配線基板13との間にスペ
ーサ16を介在させることが望ましい。
When each semiconductor integrated circuit device 10 is mounted on the wiring board 13 in this manner, the components of the solder bumps of the ball-shaped electrodes 2 and the components of the solder bumps of the mounting electrodes 5 are changed so as to be different from each other. Since the melting points are different, it is possible to avoid melting of the ball-shaped electrode 2 soldered in the previous step when the mounting electrode 5 is soldered in the subsequent step. In the case of the structure of the present embodiment, in order to prevent the weight of the first and second radiators 6 and 9 from being applied to the semiconductor chip 1, the first radiator 6 and the wiring board 13 are separated from each other. It is desirable to interpose the spacer 16 therebetween.

【0047】以上のような実施形態4によれば、実施形
態1で得られた半導体集積回路装置10を用いてモジュ
ール基板17を組み立てているので、実施形態1と同様
に、空冷方式によるLSIにおいても熱抵抗を低減して
放熱効率の改善を図ることが可能となる。
According to the fourth embodiment as described above, the module substrate 17 is assembled using the semiconductor integrated circuit device 10 obtained in the first embodiment. Therefore, in the same manner as in the first embodiment, in the LSI by the air cooling method. It is also possible to reduce the thermal resistance and improve the heat dissipation efficiency.

【0048】(実施形態5)図11は本発明の実施形態
5による電子装置を示す断面図で、実施形態3により得
られた半導体集積回路装置10を複数用いて、共通の配
線基板13に実装してモジュール基板17を組み立てた
例を示すものである。
(Fifth Embodiment) FIG. 11 is a sectional view showing an electronic device according to a fifth embodiment of the present invention. A plurality of semiconductor integrated circuit devices 10 obtained according to the third embodiment are mounted on a common wiring board 13. This shows an example in which the module board 17 is assembled.

【0049】本実施形態の構造によれば、第1の放熱体
6の凸部11によって半導体チップ1には加重がかから
ないので、スペーサは不要になる。
According to the structure of this embodiment, since the semiconductor chip 1 is not weighted by the convex portion 11 of the first heat radiator 6, the spacer is not necessary.

【0050】以上のような実施形態5によれば、実施形
態3で得られた半導体集積回路装置10を用いてモジュ
ール基板17を組み立てているので、実施形態3と同様
に、空冷方式によるLSIにおいても熱抵抗を低減して
放熱効率の改善を図ることが可能となる。
According to the fifth embodiment as described above, since the module substrate 17 is assembled using the semiconductor integrated circuit device 10 obtained in the third embodiment, as in the third embodiment, in the air-cooled LSI. It is also possible to reduce the thermal resistance and improve the heat dissipation efficiency.

【0051】(実施形態6)図12は本発明の実施形態
6による電子装置を示す断面図で、実施形態4により得
られたモジュール基板17を複数用いて、コネクタ19
を介してメイン基板18に実装して各種コンピュータな
どの電子装置20を組み立てた例を示すものである。
(Embodiment 6) FIG. 12 is a sectional view showing an electronic device according to Embodiment 6 of the present invention, in which a plurality of module boards 17 obtained in Embodiment 4 are used and a connector 19 is provided.
1 shows an example in which an electronic device 20 such as various computers is assembled by being mounted on the main board 18 via.

【0052】以上のような実施形態6によれば、実施形
態4で得られたモジュール基板17を用いて電子装置2
0を組み立てているので、実施形態4と同様に、空冷方
式によるLSIにおいても熱抵抗を低減して放熱効率の
改善を図ることが可能となる。
According to the sixth embodiment as described above, the electronic device 2 using the module substrate 17 obtained in the fourth embodiment.
Since 0 is assembled, it is possible to reduce heat resistance and improve heat dissipation efficiency in an air-cooled LSI as in the fourth embodiment.

【0053】(実施形態7)図13は本発明の実施形態
7による電子装置を示す断面図で、実施形態5により得
られたモジュール基板17を複数用いて、コネクタ19
を介してメイン基板18に実装して各種コンピュータな
どの電子装置20を組み立てた例を示すものである。
(Embodiment 7) FIG. 13 is a sectional view showing an electronic device according to Embodiment 7 of the present invention, in which a plurality of module boards 17 obtained according to Embodiment 5 are used and a connector 19 is used.
1 shows an example in which an electronic device 20 such as various computers is assembled by being mounted on the main board 18 via.

【0054】以上のような実施形態7によれば、実施形
態5で得られたモジュール基板17を用いて電子装置2
0を組み立てているので、実施形態5と同様に、空冷方
式によるLSIにおいても熱抵抗を低減して放熱効率の
改善を図ることが可能となる。
According to the seventh embodiment as described above, the electronic device 2 using the module substrate 17 obtained in the fifth embodiment is used.
Since 0 is assembled, it is possible to reduce heat resistance and improve heat dissipation efficiency in an air-cooled LSI as in the fifth embodiment.

【0055】以上、本発明者によってなされた発明を、
前記実施形態に基づき具体的に説明したが、本発明は、
前記実施形態に限定されるものではなく、その要旨を逸
脱しない範囲において種々変更可能であることは勿論で
ある。
As described above, the invention made by the present inventor is
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above embodiment, and various changes can be made without departing from the scope of the invention.

【0056】例えば、前記実施形態では、BGAあるい
はButt−PGA構造のパッケージを有するLSIに
適用した例で説明したが、これらに限らず、例えばTA
B(Tape Automated Bonding)
構造のパッケージに適用することも可能である。
For example, in the above-described embodiment, an example in which it is applied to an LSI having a package of BGA or Butt-PGA structure has been described, but the present invention is not limited to this and, for example, TA
B (Tape Automated Bonding)
It is also possible to apply the structure package.

【0057】また、前記実施形態では、半導体チップは
例えばCMOS、あるいはこのCMOSを主要部に用い
たBiCMOSなどで構成されたマイクロプロセッサ用
のチップに例をあげて説明したが、これに限らず、EC
L−CMOS、ECLタイプのマイクロプロセッサ、あ
るいはMPU、MCUさらには周辺ASIC−LSIな
どにも適用可能である。
Further, in the above-described embodiment, the semiconductor chip has been described by way of example as a chip for a microprocessor constituted by, for example, CMOS or BiCMOS using this CMOS as a main part, but the present invention is not limited to this. EC
The present invention is also applicable to L-CMOS, ECL type microprocessors, MPUs, MCUs and peripheral ASIC-LSIs.

【0058】さらに、前記実施形態では、BGAあるい
はButt−PGA構造のパッケージを有するLSIに
適用した例で説明したが、このように実装用電極がボー
ル状あるいは短ピン状になっている構造では、特に高周
波信号を扱う場合にインダクタンス成分を低減すること
ができるので、高速化を図る上で効果的となる。
Further, in the above-described embodiment, an example in which the packaging electrode is applied to an LSI having a package of BGA or Butt-PGA structure has been described. However, in such a structure in which the mounting electrodes have a ball shape or a short pin shape, In particular, when handling a high frequency signal, the inductance component can be reduced, which is effective in increasing the speed.

【0059】なお、前記実施形態で示した、ボール状電
極、第1及び第2の放熱体、熱伝導性に優れた接着層な
どの具体的材料は一例を示したものであり、同じような
機能を有するものであれば、同様に用いることができ
る。
It should be noted that the specific materials such as the ball-shaped electrodes, the first and second heat radiators, and the adhesive layer having excellent thermal conductivity shown in the above embodiment are merely examples, and similar materials are used. If it has a function, it can be used similarly.

【0060】以上の説明では主として本発明者によって
なされた発明をその背景となった利用分野である半導体
集積回路装置に適用した場合について説明したが、それ
に限定されるものではない。本発明は、少なくとも大電
力用に使用する場合に放熱効率の改善を図ることを条件
とするものには適用できる。
In the above description, the case where the invention made by the present inventor is mainly applied to the semiconductor integrated circuit device which is the background field of application has been described, but the invention is not limited thereto. INDUSTRIAL APPLICABILITY The present invention can be applied to at least the condition that heat dissipation efficiency is improved when used for high power.

【0061】[0061]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記の通りである。
The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

【0062】ボール状電極を介してベース基板にフェー
スダウンボンディングされる半導体チップの裏面及び側
面を覆う第1の放熱体と、この第1の放熱体に取り付け
られた第2の放熱体とを有しているので、空冷方式によ
るLSIにおいても熱抵抗を低減して放熱効率の改善を
図ることが可能となる。
There is provided a first heat radiator that covers the back and side surfaces of the semiconductor chip that is face-down bonded to the base substrate through the ball-shaped electrodes, and a second heat radiator that is attached to the first heat radiator. Therefore, it is possible to reduce the heat resistance and improve the heat radiation efficiency even in the LSI using the air cooling method.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施形態1による半導体集積回路装置
を示す平面図である。
FIG. 1 is a plan view showing a semiconductor integrated circuit device according to a first embodiment of the present invention.

【図2】図1のA−A断面図である。FIG. 2 is a sectional view taken along line AA of FIG.

【図3】本発明の実施形態1による半導体集積回路装置
の製造方法の一工程を示す断面図である。
FIG. 3 is a cross-sectional view showing a step of the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

【図4】本発明の実施形態1による半導体集積回路装置
の製造方法の他の工程を示す断面図である。
FIG. 4 is a sectional view showing another step of the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

【図5】本発明の実施形態1による半導体集積回路装置
の製造方法のその他の工程を示す断面図である。
FIG. 5 is a sectional view showing another step of the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

【図6】本発明の実施形態1による半導体集積回路装置
の製造方法のその他の工程を示す断面図である。
FIG. 6 is a sectional view showing another step of the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

【図7】本発明の実施形態2による半導体集積回路装置
を示す断面図である。
FIG. 7 is a sectional view showing a semiconductor integrated circuit device according to Embodiment 2 of the present invention.

【図8】本発明の実施形態3による半導体集積回路装置
を示す断面図である。
FIG. 8 is a sectional view showing a semiconductor integrated circuit device according to a third embodiment of the present invention.

【図9】本発明の実施形態3による半導体集積回路装置
の主要部を示す底面図である。
FIG. 9 is a bottom view showing a main part of a semiconductor integrated circuit device according to a third embodiment of the present invention.

【図10】本発明の実施形態4による電子装置を示す断
面図である。
FIG. 10 is a sectional view showing an electronic device according to Embodiment 4 of the present invention.

【図11】本発明の実施形態5による電子装置を示す断
面図である。
FIG. 11 is a sectional view showing an electronic device according to a fifth embodiment of the present invention.

【図12】本発明の実施形態6による電子装置を示す断
面図である。
FIG. 12 is a sectional view showing an electronic device according to Embodiment 6 of the present invention.

【図13】本発明の実施形態7による電子装置を示す断
面図である。
FIG. 13 is a sectional view showing an electronic device according to Embodiment 7 of the present invention.

【符号の説明】[Explanation of symbols]

1…半導体チップ、1A…半導体チップの表面、1B半
導体チップの裏面、1C…半導体チップの側面、2…ボ
ール状電極、3…ベース基板、4…導電層、5…実装用
電極、6…第1の放熱体(ヒートスプレッダー)、7…
凹部、8…熱伝導性に優れた接着層、9…第2の放熱
体、10…半導体集積回路装置、11…凸部、12…絶
縁性接着層、13…配線基板、14…導電層、15…配
線基板、16…スペーサ、17…モジュール基板、18
…メイン基板、19…コネクタ、20…電子装置。
DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 1A ... Front surface of semiconductor chip, 1B Back surface of semiconductor chip, 1C ... Side surface of semiconductor chip, 2 ... Ball-shaped electrode, 3 ... Base substrate, 4 ... Conductive layer, 5 ... Mounting electrode, 6 ... 1 heat radiator (heat spreader), 7 ...
Recessed portion, 8 ... Adhesive layer having excellent thermal conductivity, 9 ... Second heat radiator, 10 ... Semiconductor integrated circuit device, 11 ... Convex portion, 12 ... Insulating adhesive layer, 13 ... Wiring board, 14 ... Conductive layer, 15 ... Wiring board, 16 ... Spacer, 17 ... Module board, 18
... main board, 19 ... connector, 20 ... electronic device.

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップをボール状電極を介してベ
ース基板にフェースダウンボンディングするとともに、
その裏面に放熱体を取り付け、前記ベース基板の底面に
前記ボール状電極と導通する実装用電極を配置した半導
体集積回路装置であって、前記半導体チップの裏面及び
側面を覆う第1の放熱体と、この第1の放熱体に取り付
けられた第2の放熱体とを有することを特徴とする半導
体集積回路装置。
1. A semiconductor chip is face-down bonded to a base substrate via a ball-shaped electrode, and
A semiconductor integrated circuit device in which a heat radiator is attached to a back surface of the base substrate, and mounting electrodes electrically connected to the ball-shaped electrodes are arranged on a bottom surface of the base substrate, the first heat radiator covering a back surface and a side surface of the semiconductor chip. And a second heat radiator attached to the first heat radiator.
【請求項2】 前記第1の放熱体は、熱伝導性に優れた
接着層を介して前記半導体チップの裏面及び側面を覆っ
ていることを特徴とする請求項1に記載の半導体集積回
路装置。
2. The semiconductor integrated circuit device according to claim 1, wherein the first heat radiator covers the back surface and the side surface of the semiconductor chip via an adhesive layer having excellent thermal conductivity. .
【請求項3】 前記ボール状電極は、半田バンプからな
ることを特徴とする請求項1または2に記載の半導体集
積回路装置。
3. The semiconductor integrated circuit device according to claim 1, wherein the ball-shaped electrodes are solder bumps.
【請求項4】 前記実装用電極は、半田バンプからなる
ことを特徴とする請求項1乃至3のいずれか1項に記載
の半導体集積回路装置。
4. The semiconductor integrated circuit device according to claim 1, wherein the mounting electrodes are solder bumps.
【請求項5】 前記第1の放熱体は、半導体チップの裏
面及び側面を覆う凹部が設けられていることを特徴とす
る請求項1乃至4のいずれか1項に記載の半導体集積回
路装置。
5. The semiconductor integrated circuit device according to claim 1, wherein the first heat radiator is provided with a concave portion that covers a back surface and a side surface of the semiconductor chip.
【請求項6】 前記第1の放熱体は、前記凹部を囲むよ
うに凸部が設けられて、この凸部が前記ベース基板の表
面に支持されるようにして前記半導体チップの裏面及び
側面を覆っていることを特徴とする請求項5に記載の半
導体集積回路装置。
6. The first heat radiator is provided with a convex portion surrounding the concave portion, and the convex portion is supported on the front surface of the base substrate so that the rear surface and the side surface of the semiconductor chip are covered. The semiconductor integrated circuit device according to claim 5, which is covered.
【請求項7】 表面にボール状電極を設けた半導体チッ
プを、底面に実装用電極を配置したベース基板の表面に
前記ボール状電極が前記実装用電極と導通するようにフ
ェースダウンボンディングする工程と、凹部が設けられ
た第1の放熱体の前記凹部に半導体チップを位置決め
し、熱伝導性に優れた接着層を介して前記半導体チップ
の裏面及び側面を覆うように第1の放熱体を取り付ける
工程と、前記第1の放熱体に熱伝導性に優れた接着層を
介して第2の放熱体を取り付ける工程とを含むことを特
徴とする半導体集積回路装置の製造方法。
7. A step of face-down bonding a semiconductor chip having a ball-shaped electrode on a surface thereof to a surface of a base substrate having a mounting electrode on a bottom surface thereof so that the ball-shaped electrode is electrically connected to the mounting electrode. , Positioning the semiconductor chip in the recess of the first heat radiator provided with the recess, and attaching the first heat radiator so as to cover the back surface and the side surface of the semiconductor chip via an adhesive layer having excellent thermal conductivity. A method of manufacturing a semiconductor integrated circuit device, comprising: a step of attaching a second heat radiator to the first heat radiator via an adhesive layer having excellent thermal conductivity.
【請求項8】 半導体チップがボール状電極を介して底
面に実装用電極が配置されたベース基板にフェースダウ
ンボンディングされ、前記半導体チップの裏面及び側面
を覆うように第1の放熱体が取り付けられるとともに、
この第1の放熱体に第2の放熱体が取り付けられてなる
半導体集積回路装置が前記実装用電極を介して配線基板
に実装され、この配線基板が複数組み込まれてなること
を特徴とする電子装置。
8. A semiconductor chip is face-down bonded to a base substrate having a mounting electrode on the bottom surface via a ball-shaped electrode, and a first heat radiator is attached so as to cover the back surface and the side surface of the semiconductor chip. With
An electronic device characterized in that a semiconductor integrated circuit device in which a second heat radiator is attached to the first heat radiator is mounted on a wiring board via the mounting electrodes, and a plurality of wiring boards are incorporated. apparatus.
【請求項9】 前記半導体集積回路装置は、前記半導体
チップの裏面及び側面を覆う凹部が設けられているとと
もに、この凹部を囲むように凸部が設けられた第1の放
熱体を有し、前記凸部が前記ベース基板の表面に支持さ
れるようにして前記半導体チップの裏面及び側面を覆っ
ていることを特徴とする請求項8に記載の電子装置。
9. The semiconductor integrated circuit device includes a first heat radiator provided with a concave portion covering a back surface and a side surface of the semiconductor chip, and a convex portion surrounding the concave portion, 9. The electronic device according to claim 8, wherein the convex portion covers the back surface and the side surface of the semiconductor chip so as to be supported by the front surface of the base substrate.
JP1630296A 1996-02-01 1996-02-01 Semiconductor integrated circuit device, manufacture thereof, and electronic device equipped therewith Pending JPH09213847A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1630296A JPH09213847A (en) 1996-02-01 1996-02-01 Semiconductor integrated circuit device, manufacture thereof, and electronic device equipped therewith

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1630296A JPH09213847A (en) 1996-02-01 1996-02-01 Semiconductor integrated circuit device, manufacture thereof, and electronic device equipped therewith

Publications (1)

Publication Number Publication Date
JPH09213847A true JPH09213847A (en) 1997-08-15

Family

ID=11912755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1630296A Pending JPH09213847A (en) 1996-02-01 1996-02-01 Semiconductor integrated circuit device, manufacture thereof, and electronic device equipped therewith

Country Status (1)

Country Link
JP (1) JPH09213847A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100320983B1 (en) * 1997-08-22 2002-06-20 포만 제프리 엘 How to Provide Chip Assemblies and Direct Open Thermally Conductive Paths
JP2002325468A (en) * 2001-04-27 2002-11-08 Matsushita Electric Ind Co Ltd Power converter
US6781832B2 (en) 2001-02-28 2004-08-24 Kabushiki Kaisha Toshiba Cooling unit for cooling heat generating component and electronic apparatus containing cooling unit
JP2009059760A (en) * 2007-08-30 2009-03-19 Toshiba Corp Heat dissipation structure of electronic circuit board
WO2012038121A1 (en) * 2010-09-23 2012-03-29 Robert Bosch Gmbh Flip-chip assembly having a cooling element and method for producing a flip-chip assembly
JP2017191904A (en) * 2016-04-15 2017-10-19 オムロン株式会社 Heat radiation structure of semiconductor device
CN111302807A (en) * 2020-04-02 2020-06-19 上海闻泰信息技术有限公司 Preparation method of heat dissipation material for chip, heat dissipation chip and application

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100320983B1 (en) * 1997-08-22 2002-06-20 포만 제프리 엘 How to Provide Chip Assemblies and Direct Open Thermally Conductive Paths
US6781832B2 (en) 2001-02-28 2004-08-24 Kabushiki Kaisha Toshiba Cooling unit for cooling heat generating component and electronic apparatus containing cooling unit
JP2002325468A (en) * 2001-04-27 2002-11-08 Matsushita Electric Ind Co Ltd Power converter
JP2009059760A (en) * 2007-08-30 2009-03-19 Toshiba Corp Heat dissipation structure of electronic circuit board
WO2012038121A1 (en) * 2010-09-23 2012-03-29 Robert Bosch Gmbh Flip-chip assembly having a cooling element and method for producing a flip-chip assembly
JP2017191904A (en) * 2016-04-15 2017-10-19 オムロン株式会社 Heat radiation structure of semiconductor device
CN111302807A (en) * 2020-04-02 2020-06-19 上海闻泰信息技术有限公司 Preparation method of heat dissipation material for chip, heat dissipation chip and application

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