JPH0878616A - Multi-chip module - Google Patents

Multi-chip module

Info

Publication number
JPH0878616A
JPH0878616A JP20979094A JP20979094A JPH0878616A JP H0878616 A JPH0878616 A JP H0878616A JP 20979094 A JP20979094 A JP 20979094A JP 20979094 A JP20979094 A JP 20979094A JP H0878616 A JPH0878616 A JP H0878616A
Authority
JP
Japan
Prior art keywords
substrate
chip module
ceramic package
metal plate
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP20979094A
Other languages
Japanese (ja)
Inventor
Masato Tsuchiya
正人 土屋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20979094A priority Critical patent/JPH0878616A/en
Publication of JPH0878616A publication Critical patent/JPH0878616A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE: To obtain a substrate for a multi-chip module capable of increasing a mounting density by mounting semiconductor elements on both the surfaces of the substrate thereby effectively utilizing the surfaces of the substrate and also capable of providing good heat radiation. CONSTITUTION: A metal plate 23 for heat radiation is sandwiched between at least two alumina laminated substrates 21 and 22 and simultaneously baked as one united body, which contains substrates mounting semiconductors on both the surfaces, a ceramics package 29 having a thermal via 32 inside which is connected to at least part of the metal plate 23 of the substrate when the substrate has been mounted, and a heat radiating member 36 attached to the ceramic package 29 in such a manner that it can be connected to the thermal via 32.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に関し、特
に複数の半導体素子を1つの基板上に高密度に実装する
ことにより、素子間の配線遅延を軽減し、高速の動作を
可能にするマルチチップ・モジュールに関する。マルチ
チップ・モジュールは、高速の半導体素子を実装する上
で優れた方式であるが、複数の半導体素子より生ずる熱
を効率良く発散させる必要がある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, by mounting a plurality of semiconductor elements on a single substrate at high density, wiring delay between the elements can be reduced and high speed operation can be realized. Regarding multi-chip modules. The multi-chip module is an excellent method for mounting high-speed semiconductor devices, but it is necessary to efficiently dissipate heat generated by a plurality of semiconductor devices.

【0002】[0002]

【従来の技術】図4に、基板の表裏両面に複数の半導体
素子が搭載された従来のマルチチップ・モジュールの一
例(従来構造1)を示す。基板1の表裏両面には複数の
半導体素子2が搭載されており、これらの半導体素子2
はボンディングワイヤ3により基板1上の導体パターン
(図示せず)に接続されている。基板1と外部リード4
との間もボンディングワイヤ5により接続され、複数の
半導体素子2を含む基板1はトランスファモールドによ
って、例えばエポキシ等の樹脂6により気密封止されて
プラスチックパッケージ7を構成する。樹脂6の外面に
は放熱フィン8が取付けられ、このパッケージの熱、特
に複数の半導体素子2の熱を放散している。なお、9は
基板1の表裏面のパターン(図示せず)間の導通を図る
ためのスルーホールである。
2. Description of the Related Art FIG. 4 shows an example of a conventional multichip module (conventional structure 1) in which a plurality of semiconductor elements are mounted on both front and back surfaces of a substrate. A plurality of semiconductor elements 2 are mounted on both front and back surfaces of the substrate 1.
Are connected to a conductor pattern (not shown) on the substrate 1 by bonding wires 3. Board 1 and external leads 4
Is also connected by a bonding wire 5, and the substrate 1 including the plurality of semiconductor elements 2 is hermetically sealed with a resin 6 such as epoxy by transfer molding to form a plastic package 7. Radiating fins 8 are attached to the outer surface of the resin 6 to dissipate the heat of this package, especially the heat of the plurality of semiconductor elements 2. Reference numeral 9 is a through hole for establishing conduction between patterns (not shown) on the front and back surfaces of the substrate 1.

【0003】図5に、プラスチックパッケージに比較し
て熱抵抗の低いセラミックパッケージを使用した従来例
(従来構造2)を示す。図5において、セラミックパッ
ケージ(セラミック基板)11の片面(図5の下面)に
複数の半導体素子12が搭載されており、これらの半導
体素子12はボンディングワイヤ13によりセラミック
パッケージ11上の導体パターン(図示せず)に接続さ
れる。セラミックパッケージ11の周囲立ち上がり部に
はキャップ15が被せられ、内部の半導体素子12を保
護する。セラミックパッケージ11の半導体素子12と
は反対側の面には、放熱フィン18が取付けられ、また
外部リード14がセラミックパッケージ11に接続され
ている。半導体素子12と外部リード14との間の接続
はセラミックパッケージ11内部の配線パターン(図示
せず)にて行われる。
FIG. 5 shows a conventional example (conventional structure 2) using a ceramic package having a lower thermal resistance than a plastic package. In FIG. 5, a plurality of semiconductor elements 12 are mounted on one surface (lower surface in FIG. 5) of a ceramic package (ceramic substrate) 11, and these semiconductor elements 12 are bonded by a bonding wire 13 to a conductor pattern (see FIG. Connected (not shown). A cap 15 covers the rising portion of the periphery of the ceramic package 11 to protect the semiconductor element 12 inside. Radiating fins 18 are attached to the surface of the ceramic package 11 opposite to the semiconductor element 12, and external leads 14 are connected to the ceramic package 11. The connection between the semiconductor element 12 and the external lead 14 is made by a wiring pattern (not shown) inside the ceramic package 11.

【0004】[0004]

【発明が解決しようとする課題】上述のような従来のマ
ルチチップ・モジュールにおいて、半導体素子から生ず
る熱の伝導に関しては、基板を介してパッケージに熱を
伝達する方法、或いは、半導体素子等から直接熱をパッ
ケージに伝達させる方法があるが、いずれの方法におい
ても、基板及びパッケージは熱抵抗が高いため(特に、
図4に示したプラスチックパッケージ7は熱抵抗が高
い)、熱伝導率の低下の原因となる。
Regarding the conduction of heat generated from the semiconductor element in the conventional multi-chip module as described above, the heat is transferred to the package through the substrate, or the semiconductor element is directly connected to the package. There is a method to transfer heat to the package, but in either method, the board and the package have high thermal resistance (especially,
The plastic package 7 shown in FIG. 4 has a high thermal resistance), which causes a decrease in thermal conductivity.

【0005】即ち、図4のような従来の両面実装のマル
チチップ・モジュール用基板においては、表裏両面に半
導体素子2を搭載して実装密度を上げることは可能であ
るが、マルチチップ・モジュール用基板からの熱の放散
性に問題があった。また、図4のような両面実装のマル
チチップ・モジュール用基板はプラスチックパッケージ
であるため、熱伝導性が悪く、消費電力の大きなものに
は適用することができない。
That is, in the conventional double-sided mounting multi-chip module substrate as shown in FIG. 4, it is possible to mount the semiconductor elements 2 on both front and back surfaces to increase the mounting density. There was a problem in heat dissipation from the substrate. Further, since the double-sided mounting multichip module substrate as shown in FIG. 4 is a plastic package, it has poor thermal conductivity and cannot be applied to a device with large power consumption.

【0006】一方、図5のような従来のセラミックパッ
ケージを用いたマルチチップ・モジュール用基板におい
ては、半導体素子12の熱はセラミックパッケージ11
自体を介して放熱フィン17により放熱されるので放熱
性は良好であるが、セラミックパッケージ11の片面し
か半導体素子12を実装できないため、実装密度を上げ
ることが困難である。
On the other hand, in the conventional multi-chip module substrate using the ceramic package as shown in FIG. 5, the heat of the semiconductor element 12 is the ceramic package 11.
The heat radiation is good through the heat radiation fins 17 through itself, but the heat radiation is good, but it is difficult to increase the packaging density because the semiconductor elements 12 can be mounted on only one side of the ceramic package 11.

【0007】そこで、本発明は、基板の両面に半導体素
子を搭載して基板面を有効に利用して実装密度を上げる
ことができ、且つ放熱の良好なマルチチップ・モジュー
ル用基板を提供することを目的とする。
Therefore, the present invention provides a substrate for a multi-chip module, in which semiconductor elements are mounted on both sides of the substrate, the substrate surfaces can be effectively used to increase the mounting density, and the heat dissipation is good. With the goal.

【0008】[0008]

【課題を解決するための手段】このような課題を解決す
るために、請求項1によれば、図3に示すように、放熱
用の金属板23を少なくとも2枚のアルミナ積層基板2
1、22で挟んで同時焼成して一体化し、両面に半導体
素子26を実装可能とした基板20を具備することを特
徴とするマルチチップ・モジュール用基板が提供され
る。
In order to solve such a problem, according to claim 1, as shown in FIG. 3, at least two alumina laminated substrates 2 for heat dissipation are provided.
A substrate for a multi-chip module is provided, which is provided with a substrate 20 sandwiched between Nos. 1 and 22 and co-fired to be integrated so that a semiconductor element 26 can be mounted on both surfaces.

【0009】請求項2によれば、図3において、前記ア
ルミナ積層基板21、22に基板20の面から金属板2
3に至るスルーホールに熱伝導性の良好の物質を充填し
て成るサーマルビア28を設けたことを特徴とする請求
項1に記載のマルチチップ・モジュール用基板が提供さ
れる。請求項3によれば、図1及び図3に示すように、
放熱用の金属板23を少なくとも2枚のアルミナ積層基
板21、22で挟んで同時焼成して一体化し、両面に半
導体素子26を実装した基板20と、内部にサーマルビ
ア32を有し且つ前記基板20を実装した際に基板20
の金属板23の少なくとも一部が該サーマルビア32に
接続するように構成したセラミックパッケージ29と、
前記サーマルビア32に接続するように該セラミックパ
ッケージ29に取付けられた放熱部材36とを含んでな
ることを特徴とするマルチチップ・モジュールが提供さ
れる。
According to claim 2, in FIG. 3, the metal plate 2 is formed on the alumina laminated substrates 21 and 22 from the surface of the substrate 20.
The substrate for a multi-chip module according to claim 1, wherein the through holes up to 3 are provided with thermal vias 28 formed by filling a material having a good thermal conductivity. According to claim 3, as shown in FIGS. 1 and 3,
A substrate 20 having a metal plate 23 for heat radiation sandwiched between at least two alumina laminated substrates 21 and 22 and simultaneously fired to be integrated, and a semiconductor element 26 mounted on both surfaces, and a thermal via 32 inside and the substrate 20. Board 20 when 20 is mounted
A ceramic package 29 configured such that at least a part of the metal plate 23 is connected to the thermal via 32,
A multi-chip module is provided, which includes a heat dissipation member 36 attached to the ceramic package 29 so as to be connected to the thermal via 32.

【0010】[0010]

【作用】請求項1によれば、基板の両面に搭載した半導
体素子26の熱は、アルミナ積層基板21、22と一体
を成す金属板23を介して効率良く放熱されるので、実
装密度が高く、しかも放熱性の良いマルチチップ・モジ
ュールを得ることができる。
According to the present invention, the heat of the semiconductor elements 26 mounted on both surfaces of the substrate is efficiently radiated through the metal plate 23 which is integrated with the alumina laminated substrates 21 and 22, so that the mounting density is high. Moreover, it is possible to obtain a multi-chip module having good heat dissipation.

【0011】請求項2によれば、基板20の両面に搭載
した半導体素子26の熱は、サーマルビア28を介して
金属板に伝わるので、より一層効率良く放熱される。請
求項3によれば、基板20の両面に搭載した半導体素子
の熱は、アルミナ積層基板21、22と一体を成す金属
板23を介して効率良く放熱され、更にセラミックパッ
ケージのサーマルビア32を介して放熱部材36に放熱
されるので、実装密度が高く放熱性の良好なマルチチッ
プ型半導体装置が得られる。請求項3において、請求項
2のように、基板20のアルミナ積層基板21、22に
サーマルビア28を設けると放熱性が一層良好となる。
According to the second aspect, the heat of the semiconductor elements 26 mounted on both surfaces of the substrate 20 is transferred to the metal plate through the thermal vias 28, so that the heat is radiated more efficiently. According to claim 3, the heat of the semiconductor elements mounted on both sides of the substrate 20 is efficiently radiated through the metal plate 23 which is integrated with the alumina laminated substrates 21 and 22, and further through the thermal vias 32 of the ceramic package. Since the heat is radiated to the heat dissipation member 36, a multi-chip type semiconductor device having a high packaging density and good heat dissipation can be obtained. In claim 3, when the thermal vias 28 are provided in the alumina laminated substrates 21 and 22 of the substrate 20 as in claim 2, the heat dissipation is further improved.

【0012】[0012]

【実施例】以下、図1〜図3を参照して本発明の実施例
を詳細に説明する。図1は本発明のマルチチップ・モジ
ュール用基板の断面図である。図2(a)、(b)及び
(c)は本発明で使用する基板を示す平面(表面)図、
裏面図及び断面図である。図3は本発明のマルチチップ
・モジュール用基板の部分拡大断面図である。
Embodiments of the present invention will be described in detail below with reference to FIGS. FIG. 1 is a sectional view of a substrate for a multichip module of the present invention. 2A, 2B and 2C are plan (surface) views showing a substrate used in the present invention,
It is a back view and a sectional view. FIG. 3 is a partially enlarged sectional view of the substrate for a multichip module of the present invention.

【0013】まず、図2において、2枚の矩形平板状の
アルミナ積層基板21、22の間に、これらのアルミナ
基板21、22と熱膨張係数の近い放熱用の金属板、例
えばコバール板などのような熱伝導性の良好な金属板2
3をサンドイッチ状に挟み、同時焼成することにより熱
伝導性の良好な基板20を作成する。金属板23は、ア
ルミナ積層基板21、22と同様に略矩形の平板である
が、4隅にこれらのアルミナ積層基板21、22より外
側へ突き出した部分23aを有する。これらの突出し部
分23aは後述のように基板20からの熱の逃すための
ものである。
First, as shown in FIG. 2, between two rectangular flat plate-shaped alumina laminated substrates 21 and 22, a metal plate for heat dissipation, such as a Kovar plate, which has a thermal expansion coefficient close to those of the alumina substrates 21 and 22. Metal plate with good thermal conductivity 2
3 is sandwiched and co-fired to form a substrate 20 having good thermal conductivity. The metal plate 23 is a substantially rectangular flat plate like the alumina laminated substrates 21 and 22, but has portions 23a protruding outward from the alumina laminated substrates 21 and 22 at four corners. These protruding portions 23a are for releasing heat from the substrate 20 as described later.

【0014】基板20の最上面(アルミナ積層基板21
上)には、部品実装用の導体パターン(図示せず)以外
に、特に周囲部において、図2(a)に示すようにはん
だバンプ24が設けられ、後述のように、セラミックパ
ッケージとの間でバンプ接続が行われる。一方、基板2
0の最下面(アルミナ積層基板22上)にも、部品実装
用の導体パターン(図示せず)以外に、特に周囲部にお
いて、図2(b)に示すようにワイヤボンディング用の
導体パッド25が設けられ、後述のように、セラミック
パッケージとの間でワイヤボンディングにより接続され
る。
The uppermost surface of the substrate 20 (alumina laminated substrate 21)
In the upper part, in addition to a conductor pattern (not shown) for mounting components, solder bumps 24 are provided as shown in FIG. The bump connection is done with. On the other hand, substrate 2
On the lowermost surface of 0 (on the alumina laminated substrate 22), in addition to the conductor pattern (not shown) for mounting components, the conductor pads 25 for wire bonding as shown in FIG. It is provided and is connected to the ceramic package by wire bonding as described later.

【0015】図3は、基板20の表裏両面(アルミナ積
層基板21、22)上に半導体素子26をボンディング
ワイヤ27により実装した状態を拡大して示す。アルミ
ナ基板21、22には各半導体素子26の位置に対応し
て半導体素子26からコバールの金属板23まで延びる
サーマルビア28が設けてある。これらのサーマルビア
28はアルミナ基板21、22を貫通するスルーホール
に熱伝導性の良好な物質、例えば金属粉などを詰めたも
のであり、半導体素子26の熱を金属板23に放熱する
役目をする。
FIG. 3 is an enlarged view showing a state in which the semiconductor element 26 is mounted on both front and back surfaces (alumina laminated substrates 21 and 22) of the substrate 20 by the bonding wires 27. The alumina substrates 21 and 22 are provided with thermal vias 28 corresponding to the positions of the semiconductor elements 26 and extending from the semiconductor elements 26 to the Kovar metal plate 23. These thermal vias 28 are formed by filling through holes penetrating the alumina substrates 21 and 22 with a substance having good thermal conductivity, such as metal powder, and have a role of radiating the heat of the semiconductor element 26 to the metal plate 23. To do.

【0016】図1は、QFPタイプの半導体パッケージ
であって、半導体素子26を実装した基板20をセラミ
ックパッケージ29に搭載した状態を示す。セラミック
パッケージ29には、基板20を搭載するための2つの
段差部分がある。即ち、表面側アルミナ基板21のはん
だバンプ24を接続するための段差部30及び金属板2
3の突出し部分23aが接触するための段差部31であ
る。段差部31にはセラミックパッケージ29を貫通す
るサーマルビア32が形成されている。したがって、基
板20のはんだバンプ24がセラミックパッケージ29
の段差部30に形成された導体部とはんだ付けによって
接続され、これによって基板20側とセラミックパッケ
ージ29側との間の電気的な接続が行なわれる。また同
時に金属板23の突出し部分23aがセラミックパッケ
ージ29の段差部31にあるサーマルビア32に高温は
んだ又は熱伝導率の高い接着材等により接続される。一
方、裏面側アルミナ基板22のボンディング用のバッド
25はワイヤボンディング33によりセラミックパッケ
ージ29の導体部に接続される。
FIG. 1 shows a QFP type semiconductor package in which a substrate 20 on which a semiconductor element 26 is mounted is mounted on a ceramic package 29. The ceramic package 29 has two step portions for mounting the substrate 20. That is, the step portion 30 and the metal plate 2 for connecting the solder bumps 24 of the front side alumina substrate 21.
3 is a step portion 31 with which the protruding portion 23a of 3 contacts. A thermal via 32 penetrating the ceramic package 29 is formed in the step portion 31. Therefore, the solder bumps 24 of the substrate 20 may be connected to the ceramic package 29.
The conductor portion formed on the stepped portion 30 is connected by soldering, and thereby the electric connection is made between the substrate 20 side and the ceramic package 29 side. At the same time, the protruding portion 23a of the metal plate 23 is connected to the thermal via 32 in the step portion 31 of the ceramic package 29 by high-temperature solder or an adhesive having high thermal conductivity. On the other hand, the bonding pad 25 of the back side alumina substrate 22 is connected to the conductor portion of the ceramic package 29 by wire bonding 33.

【0017】セラミックパッケージ29には外部リード
34が接続され、基板20の側はキャップ35によりカ
バーされる。また、セラミックパッケージ29の基板2
0とは反対側の面には放熱フィン36が接続される。こ
れにより、半導体素子26からの熱はサーマルビア28
を通って金属板23に放熱され、更にセラミックパッケ
ージ29のサーマルビア32を介して放熱フィン36に
より外部に効率良く放熱される。
External leads 34 are connected to the ceramic package 29, and the side of the substrate 20 is covered with a cap 35. In addition, the substrate 2 of the ceramic package 29
A radiation fin 36 is connected to the surface opposite to 0. As a result, the heat from the semiconductor element 26 is transferred to the thermal via 28.
The heat is dissipated to the metal plate 23 through the through holes, and is further efficiently dissipated to the outside by the heat dissipating fins 36 through the thermal vias 32 of the ceramic package 29.

【0018】[0018]

【発明の効果】以上説明したように、本発明によれば、
複数の半導体素子が高密度に実装可能で、大電力を消費
するマルチチップ・モジュールにおいても、基板の両面
に部品を高密度に搭載することができ、且つ放熱性の良
好な半導体装置が得られる。
As described above, according to the present invention,
Multiple semiconductor elements can be mounted at high density, and even in a multi-chip module that consumes a large amount of power, it is possible to mount components on both sides of the board at high density and obtain a semiconductor device with good heat dissipation. .

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のマルチチップ・モジュールの断面図で
ある。
FIG. 1 is a cross-sectional view of a multichip module of the present invention.

【図2】(a)は本発明で用いるマルチチップ・モジュ
ール用基板の平面(表面)図、(b)は同基板の裏面
図、(c)は同基板の断面図である。
2A is a plan (front) view of a substrate for a multichip module used in the present invention, FIG. 2B is a rear view of the substrate, and FIG. 2C is a sectional view of the substrate.

【図3】本発明で用いるマルチチップ・モジュール用基
板に半導体素子を搭載した状態を示す拡大断面図であ
る。
FIG. 3 is an enlarged cross-sectional view showing a state in which a semiconductor element is mounted on a substrate for a multi-chip module used in the present invention.

【図4】従来のマルチチップ・モジュールの一例(特
に、プラスチックパッケージ)を示す断面図である。
FIG. 4 is a sectional view showing an example of a conventional multi-chip module (particularly, a plastic package).

【図5】従来のマルチチップ・モジュールの他の例(特
に、セラミックパッケージ)を示す断面図である。
FIG. 5 is a cross-sectional view showing another example of a conventional multi-chip module (particularly, a ceramic package).

【符号の説明】 20…基板 21,22…アルミナ積層基板 23…金属(コバール)板 24…はんだバンプ 25…ボンディングパッド 26…半導体素子 27…ワイヤ 28…サーマルビア 29…セラミックパッケージ 30,31…段差 32…サーマルビア 33…ワイヤ 34…リード 35…キャップ 36…放熱フィン[Explanation of Codes] 20 ... Substrate 21, 22 ... Alumina Laminated Substrate 23 ... Metal (Kovar) Plate 24 ... Solder Bump 25 ... Bonding Pad 26 ... Semiconductor Element 27 ... Wire 28 ... Thermal Via 29 ... Ceramic Package 30, 31 ... Step 32 ... Thermal via 33 ... Wire 34 ... Lead 35 ... Cap 36 ... Radiating fin

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 放熱用の金属板(23)を少なくとも2
枚のアルミナ積層基板(21、22)で挟んで同時焼成
して一体化し、両面に半導体素子(26)を実装可能と
した基板(20)を具備することを特徴とするマルチチ
ップ・モジュール用基板。
1. At least two metal plates (23) for heat dissipation are provided.
A substrate for a multi-chip module, comprising a substrate (20) sandwiched between a plurality of alumina laminated substrates (21, 22) and simultaneously fired to be integrated, and a semiconductor element (26) can be mounted on both surfaces. .
【請求項2】 前記アルミナ積層基板(21、22)に
基板(20)の面から金属板(23)に至るスルーホー
ルに熱伝導性の良好の物質を充填して成るサーマルビア
(28)を設けたことを特徴とする請求項1に記載のマ
ルチチップ・モジュール用基板。
2. A thermal via (28) formed by filling a through hole extending from the surface of the substrate (20) to the metal plate (23) with a substance having good thermal conductivity in the alumina laminated substrate (21, 22). The multi-chip module substrate according to claim 1, wherein the substrate is provided.
【請求項3】 放熱用の金属板(23)を少なくとも2
枚のアルミナ積層基板(21、22)で挟んで同時焼成
して一体化し、両面に半導体素子(26)を実装した基
板(20)と、内部にサーマルビア(32)を有し且つ
前記基板(20)を実装した際に基板(20)の金属板
(23)の少なくとも一部が該サーマルビア(32)に
接続するように構成したセラミックパッケージ(29)
と、前記サーマルビア(32)に接続するように該セラ
ミックパッケージ(29)に取付けられた放熱部材(3
6)とを含んでなることを特徴とするマルチチップ・モ
ジュール。
3. At least two metal plates (23) for heat dissipation are provided.
A substrate (20) sandwiched between a plurality of alumina laminated substrates (21, 22) and simultaneously fired to be integrated with each other and semiconductor elements (26) mounted on both sides, and a thermal via (32) inside the substrate (20). A ceramic package (29) configured such that at least a part of the metal plate (23) of the substrate (20) is connected to the thermal via (32) when the component (20) is mounted.
And a heat dissipation member (3) attached to the ceramic package (29) so as to be connected to the thermal via (32).
6) A multi-chip module comprising:
JP20979094A 1994-09-02 1994-09-02 Multi-chip module Withdrawn JPH0878616A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20979094A JPH0878616A (en) 1994-09-02 1994-09-02 Multi-chip module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20979094A JPH0878616A (en) 1994-09-02 1994-09-02 Multi-chip module

Publications (1)

Publication Number Publication Date
JPH0878616A true JPH0878616A (en) 1996-03-22

Family

ID=16578640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20979094A Withdrawn JPH0878616A (en) 1994-09-02 1994-09-02 Multi-chip module

Country Status (1)

Country Link
JP (1) JPH0878616A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000101018A (en) * 1998-09-25 2000-04-07 Shindengen Electric Mfg Co Ltd Electric device
US6285559B1 (en) 1998-05-26 2001-09-04 Nec Corporation Multichip module
JP2001284097A (en) * 2000-03-29 2001-10-12 Hitachi Medical Corp High voltage switching circuit and x-ray system using this circuit
WO2008108335A1 (en) * 2007-03-06 2008-09-12 Nikon Corporation Semiconductor device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6285559B1 (en) 1998-05-26 2001-09-04 Nec Corporation Multichip module
JP2000101018A (en) * 1998-09-25 2000-04-07 Shindengen Electric Mfg Co Ltd Electric device
JP2001284097A (en) * 2000-03-29 2001-10-12 Hitachi Medical Corp High voltage switching circuit and x-ray system using this circuit
JP4497640B2 (en) * 2000-03-29 2010-07-07 株式会社日立メディコ High voltage switch circuit and X-ray apparatus using the same
WO2008108335A1 (en) * 2007-03-06 2008-09-12 Nikon Corporation Semiconductor device
US8183686B2 (en) 2007-03-06 2012-05-22 Nikon Corporation Semiconductor device
JP5521546B2 (en) * 2007-03-06 2014-06-18 株式会社ニコン Semiconductor device
TWI456712B (en) * 2007-03-06 2014-10-11 尼康股份有限公司 Semiconductor device
US8878358B2 (en) 2007-03-06 2014-11-04 Nikon Corporation Semiconductor device
KR101477309B1 (en) * 2007-03-06 2014-12-29 가부시키가이샤 니콘 Semiconductor device

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