JPS56134747A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56134747A
JPS56134747A JP3979480A JP3979480A JPS56134747A JP S56134747 A JPS56134747 A JP S56134747A JP 3979480 A JP3979480 A JP 3979480A JP 3979480 A JP3979480 A JP 3979480A JP S56134747 A JPS56134747 A JP S56134747A
Authority
JP
Japan
Prior art keywords
substrate
chip
facedown
chips
constructed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3979480A
Other languages
Japanese (ja)
Other versions
JPS6041861B2 (en
Inventor
Miyoshi Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3979480A priority Critical patent/JPS6041861B2/en
Publication of JPS56134747A publication Critical patent/JPS56134747A/en
Publication of JPS6041861B2 publication Critical patent/JPS6041861B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain the device in high integration degree and high reliability by a method wherein a wiring film is formed on a substrate made of the same material as that of a semiconductor chip through an insulating film and fixedly attached on a packaged substrate, and a facedown junction of the chip is constructed. CONSTITUTION:An SiO2 film 11 is formed and gold films 12a, 12b are formed on the Si substrate 10. The facedown junctions of projecting electrodes 2a1, 2b1, 2a2, 2b2 of the Si chips 1a, 1b are constructed. Then, the Si substrate 10 is fixedly attached on the packaged substrate 14, and the gold films 12a, 12b on the substrate 10 are connected 16a, 16b at external connecting leads 17a, 17b and terminals 15a, 15b. With this construction, since a pattern can be formed finely on the flat Si substrate 10, the chips can be made integral in high density and also, a thermal strain is not produced due to the same quality as the chip, and the device can be attained in the high reliability.
JP3979480A 1980-03-25 1980-03-25 semiconductor equipment Expired JPS6041861B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3979480A JPS6041861B2 (en) 1980-03-25 1980-03-25 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3979480A JPS6041861B2 (en) 1980-03-25 1980-03-25 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS56134747A true JPS56134747A (en) 1981-10-21
JPS6041861B2 JPS6041861B2 (en) 1985-09-19

Family

ID=12562855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3979480A Expired JPS6041861B2 (en) 1980-03-25 1980-03-25 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6041861B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59117250A (en) * 1982-12-24 1984-07-06 Hitachi Micro Comput Eng Ltd Semiconductor device
FR2564244A1 (en) * 1984-05-14 1985-11-15 Gigabit Logic Inc MOUNTING STRUCTURE FOR FAST INTEGRATED CIRCUITS
WO1995000973A1 (en) * 1993-06-23 1995-01-05 Vlsi Technology, Inc. Electrically and thermally enhanced package using a separate silicon substrate
JPH08124967A (en) * 1994-10-21 1996-05-17 Nec Corp Semiconductor device
US5598031A (en) * 1993-06-23 1997-01-28 Vlsi Technology, Inc. Electrically and thermally enhanced package using a separate silicon substrate
KR100218259B1 (en) * 1996-11-22 1999-09-01 김덕중 Semiconductor package having a high pressure insulation structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59117250A (en) * 1982-12-24 1984-07-06 Hitachi Micro Comput Eng Ltd Semiconductor device
FR2564244A1 (en) * 1984-05-14 1985-11-15 Gigabit Logic Inc MOUNTING STRUCTURE FOR FAST INTEGRATED CIRCUITS
WO1995000973A1 (en) * 1993-06-23 1995-01-05 Vlsi Technology, Inc. Electrically and thermally enhanced package using a separate silicon substrate
US5598031A (en) * 1993-06-23 1997-01-28 Vlsi Technology, Inc. Electrically and thermally enhanced package using a separate silicon substrate
JPH08124967A (en) * 1994-10-21 1996-05-17 Nec Corp Semiconductor device
KR100218259B1 (en) * 1996-11-22 1999-09-01 김덕중 Semiconductor package having a high pressure insulation structure

Also Published As

Publication number Publication date
JPS6041861B2 (en) 1985-09-19

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