JPS5236985A - Method of connecting semiconductor devices etc. - Google Patents

Method of connecting semiconductor devices etc.

Info

Publication number
JPS5236985A
JPS5236985A JP50113326A JP11332675A JPS5236985A JP S5236985 A JPS5236985 A JP S5236985A JP 50113326 A JP50113326 A JP 50113326A JP 11332675 A JP11332675 A JP 11332675A JP S5236985 A JPS5236985 A JP S5236985A
Authority
JP
Japan
Prior art keywords
semiconductor devices
connecting semiconductor
devices etc
obtainable
embedded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50113326A
Other languages
Japanese (ja)
Inventor
Takao Yuri
Masahiro Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP50113326A priority Critical patent/JPS5236985A/en
Publication of JPS5236985A publication Critical patent/JPS5236985A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method of connecting semiconductor devices, etc. wherein semiconductor chips, etc. are embedded in the insulation layer formed on an insulation substrate, whereby a hybrid integrated circuit device of high reliability permitting high density packaging is obtainable.
COPYRIGHT: (C)1977,JPO&Japio
JP50113326A 1975-09-18 1975-09-18 Method of connecting semiconductor devices etc. Pending JPS5236985A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50113326A JPS5236985A (en) 1975-09-18 1975-09-18 Method of connecting semiconductor devices etc.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50113326A JPS5236985A (en) 1975-09-18 1975-09-18 Method of connecting semiconductor devices etc.

Publications (1)

Publication Number Publication Date
JPS5236985A true JPS5236985A (en) 1977-03-22

Family

ID=14609391

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50113326A Pending JPS5236985A (en) 1975-09-18 1975-09-18 Method of connecting semiconductor devices etc.

Country Status (1)

Country Link
JP (1) JPS5236985A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS523558A (en) * 1975-06-27 1977-01-12 Kobe Steel Ltd Automatic sheet thickness control device for rolling mill
JPS55118959A (en) * 1979-03-05 1980-09-12 Dow Corning Formation of molded product
JPS5722812A (en) * 1980-07-15 1982-02-05 Toshiba Corp Method for automatic control of plate thickness of multistand rolling mill
US4635356A (en) * 1984-12-28 1987-01-13 Kabushiki Kaisha Toshiba Method of manufacturing a circuit module

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS523558A (en) * 1975-06-27 1977-01-12 Kobe Steel Ltd Automatic sheet thickness control device for rolling mill
JPS55118959A (en) * 1979-03-05 1980-09-12 Dow Corning Formation of molded product
JPS6250287B2 (en) * 1979-03-05 1987-10-23 Dow Corning
JPS5722812A (en) * 1980-07-15 1982-02-05 Toshiba Corp Method for automatic control of plate thickness of multistand rolling mill
US4635356A (en) * 1984-12-28 1987-01-13 Kabushiki Kaisha Toshiba Method of manufacturing a circuit module

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