JPS5211862A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5211862A
JPS5211862A JP50088740A JP8874075A JPS5211862A JP S5211862 A JPS5211862 A JP S5211862A JP 50088740 A JP50088740 A JP 50088740A JP 8874075 A JP8874075 A JP 8874075A JP S5211862 A JPS5211862 A JP S5211862A
Authority
JP
Japan
Prior art keywords
semiconductor device
conductor wiring
micropattern
protected
damage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50088740A
Other languages
Japanese (ja)
Inventor
Masaharu Noyori
Isamu Kitahiro
Hiroaki Fujimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP50088740A priority Critical patent/JPS5211862A/en
Publication of JPS5211862A publication Critical patent/JPS5211862A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: By forming the conductor wiring pattern on an insulating substrate which makes the face down bonding of a semiconductor element through the anodic oxidation of a metalic layer, the damage on the conductor wiring surface shall be protected and the micropattern be made possible.
COPYRIGHT: (C)1977,JPO&Japio
JP50088740A 1975-07-18 1975-07-18 Semiconductor device Pending JPS5211862A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50088740A JPS5211862A (en) 1975-07-18 1975-07-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50088740A JPS5211862A (en) 1975-07-18 1975-07-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5211862A true JPS5211862A (en) 1977-01-29

Family

ID=13951303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50088740A Pending JPS5211862A (en) 1975-07-18 1975-07-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5211862A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61194732A (en) * 1985-02-22 1986-08-29 Casio Comput Co Ltd Method for jointing semiconductor pellet and substrate
US5341564A (en) * 1992-03-24 1994-08-30 Unisys Corporation Method of fabricating integrated circuit module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61194732A (en) * 1985-02-22 1986-08-29 Casio Comput Co Ltd Method for jointing semiconductor pellet and substrate
US5341564A (en) * 1992-03-24 1994-08-30 Unisys Corporation Method of fabricating integrated circuit module

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