JPS522173A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS522173A
JPS522173A JP7742775A JP7742775A JPS522173A JP S522173 A JPS522173 A JP S522173A JP 7742775 A JP7742775 A JP 7742775A JP 7742775 A JP7742775 A JP 7742775A JP S522173 A JPS522173 A JP S522173A
Authority
JP
Japan
Prior art keywords
semiconductor integrated
integrated circuit
circuit substrate
circuit
steps required
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7742775A
Other languages
Japanese (ja)
Inventor
Hiroyuki Miyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP7742775A priority Critical patent/JPS522173A/en
Publication of JPS522173A publication Critical patent/JPS522173A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To provide rational and efficient mutual wiring between semiconductor integrated circuit and circuit substrate.by reducing steps required for charging semiconductor integrated circuit to circuit substrate.
COPYRIGHT: (C)1977,JPO&Japio
JP7742775A 1975-06-23 1975-06-23 Semiconductor integrated circuit Pending JPS522173A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7742775A JPS522173A (en) 1975-06-23 1975-06-23 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7742775A JPS522173A (en) 1975-06-23 1975-06-23 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS522173A true JPS522173A (en) 1977-01-08

Family

ID=13633676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7742775A Pending JPS522173A (en) 1975-06-23 1975-06-23 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS522173A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5571091A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Multilayer circuit board
JPS60224401A (en) * 1984-04-24 1985-11-08 太昭農工機株式会社 Bearing apparatus in intertillage weeder
JPS63180402U (en) * 1987-05-14 1988-11-22
US5081563A (en) * 1990-04-27 1992-01-14 International Business Machines Corporation Multi-layer package incorporating a recessed cavity for a semiconductor chip
US5241456A (en) * 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5355102A (en) * 1990-04-05 1994-10-11 General Electric Company HDI impedance matched microwave circuit assembly
US5452182A (en) * 1990-04-05 1995-09-19 Martin Marietta Corporation Flexible high density interconnect structure and flexibly interconnected system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4996264A (en) * 1973-01-22 1974-09-12
JPS5013668B1 (en) * 1968-09-27 1975-05-21

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5013668B1 (en) * 1968-09-27 1975-05-21
JPS4996264A (en) * 1973-01-22 1974-09-12

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5571091A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Multilayer circuit board
JPS60224401A (en) * 1984-04-24 1985-11-08 太昭農工機株式会社 Bearing apparatus in intertillage weeder
JPS63180402U (en) * 1987-05-14 1988-11-22
US5355102A (en) * 1990-04-05 1994-10-11 General Electric Company HDI impedance matched microwave circuit assembly
US5452182A (en) * 1990-04-05 1995-09-19 Martin Marietta Corporation Flexible high density interconnect structure and flexibly interconnected system
US5081563A (en) * 1990-04-27 1992-01-14 International Business Machines Corporation Multi-layer package incorporating a recessed cavity for a semiconductor chip
US5241456A (en) * 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure

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