JPS6432662A - Structure of semiconductor package - Google Patents
Structure of semiconductor packageInfo
- Publication number
- JPS6432662A JPS6432662A JP62187525A JP18752587A JPS6432662A JP S6432662 A JPS6432662 A JP S6432662A JP 62187525 A JP62187525 A JP 62187525A JP 18752587 A JP18752587 A JP 18752587A JP S6432662 A JPS6432662 A JP S6432662A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- small substrate
- solder bumps
- surface electrodes
- small
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
PURPOSE:To reduce thermal stress applied to a thin-film electrode, and to prevent the disconnection of an aluminum wiring by making the difference of the thermal expansion coefficients of a semiconductor chip and a small substrate smaller than that of the small substrate and a large substrate. CONSTITUTION:Back electrodes 10 on a small substrate 2 and surface electrodes 11 on a wiring substrate 3 are connected by solder bumps, and a section between the small substrate 2 and the wiring substrate 3 is filled with a resin 6. The thermal expansion coefficient of the resin 6 is brought close to the value of the solder bumps 7, thus reducing thermal stress applied to the solder bumps 7. Through-hole conductors 5 are formed into the small substrate 2, and electrically connect the back electrodes 10 on the small substrate and surface electrodes 9 on the small substrate. Surface electrodes 8 on a semiconductor chip 1 and the surface electrodes 9 on the small substrate are connected by solder bumps 4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62187525A JPS6432662A (en) | 1987-07-29 | 1987-07-29 | Structure of semiconductor package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62187525A JPS6432662A (en) | 1987-07-29 | 1987-07-29 | Structure of semiconductor package |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6432662A true JPS6432662A (en) | 1989-02-02 |
Family
ID=16207606
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62187525A Pending JPS6432662A (en) | 1987-07-29 | 1987-07-29 | Structure of semiconductor package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6432662A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02307295A (en) * | 1989-05-23 | 1990-12-20 | Japan Radio Co Ltd | Junction of multilayer printed board |
US8178255B2 (en) * | 2007-02-06 | 2012-05-15 | Sanyo Electric Co., Ltd. | Fuel cell |
USRE44251E1 (en) | 1996-09-12 | 2013-06-04 | Ibiden Co., Ltd. | Circuit board for mounting electronic parts |
-
1987
- 1987-07-29 JP JP62187525A patent/JPS6432662A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02307295A (en) * | 1989-05-23 | 1990-12-20 | Japan Radio Co Ltd | Junction of multilayer printed board |
USRE44251E1 (en) | 1996-09-12 | 2013-06-04 | Ibiden Co., Ltd. | Circuit board for mounting electronic parts |
US8178255B2 (en) * | 2007-02-06 | 2012-05-15 | Sanyo Electric Co., Ltd. | Fuel cell |
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