GB2136203B - Through-wafer integrated circuit connections - Google Patents
Through-wafer integrated circuit connectionsInfo
- Publication number
- GB2136203B GB2136203B GB08305761A GB8305761A GB2136203B GB 2136203 B GB2136203 B GB 2136203B GB 08305761 A GB08305761 A GB 08305761A GB 8305761 A GB8305761 A GB 8305761A GB 2136203 B GB2136203 B GB 2136203B
- Authority
- GB
- United Kingdom
- Prior art keywords
- wafer
- device components
- integrated circuit
- circuit connections
- connections
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/85424—Aluminium (Al) as principal constituent
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/01013—Aluminum [Al]
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- H01L2924/01014—Silicon [Si]
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- H01L2924/01015—Phosphorus [P]
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- H01L2924/01028—Nickel [Ni]
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- H01L2924/01029—Copper [Cu]
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- H01L2924/01074—Tungsten [W]
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- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Integrated circuit device components are provided at a first surface of a semiconductor wafer either by formation directly within the wafer (1 - Fig. 2) or bonding a separate chip (15) to the wafer (12 - Fig. 3). The wafer is provided with discrete electrical connections (13 - Fig. 3) extending therethrough from the first to the opposite surface either by diffusion and etching (Figs. 2 and 3), or forming dielectrically insulated conductive islands. The device components are electrically connected to the discrete connections at the first surface and external metallisation, forming contact pads (8), is provided at the second surface so that the overall package can be directly mounted to a substrate. The device components are encapsulated by a passivating layer (11) on the first surface (Fig. 2), or a cover (16) bonded to the first surface (Fig. 3). The packaging technique is particularly applicable to very high power integrated circuits of large areas and high pin count. <IMAGE>
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08305761A GB2136203B (en) | 1983-03-02 | 1983-03-02 | Through-wafer integrated circuit connections |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08305761A GB2136203B (en) | 1983-03-02 | 1983-03-02 | Through-wafer integrated circuit connections |
Publications (3)
Publication Number | Publication Date |
---|---|
GB8305761D0 GB8305761D0 (en) | 1983-04-07 |
GB2136203A GB2136203A (en) | 1984-09-12 |
GB2136203B true GB2136203B (en) | 1986-10-15 |
Family
ID=10538872
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB08305761A Expired GB2136203B (en) | 1983-03-02 | 1983-03-02 | Through-wafer integrated circuit connections |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2136203B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8703603B2 (en) | 2003-09-15 | 2014-04-22 | Nuvotronics, Llc | Device package and methods for the fabrication and testing thereof |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3516954A1 (en) * | 1984-05-14 | 1985-11-14 | Gigabit Logic, Inc., Newbury Park, Calif. | MOUNTED INTEGRATED CIRCUIT |
US4617730A (en) * | 1984-08-13 | 1986-10-21 | International Business Machines Corporation | Method of fabricating a chip interposer |
US5051811A (en) * | 1987-08-31 | 1991-09-24 | Texas Instruments Incorporated | Solder or brazing barrier |
FR2629665B1 (en) * | 1988-03-30 | 1991-01-11 | Bendix Electronics Sa | ELECTRONIC CIRCUIT BOX |
JPH0215652A (en) * | 1988-07-01 | 1990-01-19 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
DE4318339A1 (en) * | 1993-06-02 | 1994-12-08 | Philips Patentverwaltung | Sealed via for a ceramic substrate of a thick-film circuit and a method for producing the same |
DE10229711B4 (en) * | 2002-07-02 | 2009-09-03 | Curamik Electronics Gmbh | Semiconductor module with microcooler |
US6825559B2 (en) | 2003-01-02 | 2004-11-30 | Cree, Inc. | Group III nitride based flip-chip intergrated circuit and method for fabricating |
JP4919984B2 (en) * | 2007-02-25 | 2012-04-18 | サムスン エレクトロニクス カンパニー リミテッド | Electronic device package and method for forming the same |
US10319654B1 (en) | 2017-12-01 | 2019-06-11 | Cubic Corporation | Integrated chip scale packages |
CN111599743B (en) * | 2020-07-06 | 2024-05-28 | 绍兴同芯成集成电路有限公司 | Method for producing wafer by combining composite adhesive film with through hole glass carrier plate structure |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3343256A (en) * | 1964-12-28 | 1967-09-26 | Ibm | Methods of making thru-connections in semiconductor wafers |
USB436421I5 (en) * | 1965-01-27 | |||
US3577037A (en) * | 1968-07-05 | 1971-05-04 | Ibm | Diffused electrical connector apparatus and method of making same |
DE1933731C3 (en) * | 1968-07-05 | 1982-03-25 | Honeywell Information Systems Italia S.p.A., Caluso, Torino | Method for producing a semiconductor integrated circuit |
DE2450902A1 (en) * | 1973-10-30 | 1975-05-07 | Gen Electric | ELECTRICAL LADDER IN SEMI-CONDUCTOR DEVICES |
-
1983
- 1983-03-02 GB GB08305761A patent/GB2136203B/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8703603B2 (en) | 2003-09-15 | 2014-04-22 | Nuvotronics, Llc | Device package and methods for the fabrication and testing thereof |
Also Published As
Publication number | Publication date |
---|---|
GB2136203A (en) | 1984-09-12 |
GB8305761D0 (en) | 1983-04-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |