JPS6489440A - Chip carrier - Google Patents

Chip carrier

Info

Publication number
JPS6489440A
JPS6489440A JP62243838A JP24383887A JPS6489440A JP S6489440 A JPS6489440 A JP S6489440A JP 62243838 A JP62243838 A JP 62243838A JP 24383887 A JP24383887 A JP 24383887A JP S6489440 A JPS6489440 A JP S6489440A
Authority
JP
Japan
Prior art keywords
chip
cap
warping
plate
solder balls
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62243838A
Other languages
Japanese (ja)
Inventor
Hiroaki Doi
Tadakatsu Nakajima
Shinji Sakata
Tatsuji Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62243838A priority Critical patent/JPS6489440A/en
Publication of JPS6489440A publication Critical patent/JPS6489440A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To decrease warping of a chip and to prevent breakdown due to strain yielded in solder balls, by soldering an Si plate to the upper surface of the cap of an LSI chip carrier. CONSTITUTION:An Si chip 1 is electrically connected to a wiring board 3 with solder balls 7. The Si chip 1 and an Si plate 8 are soldered to a cap 4 with brazing filler metals 6 and 8. When temperature is changed, warping due to the difference in linear expansion coefficients of the cap 4 and the chip 1 can be made small by the warping in the opposite direction due to the difference in linear expansion coefficients of the cap 4 and the Si plate 8. The warping of the Si chip 1 is decreased by this constitution. Breakdown due to strain yielded in the solder balls 7 is prevented.
JP62243838A 1987-09-30 1987-09-30 Chip carrier Pending JPS6489440A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62243838A JPS6489440A (en) 1987-09-30 1987-09-30 Chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62243838A JPS6489440A (en) 1987-09-30 1987-09-30 Chip carrier

Publications (1)

Publication Number Publication Date
JPS6489440A true JPS6489440A (en) 1989-04-03

Family

ID=17109696

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62243838A Pending JPS6489440A (en) 1987-09-30 1987-09-30 Chip carrier

Country Status (1)

Country Link
JP (1) JPS6489440A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07201921A (en) * 1993-11-25 1995-08-04 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07201921A (en) * 1993-11-25 1995-08-04 Nec Corp Semiconductor device

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