JPS6231498B2 - - Google Patents

Info

Publication number
JPS6231498B2
JPS6231498B2 JP53115342A JP11534278A JPS6231498B2 JP S6231498 B2 JPS6231498 B2 JP S6231498B2 JP 53115342 A JP53115342 A JP 53115342A JP 11534278 A JP11534278 A JP 11534278A JP S6231498 B2 JPS6231498 B2 JP S6231498B2
Authority
JP
Japan
Prior art keywords
lead
conductor layer
semiconductor device
metal
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53115342A
Other languages
Japanese (ja)
Other versions
JPS5541760A (en
Inventor
Katsuhiko Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP11534278A priority Critical patent/JPS5541760A/en
Publication of JPS5541760A publication Critical patent/JPS5541760A/en
Publication of JPS6231498B2 publication Critical patent/JPS6231498B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は改良された半導体装置の構造に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved semiconductor device structure.

従来、低融点硝子封止気密容器を用いた半導体
装置は第１図に示された断面図に見られる如く、
セラミツク基板２の中央に設けられた半導体素子
６を接着する凹部９の底面に金ペーストによる金
属化導体層５を設け、且つ片面に低融点硝子３が
接着されたセラミツク基板２にリードフレーム１
２を取り付けた構造の容器に、半導体素子６を金
属化導体層５に金―シリコン合金を介在させて接
着し、金属細線７により内部リード１１と素子電
極とを結線した後に片面に低融点硝子３が接着さ
れたキヤツプ１により半導体素子を気密封止する
ものであつた。 Conventionally, a semiconductor device using an airtight container sealed with low melting point glass is as shown in the cross-sectional view shown in FIG.
A metallized conductor layer 5 made of gold paste is provided on the bottom of a recess 9 provided in the center of the ceramic substrate 2 to which a semiconductor element 6 is to be bonded, and a lead frame 1 is attached to the ceramic substrate 2 with a low melting point glass 3 bonded to one side.
2, a semiconductor element 6 is bonded to the metallized conductor layer 5 with a gold-silicon alloy interposed therebetween, and after connecting the internal lead 11 and the element electrode with the thin metal wire 7, a low melting point glass layer is attached on one side. The semiconductor element was hermetically sealed by the cap 1 to which the cap 3 was bonded.

然しながら従来の容器は単にセラミツク基板上
に低融点硝子でリードフレームが接着されている
だけであり、又金ペーストからなる素子接着用金
属化導体層にも予め接地用の接続部分が設けられ
ておらず、そのため素子接着用金属化導体層と任
意の内部リードとを電気的に接続（以下接地と呼
ぶ）する事が難しかつた。そこでこの種の容器を
接地して使用する場合には、第２図に示された断
面図に見られる如く、微小な金属板８を金属化導
体層５に接着して該金属板８とリードフレーム１
２の接地用リード１５とを金属細線７で接続し、
この金属板８及び金属細線７を介して金属化導体
層５と接地用リード１５との導通を行うようにし
ていた。 However, in conventional containers, a lead frame is simply bonded to a ceramic substrate using low-melting point glass, and the metallized conductor layer for bonding elements, which is made of gold paste, does not have a grounding connection part provided in advance. First, it has been difficult to electrically connect (hereinafter referred to as grounding) between the metallized conductor layer for device adhesion and any internal leads. Therefore, when using this type of container in a grounded manner, as shown in the cross-sectional view shown in FIG. frame 1
Connect the grounding lead 15 of No. 2 with the thin metal wire 7,
The metallized conductor layer 5 and the grounding lead 15 were electrically connected through the metal plate 8 and the thin metal wire 7.

従つて、かかる方法によつて金属化導体層５を
特定リードに接地する為には、金属板８の接着工
数を要する事、及び半導体装置としての信頼度の
低下等の欠点があつた。 Therefore, in order to ground the metallized conductor layer 5 to a specific lead by such a method, there are disadvantages such as the need for many man-hours for bonding the metal plate 8 and a decrease in the reliability of the semiconductor device.

本発明の目的は、上述した従来の欠点を除去し
信頼度の高い新規な半導体装置を提供することに
ある。 An object of the present invention is to eliminate the above-mentioned conventional drawbacks and provide a novel semiconductor device with high reliability.

即ち本発明に用いる容器は、半導体素子を搭載
する凹部を備えたセラミツク基板と、接地用リー
ドを含む内部リード及び外部リードを備えたリー
ドフレームと、前記半導体素子を封止するキヤツ
プと、前記基板及びキヤツプの間に設けられた前
記リードフレームを接着する低融点硝子とから成
り、リードフレームの中央にタイバーで吊られた
金属枠が、前記セラミツク基板の凹部底面に施さ
れた金属化導体層に低融点ろう材によつて接着さ
れ電気的に導通された構造である。 That is, the container used in the present invention includes a ceramic substrate having a recess for mounting a semiconductor element, a lead frame having internal and external leads including a grounding lead, a cap for sealing the semiconductor element, and the substrate. and a low melting point glass that adheres the lead frame provided between the caps, and a metal frame suspended by a tie bar in the center of the lead frame is attached to the metallized conductor layer applied to the bottom of the recess of the ceramic substrate. The structure is bonded and electrically conductive using a low melting point brazing material.

従つて本発明に係る容器は、従来の容器に比較
し、リードフレームを容器に接着する時に同時に
接地用金属枠も接着されるので、接地用金属板の
接着と接続工数が不要となるばかりでなく、任意
の内部リードとをワイヤーボンデイングにより接
続できるので種々の半導体素子を搭載することが
できる。従つて容器のコストダウンが可能になる
とともに信頼性が高くなる。 Therefore, in the container according to the present invention, as compared to conventional containers, since the grounding metal frame is also bonded at the same time when the lead frame is bonded to the container, there is no need for bonding and connecting the grounding metal plate. Since it can be connected to any internal lead by wire bonding, various semiconductor elements can be mounted thereon. Therefore, the cost of the container can be reduced and reliability can be increased.

次に本発明を添付図面を参照しながらその良好
な実施例について説明しよう。第３図は本発明の
一つの実施例である半導体装置のキヤツプ封止前
の平面図、第４図は第３図をキヤツプ封止したＡ
―A′断面図、第５図はＢ―B′部分断面図を示す
ものである。 Next, preferred embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 3 is a plan view of a semiconductor device according to an embodiment of the present invention before the cap is sealed, and FIG. 4 is a plan view of the semiconductor device shown in FIG.
-A' sectional view, and FIG. 5 shows a BB' partial sectional view.

図に於いてセラミツク基板２のほぼ中央部には
凹部９が設けられている。凹部９の底面にはモリ
ブデン―マンガンメタライズ（金属化）された層
にニツケルメツキ及び金メツキを施して形成され
た金属化導体層５が設けられている。金属化導体
層５は前記モリブデン―マンガン層の代りに、タ
ングステンメタライズされたものにニツケルメツ
キ及び金メツキを施すか或いは金ペースト（例え
ばアルゼライトGCNo.―の商品名で市販されてい
る）で処理して形成しても良い。リードフレーム
１２′の構造は、中央に向つてほぼ放射状に伸び
る内部リード１１の先端部で囲まれた中央の空間
部に、0.3mm幅程度の金属枠１０がタイバー１３
の両端から内部タイバー１４によつて吊られてい
る。前記リードフレーム１２′の外部リード４を
折曲げて第４図及び第５図に示すような断面構造
に成形する。 In the figure, a recess 9 is provided approximately at the center of the ceramic substrate 2. A metallized conductor layer 5 is provided on the bottom surface of the recess 9, which is formed by applying nickel plating and gold plating to a molybdenum-manganese metallized layer. Instead of the molybdenum-manganese layer, the metallized conductor layer 5 is made of tungsten metallized with nickel plating and gold plating, or treated with gold paste (for example, commercially available under the trade name Alzerite GC No.). It may be formed by The structure of the lead frame 12' is such that a metal frame 10 with a width of about 0.3 mm is attached to tie bars 13 in a central space surrounded by the tips of internal leads 11 extending almost radially toward the center.
It is suspended from both ends by internal tie bars 14. The external leads 4 of the lead frame 12' are bent and formed into a cross-sectional structure as shown in FIGS. 4 and 5.

次に前記リードフレームの製造方法の一例につ
いて説明する。0.25mm厚で20〜40mm幅程度の帯状
の鉄―ニツケル合金の一面にアルミニウム、他面
に錫を真空蒸着法又はスパツタリング法により金
属薄膜を必要量蒸着させる。この鉄―ニツケル合
金をコイル状にし、アルミニウム面が外側になる
ようにして金属枠部をセラミツク基板の凹部に入
るようにリード面より下げてプレス成形加工す
る。 Next, an example of a method for manufacturing the lead frame will be described. A required amount of metal thin film is deposited on one side of a band-shaped iron-nickel alloy with a thickness of 0.25 mm and a width of about 20 to 40 mm with aluminum and tin on the other side by vacuum evaporation or sputtering. This iron-nickel alloy is formed into a coil, and with the aluminum surface facing outward, the metal frame is pressed below the lead surface so as to fit into the recess of the ceramic substrate.

次にこのリードフレーム１２′と前述したセラ
ミツク基板２をヒーターブロツク上で熱圧着させ
る。すなわち低融点硝子３が軟化流動する程度に
加熱したヒーターブロツク上にセラミツク基板２
をのせ、凹部９に窒素ブローしながら前記リード
フレームを位置合せして低融点硝子３で熱圧着し
て固着する際、金属化導体層５の金と金属枠１０
の下面に蒸着された錫とが金―錫合金をつくり、
金属化導体層５と金属枠１０との電気的導通が得
られる。このようにして得られた容器に半導体素
子６を金―シリコン合金（図示せず）を介在させ
て接着し、次いで素子電極と内部リード１１をそ
れぞれアルミニウム細線で結線すると供に接地す
べき素子電極から金属枠１０へ、更に金属枠１０
から接地すべきリード１５へ結線する。次にキヤ
ツプ１を用いて前記容器をベルト炉内で封入して
から外部リード部を錫などのメツキ処理をした後
タイバー切断をして半導体装置が完成する。 Next, this lead frame 12' and the aforementioned ceramic substrate 2 are bonded together by thermocompression on a heater block. That is, the ceramic substrate 2 is placed on a heater block heated to such an extent that the low melting point glass 3 softens and flows.
When aligning the lead frame while blowing nitrogen into the recess 9 and fixing it by thermocompression with the low melting point glass 3, the gold of the metallized conductor layer 5 and the metal frame 10
The tin deposited on the bottom surface of the gold-tin alloy creates a gold-tin alloy.
Electrical continuity between the metallized conductor layer 5 and the metal frame 10 is obtained. The semiconductor element 6 is adhered to the container obtained in this manner with a gold-silicon alloy (not shown) interposed therebetween, and then the element electrodes and the internal leads 11 are connected with thin aluminum wires, and the element electrodes to be grounded are connected. to the metal frame 10, and further to the metal frame 10.
Connect from the lead 15 to the lead 15 to be grounded. Next, the container is sealed in a belt furnace using the cap 1, and the external lead portions are plated with tin or the like and then cut with tie bars to complete the semiconductor device.

第６図は本発明の変形例を示す平面図、金属枠
１０を支える２本のタイバー１３のうちの１本を
接地リード１５に代え、又金属化導体層５′の周
辺から伸びた４個所の導体層に金属枠１０を接合
させたものである。 FIG. 6 is a plan view showing a modification of the present invention, in which one of the two tie bars 13 supporting the metal frame 10 is replaced with a ground lead 15, and four points extending from the periphery of the metallized conductor layer 5' are used. A metal frame 10 is bonded to the conductor layer.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装置の断面図、第２図は
金属板を用いて接地した従来の半導体装置の断面
図、第３図は本発明に係る半導体装置の一実施例
を示す平面図、第４図は第３図のキヤツプ封止し
た状態のＡ―A′断面図、第５図は同じくＢ―
B′部分断面図、第６図は本発明の変形例を示す平
面図である。 １……キヤツプ、２……セラミツク基板、３…
…低融点硝子、４……外部リード、５，５′……
金属化導体層、６……半導体素子、７……金属細
線、８……金属板、９……凹部、１０……金属
枠、１１……内部リード、１２，１２′……リー
ドフレーム、１３……タイバー、１４……内部タ
イバー、１５……接地用リード。 FIG. 1 is a sectional view of a conventional semiconductor device, FIG. 2 is a sectional view of a conventional semiconductor device grounded using a metal plate, and FIG. 3 is a plan view showing an embodiment of a semiconductor device according to the present invention. Figure 4 is a sectional view taken along line A-A' in Figure 3 with the cap sealed, and Figure 5 is a cross-sectional view taken along line B--
B' is a partial sectional view, and FIG. 6 is a plan view showing a modification of the present invention. 1...cap, 2...ceramic substrate, 3...
...Low melting point glass, 4...External lead, 5,5'...
Metallized conductor layer, 6... Semiconductor element, 7... Metal thin wire, 8... Metal plate, 9... Recess, 10... Metal frame, 11... Internal lead, 12, 12'... Lead frame, 13 ...Tie bar, 14...Internal tie bar, 15...Grounding lead.

Claims (1)

【特許請求の範囲】[Claims] １ セラミツク基板に凹部が設けられ、前記凹部
の底面に金属導体層が付着され、前記金属導体層
上に半導体素子が接着され、前記セラミツク基板
の上面に接地用リードが接着されている半導体装
置において、前記接地用リード又は内部タイバー
に一体化された金属枠を有し、前記金属枠が前記
半導体素子の周囲の凹部表面に固着され、前記半
導体素子と接地用リードが前記金属枠又は金属細
線を介して導通されていることを特徴とする半導
体装置。1. A semiconductor device in which a ceramic substrate is provided with a recess, a metal conductor layer is adhered to the bottom surface of the recess, a semiconductor element is adhered to the metal conductor layer, and a grounding lead is adhered to the upper surface of the ceramic substrate. , a metal frame is integrated with the grounding lead or the internal tie bar, the metal frame is fixed to the surface of the recess around the semiconductor element, and the semiconductor element and the grounding lead are connected to the metal frame or the metal thin wire. 1. A semiconductor device characterized in that conduction is established through a semiconductor device.
JP11534278A 1978-09-19 1978-09-19 Semiconductor device Granted JPS5541760A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11534278A JPS5541760A (en) 1978-09-19 1978-09-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11534278A JPS5541760A (en) 1978-09-19 1978-09-19 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5541760A JPS5541760A (en) 1980-03-24
JPS6231498B2 true JPS6231498B2 (en) 1987-07-08

Family

ID=14660160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11534278A Granted JPS5541760A (en) 1978-09-19 1978-09-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5541760A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6047699A (en) * 1983-08-26 1985-03-15 久保田　煕 Fructose separating method
JP2706077B2 (en) * 1988-02-12 1998-01-28 株式会社日立製作所 Resin-sealed semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
JPS5541760A (en) 1980-03-24

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