JPS634350B2 - - Google Patents
Info
- Publication number
- JPS634350B2 JPS634350B2 JP55119843A JP11984380A JPS634350B2 JP S634350 B2 JPS634350 B2 JP S634350B2 JP 55119843 A JP55119843 A JP 55119843A JP 11984380 A JP11984380 A JP 11984380A JP S634350 B2 JPS634350 B2 JP S634350B2
- Authority
- JP
- Japan
- Prior art keywords
- cap
- chip carrier
- sealing
- semiconductor device
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 19
- 238000007789 sealing Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 238000002844 melting Methods 0.000 claims description 4
- 239000003566 sealing material Substances 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 3
- 230000008018 melting Effects 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000005253 cladding Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000005394 sealing glass Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 229910000833 kovar Inorganic materials 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置、特にLID（Leadless
Inverted Device）の封止用キヤツプ構造の改良
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, particularly LID (Leadless
This invention relates to improvements in the sealing cap structure of Inverted Devices.
LID型半導体装置においては、セラミツクから
なるチツプキヤリアの凹所内に半導体素子をボン
デイングし、この凹所をキヤツプが密封的に封止
している。このようなLID型半導体装置はリード
端子をもたず、配線パターンを形成したマザーボ
ード上に上下逆転した状態、即ち半導体素子を接
着した凹所底面をマザーボードに対面させた状態
でリード端子の代りにチツプの各電極に連結する
ハンダバンプにより接合される。キヤツプの耐久
性、密封性等の点からキヤツプ材料として金属材
料を用いる場合があるが、この場合従来はキヤツ
プとチツプキヤリア間を金−錫合金からなる封着
材料で封止していた。従つて材料費が高価なもの
であつた。また、金属製キヤツプを用いた場合、
ハンダバンプが接合溶融時に金属製キヤツプ上に
濡れ上りキヤツプに接触して電極同士が短絡する
とい問題を生じていた。 In an LID type semiconductor device, a semiconductor element is bonded within a recess of a chip carrier made of ceramic, and this recess is hermetically sealed with a cap. Such LID type semiconductor devices do not have lead terminals, and instead of lead terminals, they are placed upside down on a motherboard on which a wiring pattern is formed, that is, with the bottom of the recess to which the semiconductor element is glued facing the motherboard. They are joined by solder bumps connected to each electrode of the chip. A metal material is sometimes used as the cap material from the viewpoint of the durability and sealability of the cap, but in this case, conventionally, the gap between the cap and the chip carrier has been sealed with a sealing material made of a gold-tin alloy. Therefore, the cost of materials was high. Also, when using a metal cap,
When the solder bumps are bonded and melted, they wet the metal cap and come into contact with the cap, causing a problem in which the electrodes short-circuit.
本発明は上記の点に鑑みなされたものであつ
て、LID型半導体装置のキヤツプ構造を改良する
ことによりコストの低減を計りまたマザーボード
上への搭載接合時にハンダバンプによる電極間短
絡を防止できる半導体装置の封着構造の提供を目
的とする。このため本発明においては、キヤツプ
としてチツプキヤリアと同程度の熱膨張係数を有
する金属板材を用い、キヤツプおよびチツプキヤ
リア間の封着材料としてチツプキヤリアと同程度
の熱膨張係数を有するフリツト系低融点ガラス材
料を用い、キヤツプの少くとも外側表面にキヤツ
プ封着時の熱により絶縁性金属酸化膜を形成して
いる。 The present invention has been made in view of the above points, and is a semiconductor device that can reduce costs by improving the cap structure of an LID type semiconductor device, and can prevent short circuits between electrodes due to solder bumps when mounting and bonding on a motherboard. The purpose is to provide a sealing structure for Therefore, in the present invention, a metal plate material having a coefficient of thermal expansion comparable to that of the chip carrier is used as the cap, and a frit-based low melting point glass material having a coefficient of thermal expansion comparable to that of the chip carrier is used as the sealing material between the cap and the chip carrier. An insulating metal oxide film is formed on at least the outer surface of the cap by the heat generated during cap sealing.
図面は本発明に係るLID型半導体装置の断面図
である。半導体装置本体を構成するチツプキヤリ
ア１はセラミツク板材の積層体であり中央部に凹
所２が形成される。この凹所２内に半導体素子３
が接合される。半導体素子３の各電極は金ワイヤ
４を介してチツプキヤリア１に形成した電極パタ
ーン（図示しない）に接続される。凹所２はセラ
ミツクと同程度の熱膨張係数を有するコバール又
は鉄−ニツケル合金等の金属材料からなるキヤツ
プ５で覆われる。このキヤツプ５は上記コバー
ル、セラミツク等と同程度の熱膨張係数を有する
フリツト系低融点封着ガラス６により凹所２を密
封してチツプキヤリア１に接合される。このチツ
プキヤリア１はこのチツプキヤリア内に設けた図
示しないスルーホールあるいは電極パターンを介
して半導体素子３の各電極と連結するハンダバン
プ８によりマザーボード７上に形成した配線パタ
ーン（図示しない）と接続される。キヤツプ５の
下面には予めアルミニウム薄膜からなるアルミニ
ウムクラツド層９を設けておく。このアルミニウ
ムクラツド層９はキヤツプ５の封着時あるいはそ
の他の熱処理工程において酸化され絶縁性酸化膜
となる。また、キヤツプ５の上面にもアルミニウ
ムクラツド層を設けてこれを酸化処理すれば封着
ガラス６による接合性が良好になる。 The drawing is a sectional view of an LID type semiconductor device according to the present invention. A chip carrier 1 constituting the main body of the semiconductor device is a laminate of ceramic plates, and a recess 2 is formed in the center. A semiconductor element 3 is placed inside this recess 2.
are joined. Each electrode of the semiconductor element 3 is connected to an electrode pattern (not shown) formed on the chip carrier 1 via a gold wire 4. The recess 2 is covered with a cap 5 made of a metal material such as Kovar or an iron-nickel alloy having a coefficient of thermal expansion similar to that of ceramic. The cap 5 is bonded to the chip carrier 1 with the recess 2 sealed by a frit type low melting point sealing glass 6 having a coefficient of thermal expansion comparable to that of Kovar, ceramic or the like. This chip carrier 1 is connected to a wiring pattern (not shown) formed on a motherboard 7 by solder bumps 8 which are connected to each electrode of the semiconductor element 3 via a through hole (not shown) provided in the chip carrier or an electrode pattern (not shown). An aluminum cladding layer 9 made of a thin aluminum film is previously provided on the lower surface of the cap 5. This aluminum cladding layer 9 is oxidized to become an insulating oxide film during sealing of the cap 5 or during other heat treatment steps. Further, if an aluminum cladding layer is also provided on the upper surface of the cap 5 and this is oxidized, the bondability with the sealing glass 6 will be improved.
以上のような半導体装置の封着構造を用いれ
ば、キヤツプの封着材料として安価な低融点ガラ
スを用いているためコスト低減が計れまたアルミ
ニウムクラツド層を添付したキヤツプを用いるこ
とによりこれが熱処理により酸化されて絶縁性酸
化膜が形成されハンダバンプのキヤツプ上への濡
れ上りによる電極間の短絡が防止される。 If the above-described sealing structure for semiconductor devices is used, costs can be reduced because inexpensive low-melting glass is used as the sealing material for the cap, and by using a cap with an aluminum cladding layer, this can be reduced by heat treatment. It is oxidized to form an insulating oxide film, which prevents short circuits between the electrodes due to wetting of the solder bump onto the cap.
図面は本発明に係るLID型半導体装置の断面図
である。
１……チツプキヤリア、２……凹所、３……半
導体素子、５……キヤツプ、６……封着ガラス、
９……アルミニウムクラツド層。
The drawing is a sectional view of an LID type semiconductor device according to the present invention. 1... Chip carrier, 2... Recess, 3... Semiconductor element, 5... Cap, 6... Sealing glass,
9...Aluminum cladding layer.
Claims (1)
凹所内に半導体素子を装着し、該凹所をキヤツプ
用板材で封止した半導体装置の封着構造におい
て、上記キヤツプとして上記チツプキヤリアと同
程度の熱膨張係数を有する金属板材を用い、該キ
ヤツプおよびチツプキヤリア間の封着材料として
上記チツプキヤリアと同程度の熱膨張係数を有す
るフリツト系低融点ガラス材料を用い、上記キヤ
ツプの少なくとも外側表面にキヤツプ封着時の熱
により絶縁性金属酸化膜を形成したことを特徴と
する半導体装置の封着構造。1. In a semiconductor device sealing structure in which a semiconductor element is mounted in a recess of a chip carrier constituting a main body of the semiconductor device, and the recess is sealed with a cap plate material, the cap has a coefficient of thermal expansion comparable to that of the chip carrier. A frit-based low melting point glass material having a coefficient of thermal expansion comparable to that of the chip carrier is used as the sealing material between the cap and the chip carrier, and at least the outer surface of the cap is heated by the heat during cap sealing. A sealing structure for a semiconductor device characterized by forming an insulating metal oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11984380A JPS5745262A (en) | 1980-09-01 | 1980-09-01 | Sealing and fitting structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11984380A JPS5745262A (en) | 1980-09-01 | 1980-09-01 | Sealing and fitting structure of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5745262A JPS5745262A (en) | 1982-03-15 |
| JPS634350B2 true JPS634350B2 (en) | 1988-01-28 |
Family
ID=14771630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11984380A Granted JPS5745262A (en) | 1980-09-01 | 1980-09-01 | Sealing and fitting structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5745262A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS594060A (en) * | 1982-06-30 | 1984-01-10 | Fujitsu Ltd | Semiconductor device |
| JPS6027433U (en) * | 1983-07-29 | 1985-02-25 | 松下電工株式会社 | Electronic component mounting structure |
| DE19808986A1 (en) * | 1998-03-03 | 1999-09-09 | Siemens Ag | Semiconductor component with several semiconductor chips |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5559746A (en) * | 1978-10-27 | 1980-05-06 | Hitachi Ltd | Semiconductor device and its mounting circuit device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53130974U (en) * | 1977-03-23 | 1978-10-17 |
-
1980
- 1980-09-01 JP JP11984380A patent/JPS5745262A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5559746A (en) * | 1978-10-27 | 1980-05-06 | Hitachi Ltd | Semiconductor device and its mounting circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5745262A (en) | 1982-03-15 |
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