JPS5745262A - Sealing and fitting structure of semiconductor device - Google Patents

Sealing and fitting structure of semiconductor device

Info

Publication number
JPS5745262A
JPS5745262A JP11984380A JP11984380A JPS5745262A JP S5745262 A JPS5745262 A JP S5745262A JP 11984380 A JP11984380 A JP 11984380A JP 11984380 A JP11984380 A JP 11984380A JP S5745262 A JPS5745262 A JP S5745262A
Authority
JP
Japan
Prior art keywords
cap
sealing
ceramic
melting point
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11984380A
Other languages
Japanese (ja)
Other versions
JPS634350B2 (en
Inventor
Toshio Hamano
Hidehiko Akasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11984380A priority Critical patent/JPS5745262A/en
Publication of JPS5745262A publication Critical patent/JPS5745262A/en
Publication of JPS634350B2 publication Critical patent/JPS634350B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent a short circuit between electrodes due to a solder bump by forming an insulating oxide film on an exterior surface of a cap consisting of a metallic material sealed and fitted to a chip carrier with glass with the low melting point. CONSTITUTION:With the chip carrier 1 consisting of the laminates of a ceramic board material, a concave section 2 is shaped at the central section, and a semiconductor element 3 is joined. An electrode of the semiconductor element 3 is connected to electrode patterns through gold wires 4. The concave section 2 is covered with the cap 5 in a Kovar or iron-nickel alloy having an approximately same thermal expansion coefficient as ceramic, and hermetically sealed with the frit group low melting point sealing and fitting glass 6 having the approximarely same thermal expansion coefficient as ceramic. An aluminum clad layer 9 composed of an aluminum thin-film is shaped onto a lower surface of the cap 5, oxidized in a heat treatment process such as sealing and fitting, and changed into the insulating oxide film.
JP11984380A 1980-09-01 1980-09-01 Sealing and fitting structure of semiconductor device Granted JPS5745262A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11984380A JPS5745262A (en) 1980-09-01 1980-09-01 Sealing and fitting structure of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11984380A JPS5745262A (en) 1980-09-01 1980-09-01 Sealing and fitting structure of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5745262A true JPS5745262A (en) 1982-03-15
JPS634350B2 JPS634350B2 (en) 1988-01-28

Family

ID=14771630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11984380A Granted JPS5745262A (en) 1980-09-01 1980-09-01 Sealing and fitting structure of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5745262A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0098176A2 (en) * 1982-06-30 1984-01-11 Fujitsu Limited The packaging of semiconductor chips
JPS6027433U (en) * 1983-07-29 1985-02-25 松下電工株式会社 Electronic component mounting structure
US6630727B1 (en) * 1998-03-03 2003-10-07 Infineon Technologies Ag Modularly expandable multi-layered semiconductor component

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53130974U (en) * 1977-03-23 1978-10-17
JPS5559746A (en) * 1978-10-27 1980-05-06 Hitachi Ltd Semiconductor device and its mounting circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53130974U (en) * 1977-03-23 1978-10-17
JPS5559746A (en) * 1978-10-27 1980-05-06 Hitachi Ltd Semiconductor device and its mounting circuit device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0098176A2 (en) * 1982-06-30 1984-01-11 Fujitsu Limited The packaging of semiconductor chips
EP0098176A3 (en) * 1982-06-30 1985-09-25 Fujitsu Limited The packaging of semiconductor chips
JPS6027433U (en) * 1983-07-29 1985-02-25 松下電工株式会社 Electronic component mounting structure
US6630727B1 (en) * 1998-03-03 2003-10-07 Infineon Technologies Ag Modularly expandable multi-layered semiconductor component

Also Published As

Publication number Publication date
JPS634350B2 (en) 1988-01-28

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