JPS55148445A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS55148445A
JPS55148445A JP5725379A JP5725379A JPS55148445A JP S55148445 A JPS55148445 A JP S55148445A JP 5725379 A JP5725379 A JP 5725379A JP 5725379 A JP5725379 A JP 5725379A JP S55148445 A JPS55148445 A JP S55148445A
Authority
JP
Japan
Prior art keywords
solder
metal
cap
coated
framelike
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5725379A
Other languages
Japanese (ja)
Inventor
Hideo Okamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5725379A priority Critical patent/JPS55148445A/en
Publication of JPS55148445A publication Critical patent/JPS55148445A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the short-circuit of conductors and the disconnection of a wire due to molten solder in a semiconductor device of the structure such that a cap and a stem having respectively metal portions to be coated with solder are sealed with framelike solder by forming an excessive solder absorbing metal in the inner periphery of the cap. CONSTITUTION:A metal 14 to be coated with solder is formed on the outer periphery of the surface of a ceramic cap substrate 13, and an excessive solder absorbing metal 15 having approx. 1mm wide is formed at an interval of 0.3-1mm on the inner periphery thereof to form a cap 12. A framelike solder 15 made of tin and lead eutectic solder or the like is placed on the metal to be coated with solder of the cap, a metal 17 to be coated with solder of a stem 16 mounted with a thin film substrate 19 such as a hybrid integrated circuit or the like is placed on the solder 15, and they are heated in a furnace so as to melt to seal the solder. Thus, since the molten solder 18 is adhered to the metal 15 even if it is flowed into the case during solder reflowing operation, it is not adhered to the conductor and wire 20 on a thin film substrate.
JP5725379A 1979-05-10 1979-05-10 Semiconductor device Pending JPS55148445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5725379A JPS55148445A (en) 1979-05-10 1979-05-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5725379A JPS55148445A (en) 1979-05-10 1979-05-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS55148445A true JPS55148445A (en) 1980-11-19

Family

ID=13050357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5725379A Pending JPS55148445A (en) 1979-05-10 1979-05-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS55148445A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60115247A (en) * 1983-11-28 1985-06-21 Fujitsu Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60115247A (en) * 1983-11-28 1985-06-21 Fujitsu Ltd Semiconductor device
US4626960A (en) * 1983-11-28 1986-12-02 Fujitsu Limited Semiconductor device having soldered bond between base and cap thereof

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